CN105446445B

CN105446445B - Digital circuit resetting method and signal generating device

Info

Publication number: CN105446445B
Application number: CN201510881284.4A
Authority: CN
Inventors: 叶松宏; 杨国威
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2007-10-11
Filing date: 2007-10-11
Publication date: 2020-12-01
Anticipated expiration: 2027-10-11
Also published as: CN105446445A; CN101409542A; CN101409542B

Abstract

The invention discloses a digital circuit resetting method and a signal generating device, wherein the method comprises the following steps: providing a clock signal to a digital circuit; maintaining the clock signal at a logic level according to a first prompt signal; generating a reset signal for resetting the digital circuit at a first predetermined time after maintaining the clock signal at a logic level, the reset signal lasting for a second predetermined time; and at a third preset time after the reset signal is generated, replying the clock signal according to a second prompt signal; the time interval between the first prompt signal and the second prompt signal can be determined according to a count value generated by a counter, and the third preset time is later than the second preset time.

Description

Digital circuit resetting method and signal generating device

The present application is a divisional application, and its original application is application number 200710180214.1, and its application date is 2007, 10 and 11, entitled "digital circuit resetting method and related signal generating device".

Technical Field

The present invention relates to a digital circuit, and more particularly, to a reset method and a related reset device for a digital circuit.

Background

Flip-flop (flip-flop) is a widely used logic circuit device in digital systems nowadays, and is used to store input data according to the positive edge or the negative edge of a clock signal, so as to achieve the effect of overall synchronization of the digital system. In the case of a Delay-type Flip-Flop (DFF), the DFF generally includes two signals, a synchronous signal and an asynchronous signal, the synchronous signal is a clock signal, and the asynchronous signal is a preset (preset) signal or reset (reset) signal (also called clear) signal). The preset state is that the output result of the trigger is maintained at a binary value 1 under the condition of no matter other input; while the reset state clears the output of the flip-flop to 0.

Generally, when an asynchronous signal is output to a flip-flop, two problems are encountered, namely, a problem of collision between a recovery timing of the asynchronous signal and a clock signal (i.e., a problem of propagation delay) and a problem of propagation delay of the asynchronous signal. For further explanation, please refer to fig. 1, in which fig. 1 is a diagram illustrating a relationship between a clock signal and a reset signal. In fig. 1, the reset signal RST is an asynchronous signal output to the flip-flop, and when the reset signal RST transitions from a low level to a high level (a portion of a dashed line in the figure) at the end of the reset, if the flip-flop is just triggered at the positive edge or the negative edge of the clock signal CLK, the flip-flop may generate an erroneous output result. In order to avoid this, the moment of ending the reset signal and the triggering time of the clock signal must be kept at a certain time difference, which greatly increases the difficulty in circuit design. The second problem is propagation delay (propagation delay), when a reset signal is transmitted to a plurality of flip-flops, the time for receiving the reset signal on each flip-flop is different due to the delay in signal propagation, so that some flip-flops receive the reset signal first to perform the reset operation, and some flip-flops have to wait for the next clock cycle (cycle) to be reset, thereby generating an output error. The conventional solution is to balance the propagation delay by adding a buffer (buffer), but this method causes the required buffer to increase with the increase of the number of flip-flops, and also causes unnecessary cost in terms of space and cost.

Disclosure of Invention

Therefore, one objective of the present invention is to provide a reset method for a digital circuit and a related signal generating apparatus, so as to solve the above-mentioned problems.

According to an embodiment of the present invention, a method for resetting a digital circuit is disclosed, the method comprising: providing a clock signal to a digital circuit; maintaining the clock signal at a logic level according to a first prompt signal; generating a reset signal to reset the digital circuit; and according to a second prompting signal, recovering the clock signal to the digital circuit.

According to an embodiment of the present invention, a signal generating apparatus for generating a clock signal and a reset signal to a digital circuit is disclosed, the signal generating apparatus comprising: a frequency controller for generating the clock signal to the digital circuit; and a reset signal control unit for generating a prompt signal to the frequency controller and generating the reset signal to the digital circuit; the reset signal control unit generates the reset signal to the digital circuit when the clock signal maintains a logic level.

According to an embodiment of the present invention, a method for resetting a digital circuit is disclosed, comprising: providing a clock signal to a digital circuit; maintaining the clock signal at a logic level according to a first prompt signal; generating a reset signal for resetting the digital circuit at a first predetermined time after maintaining the clock signal at a logic level, the reset signal lasting for a second predetermined time; and at a third preset time after the reset signal is generated, replying the clock signal according to a second prompt signal; the time interval between the first prompt signal and the second prompt signal can be determined according to a count value generated by a counter, and the third preset time is later than the second preset time.

According to an embodiment of the present invention, a signal generating apparatus is disclosed, the signal generating apparatus comprising: a frequency controller for generating a clock signal to the digital circuit; and a reset signal control unit for generating a first prompt signal to the frequency controller to maintain the clock signal at a logic level, and generating a reset signal to the digital circuit at a first predetermined time after maintaining the clock signal at the logic level to reset the digital circuit, the reset signal lasting for a second predetermined time; the reset signal control unit generates a second prompting signal to the frequency controller at a third preset time after generating a reset signal so as to reply the clock signal, and the time interval between the first prompting signal and the second prompting signal can be determined according to a count value generated by a counter, and the third preset time is later than the second preset time.

Drawings

FIG. 1 is a diagram of a relationship between a known clock signal and a reset signal.

FIG. 2 is a functional block diagram of a signal generator applied to a flip-flop according to a first embodiment of the present invention.

Fig. 3 is a diagram illustrating a relationship between the clock signal CLK and the reset signal RST in the signal generator shown in fig. 2.

FIG. 4 is a flowchart of generating a reset signal to a flip-flop using the signal generator shown in FIG. 2.

FIG. 5 is a block diagram of a signal generator applied to a plurality of flip-flops according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a signal generator applied to a plurality of flip-flops according to a third embodiment of the present invention.

Fig. 7 is a diagram illustrating a relationship between the clock signal CLK and the reset signal RST in the signal generator shown in fig. 6.

Description of the figures

Detailed Description

Referring to fig. 2, fig. 2 is a functional block diagram of a first embodiment of a signal generator 200 applied to a flip-flop 230 according to the present invention. The signal generator 200 includes a frequency controller 210 (e.g., a phase-locked loop PLL or a Delay-locked loop DLL) for generating a clock signal CLK to the Flip-Flop 230 (e.g., a Delay-type Flip-Flop (DFF)), and a reset signal control unit 220 for generating a reset signal RST to the Flip-Flop 230. In addition, the flip-flop 230 includes a data input terminal D for inputting data and an output terminal Q for outputting data. In this embodiment, the flip-flop 230 is a positive edge triggered flip-flop, and the reset signal RST is an asynchronous signal input to the flip-flop, and when the reset signal RST is at a low level (logic 0), the output Q of the flip-flop 230 is set to 0. Please note that the embodiments of the present invention do not limit the kind of the asynchronous signal. In the present embodiment, the signal generator 200 utilizes the reset signal control unit 220 to generate a reset signal (reset) RST to reset the flip-flop 230, and in other embodiments, a preset signal (preset) control unit may also be utilized to generate a preset signal to preset the flip-flop 230, which all fall within the scope of the present invention.

To further illustrate the embodiments of the present invention, please refer to fig. 3, in which fig. 3 is a schematic diagram illustrating a relative relationship between the clock signal CLK and the reset signal RST in the signal generator 200 shown in fig. 2. In the embodiment of the invention, when the flip-flop 230 is going to perform the reset operation, the reset signal control unit 220 provides a prompt signal S1 to the clock controller 210 to stop the clock signal CLK (as shown in fig. 3 at time T1) so that the clock signal is maintained at a logic level (logic 1 or logic 0), and then after a predetermined time (for example, at time T2 shown in fig. 3), the reset signal control unit 220 resets the flip-flop 230 (i.e., the reset signal RST is shifted from high to low), at which time the output Q of the flip-flop 230 is reset to 0; after a period of time (e.g., time T3 shown in fig. 3), the reset signal control unit 220 ends the reset operation (i.e., the reset signal RST is switched from the low level to the high level), and then the reset signal control unit 220 provides another prompt signal S2 to the clock controller 210, so that the clock controller 210 recovers the clock signal CLK (e.g., time T4 shown in fig. 3) to continue to perform the subsequent data read output operation. In the embodiment of the invention, the time interval from T1 to T4 may be determined by a counter generating a count value, and on the other hand, in other embodiments, the start timing of the clock signal CLK of the clock controller 210 (e.g., the time T4 shown in fig. 3) may be determined according to whether the reset signal RST is triggered by the positive edge or the negative edge (e.g., the time T3 shown in fig. 3).

Referring to fig. 4, fig. 4 is a flowchart illustrating the steps of generating the reset signal to the flip-flop according to the signal generator 200 shown in fig. 2, wherein the steps are summarized as follows:

step 410: according to a first indication signal, the clock controller 210 stops the clock signal CLK at time T1.

Step 420: the reset signal control unit 220 resets the flip-flop 230 at time T2.

Step 430: at time T3, the reset signal control unit 220 ends the reset operation of the flip-flop 230.

Step 440: according to a second indication signal, the clock controller 210 recovers the clock signal CLK at time T4.

On the other hand, the method of the present invention can also be applied to a plurality of flip-flops, please refer to fig. 5, in which fig. 5 is a functional block diagram illustrating a signal generator 500 applied to a plurality of flip-flops according to a second embodiment of the present invention. When the flip-

flops

531, 532, and 533 are to be reset, the clock signal CLK is stopped by the frequency controller 510 a while before the reset operation occurs, and the clock signal CLK is restarted a while after the reset operation is completed, so that the embodiment of the present invention does not have the phenomenon that the flip-flops receive the reset signal RST at different times due to the propagation delay.

Furthermore, the method of the present invention can also be applied to a synchronous reset (synchronous reset) input, referring to fig. 6 and fig. 7, fig. 6 is a functional block diagram illustrating a signal generator 600 applied to a plurality of flip-flops according to a third embodiment of the present invention. Fig. 7 is a diagram illustrating a relationship between the clock signal CLK and the reset signal RST in the signal generator 600 shown in fig. 6. In fig. 6, the input terminals D4, D5, and D6 of the flip-flops 641, 642, 643 are coupled to the output terminals Q1, Q2, and Q3 of the flip-

flops

631, 632, 633, respectively. When the flip-

flops

631, 632, and 633 perform the reset operation, the reset result (i.e., binary value 0) is inputted into the flip-flops 641, 642, and 643, so that the output terminals Q4, Q5, and Q6 of the flip-flops 641, 642, and 643 also output binary value 0 when the clock signal CLK performs edge triggering, thereby achieving the effect of synchronous reset. Referring to fig. 7, when the signal generator 600 performs the reset operation, the reset signal control unit 620 provides a prompt signal S1 to the frequency controller 610, so that the frequency controller 610 can stop the clock signal CLK in advance (as shown in fig. 7, time T1), and after a certain time (for example, time T2 shown in fig. 7), the reset signal control unit 620 performs the reset operation (i.e., the reset signal RST is switched from high to low), when the output terminals Q1, Q2 and Q3 of the flip-

flops

631 and 632 and 633 are cleared to 0; next, the clock controller 610 recovers the clock signal CLK according to the second clock signal S2 provided by the reset signal control unit 620 (e.g., at time T3 shown in fig. 7), and stops the clock signal CLK according to the third clock signal S3 provided by the reset signal control unit 620 after a certain clock period (e.g., two clock periods TCLK) (e.g., at time T4 shown in fig. 7). Please note that, since the clock signal CLK is restored by the clock controller 610, the flip-flops 641, 642 and 643 record the values of the input terminals D4, D5 and D6 (i.e., the reset value 0) to the output terminals Q4, Q5 and Q6 due to the edge triggering of the clock signal CLK, thereby completing the synchronous reset operation. Next, after a certain period of time (e.g., time T5 shown in fig. 7), the reset signal control unit 620 ends the reset operation (i.e., the reset signal RST is switched from the low level to the high level). After the flip-

flops

631, 632, 633, 634, 635 and 636 complete the reset operation, the clock controller 610 recovers the clock signal CLK according to the fourth prompt signal S4 provided by the reset signal control unit 620 (as shown in fig. 7 at time T6), and performs the subsequent data reading and outputting operations.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A method for resetting a digital circuit includes:

providing a clock signal to a digital circuit;

maintaining the clock signal at a logic level according to a first prompt signal;

generating a reset signal for resetting the digital circuit at a first predetermined time after maintaining the clock signal at a logic level, the reset signal lasting for a second predetermined time; and recovering the clock signal according to a second prompt signal at a third preset time after the reset signal is generated;

the time interval between the first prompt signal and the second prompt signal is determined according to a count value generated by a counter, and the third preset time is later than the second preset time.

2. The method of claim 1, wherein the second hint signal is generated based on the count value.

3. The method of claim 1, wherein the second cue signal is generated according to the reset signal.

4. The method of claim 1, wherein the reset signal is an asynchronous reset signal or a synchronous reset signal.

5. A signal generating device, the generating device comprising:

a frequency controller for generating a clock signal to a digital circuit; and

a reset signal control unit for generating a first prompt signal to the frequency controller to make the frequency controller maintain the clock signal at a logic level, and generating a reset signal to the digital circuit at a first predetermined time after maintaining the clock signal at the logic level to reset the digital circuit, the reset signal lasting for a second predetermined time;

the reset signal control unit generates a second prompting signal to the frequency controller at a third preset time after generating a reset signal so as to recover the clock signal, and the time interval between the first prompting signal and the second prompting signal is determined according to a count value generated by a counter, and the third preset time is later than the second preset time.

6. The signal generating apparatus according to claim 5, wherein the reset signal control unit generates the clock signal to the clock controller to maintain the clock signal at the logic level.

7. The signal generating apparatus of claim 5, wherein the digital circuit comprises a first flip-flop and a second flip-flop, the clock signal is outputted to the first flip-flop and the second flip-flop, and an input terminal of the second flip-flop is coupled to an output terminal of the first flip-flop.

8. The signal generating apparatus according to claim 7, wherein the first flip-flop is a delay flip-flop.

9. The signal generating apparatus according to claim 5, wherein the reset signal control unit generates the second prompt signal according to the count value.

10. The apparatus according to claim 5, wherein the frequency controller is a phase-locked loop or a delay-locked loop.