CN101409542B

CN101409542B - The remapping method of digital circuit and apparatus for generating relevant signal

Info

Publication number: CN101409542B
Application number: CN200710180214.1A
Authority: CN
Inventors: 叶松宏; 杨国威
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2007-10-11
Filing date: 2007-10-11
Publication date: 2016-01-20
Anticipated expiration: 2027-10-11
Also published as: CN105446445A; CN101409542A; CN105446445B

Abstract

The present invention discloses a kind of remapping method of digital circuit, and the method comprises: provide clock signal to digital circuit; According to one first cue, maintain this clock signal in a logic level; Produce a reset signal, reset this digital circuit; And according to one second cue, reply this clock signal to this digital circuit.

Description

The remapping method of digital circuit and apparatus for generating relevant signal

Technical field

The present invention relates to a kind of digital circuit, particularly relate to a kind of remapping method of digital circuit and relevant reset apparatus.

Background technology

Trigger (flip-flop) is the logic circuit apparatus of a kind of widespread use in digital display circuit now, is used for according to the positive edge of clock signal or negative edge to store the data of input, to reach the effect of digital display circuit Integral synchronous.With delayed type trigger (Delay-typeFlipFlop, DFF), usually a synchronizing signal is included and an asynchronous signal two kinds of signals carry out control trigger, synchronizing signal is a clock signal, and asynchronous signal is a kind of preset (preset) signal or replacement (reset) signal (also known as removing (clear) signal).Preset condition is when regardless of other input, and the Output rusults of trigger is maintained binary value 1; It is 0 that the Output rusults of trigger is then removed by Reset Status.

Generally speaking, when asynchronous signal exports trigger to, following two kinds of problems can be run into: one is transmission delay (propagationdelay) problem that the restoration schedule of asynchronous signal and clock signal produce collision problem (violationofasynchronousrecovertime) and asynchronous signal.For further illustrating, refer to Fig. 1, Fig. 1 is the graph of a relation of clock signal and reset signal.In FIG, reset signal RST is the asynchronous signal exporting trigger to, when reset signal RST to terminate and by electronegative potential hop jump to the part of dotted line (in the figure) during noble potential resetting, if when now trigger is just in time positioned at the positive edge triggering of clock signal clk or bears edge triggering, trigger can be caused to produce the Output rusults of mistake.In order to avoid this kind of situation occurs, reset signal terminates the regular hour to be kept poor with the triggered time of clock signal instantaneously, thus, can increase the difficulty in circuit design significantly.And the second problem is transmission delay (propagationdelay) problem, during to a reset signal is sent to multiple trigger, due to the delay on signal transmission, the time each trigger receiving this reset signal can be caused different, and cause some trigger first can receive reset signal carrying out replacement action, some trigger then must wait until that next frequency cycle (cycle) just can be reset, and then produces the situation of output error.Known solution be utilize increase impact damper (buffer) mode to balance transmission delay, but this method can cause along with the increase of trigger required impact damper also with increase, also cause spatially and cost meaningless on cost.

Summary of the invention

Therefore an object of the present invention is the remapping method and the apparatus for generating relevant signal that provide a kind of digital circuit, to solve the problem.

According to embodiments of the invention, disclose a kind of remapping method of digital circuit, the method includes: provide clock signal to digital circuit; According to one first cue, maintain this clock signal in a logic level; Produce a reset signal, reset this digital circuit; And according to one second cue, reply this clock signal to this digital circuit.

According to embodiments of the invention, also disclose a kind of signal generation device, be used for generation one clock signal and reset signal to digital circuit, this signal generation device includes: a frequency controller, is used for producing this clock signal to this digital circuit; And a reset signal control module, be used for generation one cue to this frequency controller and produce this reset signal to this digital circuit; Wherein, this reset signal control module, when this clock signal maintains a logic level, produces this reset signal to this digital circuit.

Accompanying drawing explanation

Fig. 1 is known clock signal and reset signal relativeness figure.

Fig. 2 is the function block schematic diagram that the signal generator of first embodiment of the invention is applied to a trigger.

Fig. 3 is the relativeness schematic diagram of clock signal clk and reset signal RST in the signal generator shown in Fig. 2.

Fig. 4 produces the process flow diagram of reset signal to trigger for utilizing the signal generator shown in Fig. 2.

Fig. 5 is the function block schematic diagram that the signal generator of second embodiment of the invention is applied to multiple trigger.

Fig. 6 is the function block schematic diagram that the signal generator of third embodiment of the invention is applied to multiple trigger.

Fig. 7 is the relativeness schematic diagram of clock signal clk and reset signal RST in the signal generator shown in Fig. 6.

Reference numeral explanation

200、500、600	Signal generator	210、510、610	Frequency controller
				220、520、620	Reset signal control module	230、531、532、533、631、632、633、634、635、636	Trigger

Embodiment

Refer to Fig. 2, Fig. 2 is the function block schematic diagram that the signal generator 200 of first embodiment of the invention is applied to a trigger 230.Signal generator 200 includes a frequency controller 210 (such as a phase-locked loop PLL or a delayed type phase-locked loop DLL), be used for generation one clock signal clk to a trigger 230 (such as delayed type trigger (Delay-typeFlipFlop, DFF)), and reset signal control module 220 be used for generation one reset signal (reset) RST in trigger 230.In addition, trigger 230 includes a data input pin D for inputting data, and an output terminal Q is for exporting data.Suppose in the present embodiment, trigger 230 is the trigger of a positive edge trigger-type, and reset signal RST is an asynchronous signal inputing in trigger, and when reset signal RST is positioned at electronegative potential (logical zero), the output Q of trigger 230 can be made to be set to 0.Note that embodiments of the invention do not limit the kind of asynchronous signal.In the present embodiment, signal generator 200 utilizes reset signal control module 220 to produce a reset signal (reset) RST to reset trigger 230, in other embodiments, also a preset signal (preset) control module can be utilized to produce a preset signal and carry out pretrigger 230, it all belongs to covering scope of the present invention.

For further illustrating embodiments of the invention, please refer to Fig. 3, Fig. 3 in the signal generator 200 shown in Fig. 2, the relativeness schematic diagram of clock signal clk and reset signal RST.In embodiments of the present invention, when trigger 230 resets action for performing, reset signal control module 220 provides a cue S ₁to in frequency controller 210, to stop clock signal clk (time T1 as shown in Figure 3), clock signal is made to maintain a logic level (logical one or logical zero), then after a schedule time, (the time T2 such as shown in Fig. 3) reset signal control module 220 resets trigger 230 (also by reset signal RST by noble potential hop jump to electronegative potential), and now namely the output Q of trigger 230 resets to 0; And via (the time T3 such as shown in Fig. 3) after a period of time, reset signal control module 220 terminates the action (also by reset signal RST by electronegative potential hop jump to noble potential) reset, then, reset signal control module 220 reoffers another cue S ₂to in frequency controller 210, make frequency controller 210 recovered clock signal CLK (time T4 as shown in Figure 3), read to continue performing follow-up data the action exported.In embodiments of the present invention, the time interval of time T1 to T4 can produce a count value by a counter and decide, on the other hand, in other embodiments, time startup opportunity that frequency controller 210 starts the time point (time T4 as shown in Figure 3) of clock signal clk also can trigger according to the positive edge of reset signal RST or negative edge, (time T3 as shown in Figure 3) be determined.

Refer to Fig. 4, Fig. 4 is for producing the process flow diagram of reset signal to trigger according to the signal generator 200 shown in Fig. 2, and its step arranges as follows:

Step 410: according to one first cue, frequency controller 210 stops clock signal clk when time T1.

Step 420: reset signal control module 220 when time T2, to the action that trigger 230 resets.

Step 430: reset signal control module 220, when time T3, terminates the action reset trigger 230.

Step 440: according to one second cue, frequency controller 210 is recovered clock signal CLK when time T4.

On the other hand, method of the present invention also can be applicable to, on multiple trigger, refer to Fig. 5, and Fig. 5 is the function block schematic diagram that the signal generator 500 of second embodiment of the invention is applied to multiple trigger.When trigger 531,532 and 533 will reset, frequency controller 510 namely stops clock signal clk for the previous period in replacement action generation, and reset action complete after a period of time just restart clock signal clk, thus, namely can not there is the known trigger that occurs due to the problem of transmission delay and receive the phenomenon that differs of reset signal RST time in embodiments of the invention.

Moreover method of the present invention also can be applicable to, in synchronous replacement (synchronousrest) input, refer to Fig. 6 and Fig. 7, Fig. 6 is the function block schematic diagram that the signal generator 600 of third embodiment of the invention is applied to multiple trigger.Fig. 7 is the relativeness schematic diagram of clock signal clk and reset signal RST in the signal generator 600 shown in Fig. 6.In figure 6, input end D4, D5 and D6 of trigger 641,642 and 643 are respectively coupled to output terminal Q1, Q2 and Q3 of trigger 631,632 and 633.When trigger 631,632 and 633 carries out above-mentioned replacement action, can replacement result (that is binary value 0) be inputed in trigger 641,642 and 643, therefore, by the time when clock signal clk carries out edge-triggered, output terminal Q4, Q5 and Q6 of trigger 641,642 and 643 also can export binary value 0, and reach the synchronous effect reset.Refer to Fig. 7, when signal generator 600 of the present invention performs replacement action, reset signal control module 620 provides a cue S ₁to in frequency controller 610, make frequency controller 610 can stop clock signal clk (time T1 as shown in Figure 7) in advance, after a special time (the time T2 such as shown in Fig. 7), action that reset signal control module 620 carries out resetting (also by reset signal RST by noble potential hop jump to electronegative potential), even if now output terminal Q1, Q2 and Q3 of trigger 631,632 and 633 remove is 0; Next, second cue S providing according to reset signal control module 620 of frequency controller 610 ₂recovered clock signal CLK (time T3 as shown in Figure 7), and through a characteristic frequency cycle (such as two frequency cycle T _cLK) after again according to the 3rd the cue S that reset signal control module 620 provides ₃stop clock signal clk (time T4 as shown in Figure 7).Please note, due to frequency controller 610 again recovered clock signal CLK, therefore namely the value (meaning and reset value 0) of input end D4, D5 and D6 can be noted down on output terminal Q4, Q5 and Q6 because of the edge-triggered of clock signal clk by trigger 641,642 and 643, and then completes the synchronous action reset.Next, via (the time T5 such as shown in Fig. 7) after a period of time, reset signal control module 620 terminates to reset action (also by reset signal RST by electronegative potential hop jump to noble potential).By the time trigger 631,632,633,634,635 and 636 carries out after replacement action completes, and frequency controller 610 is again according to the 4th the cue S that reset signal control module 620 provides ₄just recovered clock signal CLK (time T6 as shown in Figure 7) again, and perform follow-up data and read the action exported.

The foregoing is only preferred embodiment of the present invention, all equalizations done according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. a remapping method for digital circuit, includes:

One clock signal to digital circuit is provided;

According to one first cue, maintain this clock signal in a logic level;

In maintenance first schedule time of this clock signal after a logic level, produce a reset signal, reset this digital circuit, this reset signal continued for second schedule time; And

Producing the 3rd schedule time after described reset signal, according to one second cue, reply this clock signal;

The time interval wherein between this first cue and this second cue produces a count value according to a counter and decides, and described 3rd schedule time is early than described second schedule time;

Wherein, described clock signal is stopped according to the 3rd cue again through all after dates of a characteristic frequency; Further, via a period of time, described reset signal terminates, and after described digital circuit completes replacement action, then recovers described clock signal again according to the 4th cue.

2. the method for claim 1, wherein this second cue produced according to this count value.

3. the method for claim 1, wherein this second cue is by being produced according to this reset signal.

4. the method for claim 1, wherein this reset signal is an asynchronous reset signal or a synchronous reset signal.

5. the method for claim 1, wherein this clock signal produced by a phase-locked loop or a delayed type phase-locked loop.

6. a signal generation device, this generation device comprises:

One frequency controller, is used for generation one clock signal to digital circuit; And

One reset signal control module, be used for generation one first cue to this frequency controller, described frequency controller is made to maintain this clock signal in a logic level, and this reset signal control module produces a reset signal to this digital circuit in maintenance first schedule time of this clock signal after a logic level, to reset this digital circuit, this reset signal continued for second schedule time;

Wherein, three schedule time of this reset signal control module after generation one reset signal produces one second cue to this frequency controller, to reply this clock signal, and the time interval between this first cue and this second cue produces a count value according to a counter decides, and described 3rd schedule time is early than described second schedule time;

Wherein, described clock signal is stopped according to the 3rd cue again through all after dates of a characteristic frequency; Further, terminate replacement action via reset signal control module described after a period of time, after described digital circuit completes replacement action, described frequency controller is again according to the 4th cue recovered clock signal again that described reset signal control module provides.

7. signal generation device as claimed in claim 6, wherein this reset signal control module produces this cue to this frequency controller to maintain this clock signal in this logic level.

8. signal generation device as claimed in claim 6, wherein this digital circuit comprises one first trigger and one second trigger, this clock signal export to this first with this second trigger, an input end of this second trigger is coupled to an output terminal of this first trigger.

9. signal generation device as claimed in claim 8, wherein this first trigger is a delayed type trigger.

10. signal generation device as claimed in claim 6, wherein this reset signal control module produces this second cue according to this count value.

11. signal generation devices as claimed in claim 6, wherein this frequency controller is a phase-locked loop or a delayed type phase-locked loop.