CN102025276A - Clock domain crossing controller of digital control switch power supply and control method thereof - Google Patents
Clock domain crossing controller of digital control switch power supply and control method thereof Download PDFInfo
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Abstract
The invention relates to a clock domain crossing controller of a digital control switch power supply and a control method thereof. The controller comprises a potential-divider network, a analog to digital converter, a digital compensator, a digital pulse modulation circuit, a drive circuit and a clock logic circuit, wherein after data at the output end of a switching power supply is acquired, a voltage control signal of the switching power supply is output through carrying out sequential processing on the data by all modules, and the clock logic circuit provides a working clock of the controller. The invention adopts a system structure of synchronous clock two-edge trigger, overcomes the data delay steady state introduced by the clock single-edge trigger, and is used for optimizing the system data processing part on the basis of maintaining the advantages of the common digital control, thereby reducing the control signal hysteresis in the system, realizing a real-time data control system, cutting off the work of the forestage module after the synchronous clock pulse is ended, and saving the system power consumption.
Description
Technical field
The invention belongs to electronic technology field, relate to the design of integrated circuit, be used for the Switching Power Supply of digital control technology, be specially a kind of digital control Switching Power Supply cross clock domain controller and control method thereof.
Background technology
Adopt the Switching Power Supply of digital control technology, can bring significantly improving of power-supply system performance, because digital control method has flexibility, can realize complicated control algolithm, Ying Xiang susceptibility is lower to external world, as is subjected to the device variable effect little.
The control loop of digital power is to be formed by a plurality of functional module cascades, and how to ensure that the synchronous acquisition between each module data collection point is very important problem in the digital technology.When cross clock domain transmission data, input data and sampling clock take place along the situation of beating the edge, and circuit can not enter stable state at official hour, be metastable state this moment, the voltage of circuit output is between illegal logic level, and concrete magnitude of voltage is unpredictable, and output may be vibrated.Therefore when the cross clock domain system design, need at first the clock of system is defined, make clock synchronization.
The control loop of basic digital control Switching Power Supply comprises four submodules of analog to digital converter ADC, digital compensator and digital pulse width modulation circuit DPWM and drive circuit, as Fig. 1.If simply these several submodule input and output butt joints are built into closed-loop system, although can realize the function of feedback regulation in theory, but carry out circuit design according to this framework, transfer of data is only arranged between each submodule in the system, there is not temporal constraint, can't guarantee to transmit the correctness of data time sequence relation, therefore the framework that directly piles up of this functional module can't guarantee the correctness of system works.And the data processing speed of ADC and digital compensator two-stage is controlled by work clock separately, can have processing speed faster, and the output processing speed and the switching frequency of DPWM circuit is synchronous, and is relatively slow, thereby causes data stacking to form bottleneck.Need determine appropriate sequential relationship for each submodule for addressing the above problem, can realize by a synchronised clock.In the existing digital control Switching Power Supply solution, a kind of is to utilize a plurality of shift registers to carry out the maintenance of data in digital pulse width modulation circuit front, advantage is that all data that prime produces all can obtain handling, but, can't realize the real-time monitoring of system when the control signal of pre-treatment is several switch periods pairing values of data before; Another method is the data of piling up to be carried out " cold " handle, promptly the data that digital pulse-width modulation circuit is had little time to handle are left intact, DPWM only handles the data of current input, this scheme circuit structure is simple, but can lose a part of data, and handled data still have time-delay, are not up-to-date data, and can not learn the cycle of the data correspondence of handling.
Summary of the invention
The problem to be solved in the present invention is that digital control switching is carried out rational sequencing control, guarantees correctness, the instantaneity of transfer of data sequential relationship.
Technical scheme of the present invention is: a kind of digital control Switching Power Supply cross clock domain controller, be connected with the Switching Power Supply power stage, and controller comprises potential-divider network H
Sense, analog to digital converter ADC, error voltage signal processing module, duty cycle control signal processing module, digital pulse width modulation circuit DPWM, logical circuit of clock and drive circuit, the duty cycle control signal processing module comprises the register that digital compensator and d type flip flop are formed, Switching Power Supply output end signal V
Out(t) through potential-divider network H
SenseGathered by analog to digital converter ADC after the dividing potential drop and quantize to obtain digital signal V
o[n], digital signal V
o[n] and default discrete reference voltage V
Ref[n] input error voltage signal processing module, both in the error voltage signal processing module, subtract each other obtain error voltage signal e[n], error voltage signal e[n] carry out data processing, the d of output in the input digit compensator
c[n] is again through digital pulse width modulation circuit DPWM modulation, and by the voltage control signal d (t) that produces Switching Power Supply after the drive circuit amplification, wherein logical circuit of clock provides the synchronizing clock signals syn (t) of controller each several part.
Logical circuit of clock is by some d type flip flops, with door, not gate forms, counter by multiplexing DPWM obtains clock circuit, counter output signal feeds back to the counter input after delaying time through first d type flip flop again, send into second d type flip flop after the negate of unison counter output signal, the second d type flip flop end of oppisite phase signal inserts the input of 3d flip-flop, wherein the in-phase output end of second d type flip flop and 3d flip-flop is sent into one two input and door, and described two inputs are synchronizing clock signals with the output of door.
The control method of above-mentioned digital control Switching Power Supply cross clock domain controller is: controller is regulated the size of a duty ratio in each switch periods of Switching Power Supply, and finish the renewal of error voltage signal and duty cycle control signal simultaneously: controller carries out sequencing control by same clock signal syn (t), when rising edge of clock signal arrives, ADC starts work, carry out data acquisition process, upgrade the data of error signal processing module simultaneously, when the trailing edge of clock signal arrives, trigger the Data Update of duty cycle control signal processing module, and with up-to-date duty cycle control signal d[n] pass to DPWM and handle in real time, wherein synchronizing clock signals syn (t) is set to a narrow pulse signal that duty ratio is very little, the size of described narrow pulse signal is relevant with the work clock of analog to digital converter ADC and digital compensator, be the processing time of ADC and sum computing time of digital compensator, in a switch periods, utilize syn (t) signal as selecting signal, with actual output of DPWM and supply voltage V
DDSelected signal as the alternative selector, when syn (t) signal is high level, make DPWM output and supply voltage connect, promptly force to make that the pwm signal of output is a high level, re-use the duty cycle control signal d[n of actual generations of this switch periods after synchronizing clock signals syn (t) trailing edge] the duty ratio size of the output signal dpwm (t) of control DPWM, the pwm signal that assurance DPWM exports in each switch periods is that the systematic error voltage signal of this switch periods is regulated.
The present invention is on the basis of analyzing digital control Switching Power Supply internal circuit configuration and transfer of data sequential, proposed to adopt synchronised clock two along the system constructing that triggers, adopt the rising and falling edges of the synchronizing clock signals of inside generation data to be carried out two along triggering processing, this method makes the data flow of cross clock domain work under unified clock control, overcome the clock list along triggering the data delay stable state of introducing, and can the overall planning system module operating time, can close the prime module where necessary, reduce the power loss of system.The present invention also forces the control signal of output at synchronizing clock signals in the pulse duration be high, to reduce the time-delay of data in the system, guaranteed real-time control, overcome the deficiencies in the prior art.
The present invention optimizes the controller data processing section, thereby has reduced the control signal hysteresis on the basis that keeps ordinary numbers control advantage, realized the real time data control system, and after synchronous clock pulse finishes, cut off the work of prime module, save system power dissipation.Advantage of the present invention and beneficial effect comprise:
(1), circuit structure is simple, is made up of the standard gate circuit, be easy to realize and preparation technology simple;
(2), the inside synchronised clock that adopts in the system is two can the real time processing system data along circuits for triggering, have guaranteed the real-time of control signal;
(3), the design philosophy of the initial high level of output duty cycle signal that adopts in the system, can the processing stage of system data, keep regulatory function, improved the response speed of system;
(4), in the system each module operating time controlled, reduced the circuit power loss.
Description of drawings
Fig. 1 is the system architecture block diagram that uses the external sync clock in the digital control Switching Power Supply.
Fig. 2 is the system architecture data variation rule figure that uses the external sync clock in the digital control Switching Power Supply.
Fig. 3 is that the inside synchronised clock of digital control Switching Power Supply cross clock domain controller of the present invention is two along the triggering system block architecture diagram.
Fig. 4 is that the synchronised clock of digital control Switching Power Supply cross clock domain controller of the present invention is two along triggering system framework data variation rule.
Fig. 5 is counter, the synchronous clock generator circuit diagram of digital control Switching Power Supply cross clock domain controller of the present invention.
Fig. 6 is counter, the synchronous clock generator circuit working waveform of digital control Switching Power Supply cross clock domain controller of the present invention.
Fig. 7 is the synchronizing clock signals and the duty cycle signals of digital control Switching Power Supply cross clock domain controller of the present invention.
Fig. 8 is the connection diagram of the present invention and Switching Power Supply.
Embodiment
As Fig. 3 and Fig. 8, controller of the present invention comprises potential-divider network H
Sence, analog to digital converter, error voltage signal processing module, digital compensator, pwm signal output module, drive circuit and logical circuit of clock.Switching Power Supply fan-out is according to V
Out(t) after the potential-divider network dividing potential drop, gathered and quantize to obtain V by ADC
o[n] is with default discrete reference voltage V
Ref[n] subtract each other obtain error voltage signal e[n] send into and carry out data processing in the digital compensator, produce the voltage control signal of Switching Power Supply again through digital pulse width modulation circuit DPWM modulation, and strengthen the folding of control switching power tube after the driving force by drive circuit.Controller is regulated the size of a duty ratio in each switch periods of Switching Power Supply, the renewal of ADC sample quantization, error generation, compensator output and duty cycle control signal is finished in i.e. synchronizing clock signals syn (t) control that is produced by clocked logic in a switch periods.Logical circuit of clock is by some d type flip flops, with door, not gate forms, counter by multiplexing DPWM obtains clock circuit and obtains synchronizing clock signals syn (t), when the rising edge of clock signal syn (t) arrives, ADC starts work, carry out data sampling and quantize, error signal processing module and digital compensator dateout are upgraded; When the trailing edge of clock signal arrives, trigger DPWM duty ratio modulation module input Data Update, be about to current duty cycle control signal d
c[n] reads among the DPWM and handles in real time.Wherein synchronizing clock signals syn (t) high level is held time relevantly with the work clock of analog to digital converter ADC and digital compensator, is ADC processing time and digital compensator sum computing time.Keep in the high level time at syn (t), the prime module is being carried out data processing, and the input signal free of data of DPWM is upgraded, and the input signal of DPWM just obtains upgrading after syn (t) trailing edge arrives.In order to make that the duty ratio output signal dpwm (t) in each cycle is the processing to sampled value in the current switch periods, therefore in syn (t) high level time, will force to make that the DPWM output signal is a high level, output dpwm (t) high level that re-uses the current actual duty cycle control signal control DPWM that produces after syn (t) trailing edge is held time, promptly exporting dpwm (t) high level holds time and is made up of two parts: force high level time and accurate high level time, guaranteed that DPWM is that the current system mode of this switch periods is regulated at the pwm signal of each switch periods output.Regulate accurately for making, force high level time short as far as possible, promptly needing syn (t) is a narrow pulse signal, and high level is held time shorter, therefore requires ADC, Error processing module and digital compensator to have processing speed at a high speed.And in order to solve the problem that ADC, Error processing module and digital compensator high-frequency clock bring power consumption to increase, by synchronised clock syn (t) as clock control signal, when syn (t) trailing edge comes interim, represent that these three resume module finish, nip off its work clock, in the time need handling next time, open it again, so that reduce system power dissipation.
Specify the control method of the present invention's control below.
Each switch periods is regulated the size of a duty ratio in digital power, and adjustment process to be digital compensator and two modules of DPWM finish jointly.The big or small e[n that needs on the one hand the error voltage that digital compensator quantizes according to ADC] and the operating state of previous moment system calculate current required duty cycle control signal d
cThe size of [n]; Need DPWM according to this duty cycle control signal d on the other hand
c[n] produces the dutyfactor value dpwm (t) of output PWM waveform in the switch periods.Suppose to adopt typical digital PID compensation, then the pass of duty cycle control signal and error voltage is
d
c[n]＝d
c[n-1]+ae[n]-be[n-1]+ce[n-2] (1)
Wherein, a, b, c are respectively the penalty coefficient of PID, can determine the size of coefficient value according to switch power supply system frequency stabilization property design method, for as well known to those skilled in the art, no longer describe in detail.Therefore, calculate the duty cycle control signal size d of current switch periods
c[n] needs to use the duty ratio size d of previous switch periods
cThe error voltage e[n of [n-1], current switch periods] and preceding two switch periods error voltage e[n-1], e[n-2], so also need to use synchronised clock that above each data are once upgraded in each switch periods.Can in the error signal processing module, adopt the series connection d type flip flop to preserve related data, can utilize synchronised clock syn (t) to control each switch periods and finish Data Update one time.Because the d type flip flop of error signal processing module and duty cycle control signal processing module inside has used same synchronizing clock signals, and there are unidirectional data to flow between the two, the data of such n switch periods are upgraded by the Error processing module in this cycle and are given the size that digital compensator is used for computed duty cycle, but calculate resulting duty ratio size d
c[n] must arrive n+1 switch periods and could be regulated the duty ratio of output signal dpwm (t) by renewal of the d type flip flop in the duty cycle control signal processing module and control DPWM.Adopt this treating method can exempt the accumulation of data and lose, but still caused the hysteresis of a switch periods, the output control signal of DPWM can not in time be controlled current system mode, will inevitably bring adverse effect to system.
For fear of not controlling in real time power-supply system, wish in a switch periods, to finish simultaneously the renewal of error voltage signal, duty cycle control signal because of above-mentioned data lag behind.Because the two is subjected to same clock signal syn (t) control, the rising edge trigger error signal processing module that the present invention proposes at clock carries out Data Update, and the trailing edge of clock triggers the processing mode of the Data Update of duty cycle control signal.But since in the time period in the middle of the rising edge of synchronizing clock signals and trailing edge because duty cycle control signal d
c[n] still is not updated, and its value still is the error voltage e[n of last switch periods] result after the data relevant with other states in the circuit are calculated by digital compensator.Consider that duty ratio usually can be very not little in the actual switch power-supply system, promptly pwm signal can not become low level in a short period of time after a switch periods begins.Based on this characteristics, synchronised clock syn (t) is set to a narrow pulse signal that duty ratio is very little, the rising edge of pulse and in the time period between the trailing edge the compulsory PWM of making output signal be high level, re-use the duty cycle control signal d that this switch periods produces after the synchronizing clock signals trailing edge
cThe duty ratio size of [n] control pwm signal dpwm (t) so just can guarantee that the pwm signal of each switch periods output is that the systematic error voltage signal of this switch periods is regulated.The size of described narrow pulse signal is relevant with the work clock of analog to digital converter ADC and digital compensator, be the processing time of ADC and sum computing time of digital compensator, in the burst length of a clock signal, utilize syn (t) signal as selecting signal, with actual output of DPWM and supply voltage V
DDAs the selected signal of alternative selector, when syn (t) signal is high level, make DPWM output and supply voltage connect, promptly force to make that the DPWM output signal is a high level.
Below in conjunction with accompanying drawing and example circuit structure of the present invention, operation principle and the course of work are described further.
Referring to Fig. 2 and Fig. 3, in the digital control Switching Power Supply cross clock domain controller of optimization of the present invention digital compensator is included in the category of duty cycle control signal processing module, syn (t) signal substituting that the add-on system synchronous clock generation circuit produces in the DPWM module is outside originally give clock signal.The rising edge of synchronised clock syn (t) means the beginning of a switch periods, and this rising edge carries out Data Update in the d type flip flop in the error voltage signal processing module in can triggering figure.After the synchronised clock rising edge is high level, duty cycle control signal between high period is not because also through upgrading, its value still is the data of a last switch periods, but force DPWM to be output as high level by synchronised clock control MUX in this case, do not allow the duty cycle control signal of a switch periods control the duty ratio size of current switch periods pwm signal.Digital compensator is finished digital compensation by the backoff algorithm shown in the formula (1) during this period.The duty cycle control signal that the trailing edge arrival of synchronizing clock signals triggers current switch periods upgrades by d type flip flop, data after the renewal are given the size of DPWM control pwm signal duty ratio, the synchronizing clock signals saltus step is a low level simultaneously, the duty cycle signals of the current switch periods reality of MUX output DPWM this moment.Data are with Changing Pattern such as Fig. 4 of synchronizing clock signals.
In synchronizing clock signals syn (t) be high time period, PWM output was forced to height to the relation of the output valve dpwm of DPWM (t) and synchronised clock syn (t) as can be seen, and when syn (t) becomes when low, PWM just exports the dutyfactor value of reality.So in the sort circuit structure, the size of the minimum duty cycle signal that system can export is subjected to the restriction of clock sync signal, and can not reach desirable zero duty ratio.But from Switching Power Supply real work situation, duty cycle signals in switch periods of needs can not appear in system substantially under the PWM mode of operation be zero demand, and the restriction that therefore can export the minimum duty cycle signal does not influence side circuit work.The synchronizing clock signals of controller of the present invention and duty cycle signals such as Fig. 7, wherein 1 is duty cycle signals, 2 is synchronizing clock signals.
Synchronous clock generation circuit is to realize by the Counter Design pulse generating circuit of DPWM part in the digital multiplexing power supply among the present invention, referring to Fig. 5, logical circuit of clock is by some d type flip flops, with door, not gate is formed, counter by multiplexing DPWM obtains clock circuit, counter output signal feeds back to the counter input after delaying time through first d type flip flop again, send into second d type flip flop after the negate of unison counter output signal, the second d type flip flop end of oppisite phase signal inserts the input of 3d flip-flop, wherein the in-phase output end of second d type flip flop and 3d flip-flop is sent into one two input and door, and described two inputs are synchronizing clock signals with the output of door.In this circuit, the rising edge of input clock signal clk_in can trigger more new data of the first d type flip flop DFF, causes counter output signal N[n-1:0] add one.Counting beginning back (2
n-1) in the individual count cycle, the highest order N[n-1 of counter output] be ' 0 ' always; Through 2
nIndividual all after date counter meters are full, N[n-1] be ' 1 ', and synchronizing clock signals syn (t) during this period of time remains low level always.(2
n+ 1) individual all after date N[n-1] be ' 0 ' by ' 1 ' saltus step again.At this moment the Q of second d type flip flop DFF0 end is exported high level, and NQ holds output low level; And the output of 3d flip-flop DFF1 ' 1 ' before still keeping, the output of two d type flip flops by with logic after to cause this synchronizing signal saltus step be high level, through a clk_in after the signal period 3d flip-flop DFF1 output hopping be low level, synchronizing signal also therefore saltus step be low level.When the counter output valve once more under the situation of vanishing synchronizing signal positive transition can take place once more, so the cycle of this synchronizing signal be switch periods just, duty ratio is 1/32.The counter of digital control Switching Power Supply cross clock domain controller, synchronous clock generator circuit working waveform are as shown in Figure 6.In addition because the synchronizing signal positive transition occurs in the moment of counter output null value, this moment, positive transition also can take place in pwm signal, therefore the beginning of a switch periods of the positive transition of synchronizing signal meaning, this synchronizing signal can satisfy the needs of system data synchronization fully.
Claims (3)
1. a digital control Switching Power Supply cross clock domain controller is connected with Switching Power Supply, it is characterized in that controller comprises potential-divider network H
Sense, analog to digital converter ADC, error voltage signal processing module, duty cycle control signal processing module, digital pulse width modulation circuit DPWM, logical circuit of clock and drive circuit, the duty cycle control signal processing module comprises the register that digital compensator and d type flip flop are formed, Switching Power Supply output end signal V
Out(t) through potential-divider network H
SenseGathered by analog to digital converter ADC after the dividing potential drop and quantize to obtain digital signal V
o[n], digital signal V
o[n] and default discrete reference voltage V
Ref[n] input error voltage signal processing module, both in the error voltage signal processing module, subtract each other obtain error voltage signal e[n], error voltage signal e[n] carry out data processing, the d of output in the input digit compensator
c[n] is again through digital pulse width modulation circuit DPWM modulation, and by the voltage control signal d (t) that produces Switching Power Supply after the drive circuit amplification, wherein logical circuit of clock provides the synchronizing clock signals syn (t) of controller each several part.
2. digital control Switching Power Supply cross clock domain controller according to claim 1, it is characterized in that logical circuit of clock is by some d type flip flops, with door, not gate is formed, counter by multiplexing DPWM obtains clock circuit, counter output signal feeds back to the counter input after delaying time through first d type flip flop again, send into second d type flip flop after the negate of unison counter output signal, the second d type flip flop end of oppisite phase signal inserts the input of 3d flip-flop, wherein the in-phase output end of second d type flip flop and 3d flip-flop is sent into one two input and door, and described two inputs are synchronizing clock signals with the output of door.
3. the control method of claim 1 or 2 described digital control Switching Power Supply cross clock domain controllers, it is characterized in that the size of controller in a duty ratio of each switch periods adjusting of Switching Power Supply, and finish the renewal of error voltage signal and duty cycle control signal simultaneously: controller carries out sequencing control by same clock signal syn (t), when rising edge of clock signal arrives, ADC starts work, carry out data acquisition process, upgrade the data of error signal processing module simultaneously, when the trailing edge of clock signal arrives, trigger the Data Update of duty cycle control signal processing module, and with up-to-date duty cycle control signal d[n] pass to DPWM and handle in real time, wherein synchronizing clock signals syn (t) is set to a narrow pulse signal that duty ratio is very little, the size of described narrow pulse signal is relevant with the work clock of analog to digital converter ADC and digital compensator, be the processing time of ADC and sum computing time of digital compensator, in a switch periods, utilize syn (t) signal as selecting signal, with actual output of DPWM and supply voltage V
DDSelected signal as the alternative selector, when syn (t) signal is high level, make DPWM output and supply voltage connect, promptly force to make that the pwm signal of output is a high level, re-use the duty cycle control signal d[n of actual generations of this switch periods after synchronizing clock signals syn (t) trailing edge] the duty ratio size of the output signal dpwm (t) of control DPWM, the pwm signal that assurance DPWM exports in each switch periods is that the systematic error voltage signal of this switch periods is regulated.
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