CN109391247A - A kind of filter based on pwm signal, processing circuit and chip - Google Patents
A kind of filter based on pwm signal, processing circuit and chip Download PDFInfo
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- CN109391247A CN109391247A CN201811501490.8A CN201811501490A CN109391247A CN 109391247 A CN109391247 A CN 109391247A CN 201811501490 A CN201811501490 A CN 201811501490A CN 109391247 A CN109391247 A CN 109391247A
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- 238000012545 processing Methods 0.000 title claims abstract description 27
- 238000001914 filtration Methods 0.000 claims abstract description 8
- 230000000630 rising effect Effects 0.000 claims description 28
- 238000003708 edge detection Methods 0.000 claims description 16
- 238000012935 Averaging Methods 0.000 claims description 14
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000005070 sampling Methods 0.000 description 17
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Abstract
The present invention discloses a kind of filter based on pwm signal, processing circuit and chip, the filter is applied to the pwm signal of filtering external input, the filter includes the d type flip flop and a comparison output module of preset quantity, the d type flip flop of preset quantity constitutes the shift register of a preset quantity bit, the clock end of the d type flip flop of preset quantity is connected to the input end of clock of the filter, and the output end (Q) of the d type flip flop of preset quantity is connected respectively to the data input pin for comparing the preset quantity of output module.Be conducive to optimize the level Vibrating pulse of pwm signal in engineering practice.
Description
Technical field
The present invention relates to signal modulation technique field, it is related to a kind of filter based on pwm signal, processing circuit and core
Piece.
Background technique
PWM (Pulse Width Modulation) technology is in industrial automation, robot, precise numerical control machine, boat
The numerous areas such as empty space flight are used widely.Servo control system needs to generate the pwm signal driving of variable duty ratio
IGBT, IPM constant power device；The kinetic control systems such as robot or numerically-controlled machine tool can between motion control card and servo-driver
Pass through the pwm signal of changeable frequency, transmission location control instruction.PWM and PFM is two kinds of control modes of DC/DC switch, this kind of
Technology is usually used in some analog circuits or peripheral motor is controlled.As the integrated level of IC is higher and higher.It is most of on the market
Pwm circuit all the pwm signal of input is not handled, this is unfavorable for the control to electric system, influence motor rotation
Precision.
Summary of the invention
In order to overcome the problems referred above, the invention proposes a kind of filters based on pwm signal.
A kind of filter based on pwm signal, the filter are applied to the pwm signal of filtering external input, the filtering
Device includes the d type flip flop and a comparison output module of preset quantity, and the d type flip flop of preset quantity constitutes a preset quantity ratio
The shift register of special position, the clock end of the d type flip flop of preset quantity are connected to the input end of clock of the filter, present count
The output end (Q) of the d type flip flop of amount is connected respectively to the data input pin for comparing the preset quantity of output module, shift register
Signal input part of the data input pin as filter, the data output end for comparing output module is defeated as the signal of filter
Outlet.
Further, in the shift register, each d type flip flop other than the d type flip flop of rightmost it is defeated
The input terminal of one d type flip flop in the right is terminated to out, and the output end of the d type flip flop of rightmost accesses the relatively output module
One data input pin, data input pin of the input terminal of leftmost d type flip flop as shift register.
Further, in the shift register, each d type flip flop other than leftmost d type flip flop it is defeated
The input terminal of one d type flip flop in the left side is terminated to out, and the output end of leftmost d type flip flop accesses the relatively output module
One data input pin, data input pin of the input terminal of the d type flip flop of rightmost as shift register.
Further, the preset quantity is set as 6, so that the filter is by the pwm signal (PWM_ to be processed of input
IN the level shake in) less than 5 clock cycle is all filtered as burr, wherein the clock cycle is described to be processed
The pulse period of the jitter levels of pwm signal (PWM_IN).
A kind of processing circuit of pwm signal, the processing circuit are applied to the electric system outside adjusting, the processing circuit
Including PWM sample detecting module and PWM generation module；The input end of clock of PWM sample detecting module and PWM generation module when
Clock input terminal is connected；PWM sample detecting module includes step-length counting submodule, signal pre-divider, speed detector, first
Clock pre-divider and the filter, wherein signal of the signal input part of the filter as PWM sample detecting module
Input terminal, output end of the speed signal output end of speed detector as PWM sample detecting module；PWM sample detecting module
Internal connection relationship is: the signal output end of the filter while data input pin and signal with step-length counting submodule
The input end of clock of pre-divider connects, and the output terminal of clock of signal pre-divider is connected with the data input pin of speed detector
It connects；The input end of clock of speed detector is connected with the output terminal of clock of the first clock pre-divider；PWM generation module includes
Second clock pre-divider and pwm signal generator, the connection relationship of inside modules is: the clock of second clock pre-divider is defeated
Outlet is connected with the data input pin of pwm signal generator, and the input end of clock of second clock pre-divider is generated as PWM
The input end of clock of module, output end of the data output end of pwm signal generator as PWM generation module.
It further, include step-length counter and direction register, direction register inside the step-length counting submodule
Output end connect with the enable end of step-length counter, the terminal count output of step-length counter is as the step-length counting submodule
Output end, data input pin of the counting input end of step-length counter as the step-length counting submodule.
Further, rising edge detection circuit includes a d type flip flop and one and door, the input terminal conduct of d type flip flop
The input terminal of rising edge detection circuit, an input terminal of the input terminal connection and door of trigger, the reversed-phase output of d type flip flop
Another input terminal of connection and door；The clock end of pulsewidth counter is connected with the clock end of d type flip flop, rising edge detection electricity
By connecting with the output end of door with the reset terminal of pulsewidth counter, the data output end connection intermediate value of pulsewidth counter is average on road
The data input pin of module, speed signal output end of the output end of intermediate value averaging module as the speed detector rise
Along data input pin of the input terminal as the speed detector of detection circuit.
Further, the clock that the bit wide numerical value power of the 2 pulsewidth counter is greater than the pulsewidth counter inputs
The ratio of the signal frequency of the input terminal of the signal frequency at end and the d type flip flop.
Further, the pwm signal generator includes output frequency divider and comparator, the clock output of output frequency divider
End input terminal compared with one of comparator connects, data of the input terminal of output frequency divider as the pwm signal generator
Input terminal, data output end of the output end of comparator as the pwm signal generator.
A kind of chip, the chip interior include the processing circuit.
Compared with prior art, the filter internal design shift register comes with the combination for comparing output module to defeated
Enter pwm signal to be filtered, the number of shift register is configured according to the time precision of driving clock, can be filtered out small
In the pulse signal of 5 clock cycle, there is very strong practicability and expansion.Be conducive to optimize pwm signal in engineering practice
Level Vibrating pulse, to improve the validity and reliability of the pwm signal of sampling.
Detailed description of the invention
Fig. 1 is a kind of processing circuit structural schematic diagram of pwm signal of the embodiment of the present invention.
Fig. 2 is a kind of filter construction schematic diagram based on pwm signal of the embodiment of the present invention.
Fig. 3 is a kind of waveform diagram of the filtering principle of filter based on pwm signal of the embodiment of the present invention.
Fig. 4 is the circuit diagram of the speed detector of the embodiment of the present invention.
Fig. 5 is that the filtering of the embodiment of the present invention disappears the sampling time sequence figure of the pwm signal pulsewidth trembled.
Fig. 6 is the circuit diagram of the pwm signal generator of the embodiment of the present invention.
Specific embodiment
Specific embodiments of the present invention will be further explained with reference to the accompanying drawing:
The embodiment of the present invention provides a kind of filter based on pwm signal, which is applied to the PWM letter of filtering external input
Number, as shown in Fig. 2, the filter includes that the d type flip flop of preset quantity and a comparison output module, the preset quantity are set
Be set to 6, the filter include the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, four d flip-flop D4,
5th d type flip flop D5, the 6th d type flip flop D6 and a comparison output module, aforementioned 6 d type flip flops constitute 6 bits
Shift register, the clock end of aforementioned 6 d type flip flops all access high frequency clock signal CLK_US, the output of the first d type flip flop D1
Hold Q [0], the output end Q [1] of the second d type flip flop D2, the output end Q [2] of third d type flip flop D3, four d flip-flop D4 it is defeated
The output end Q [5] of outlet Q [3], the output end Q [4] of the 5th d type flip flop D5 and the 6th d type flip flop D6 are connected respectively to more defeated
6 data input pins of module out compare signal output end of the data output end of output module as the filter.Compare
The data output end of output module is used for outputting reference pwm signal Encoder, compares the data output end of output module as institute
The signal output end of filter is stated, to provide stable detection signal for subsequent PWM sample detecting module.
As one embodiment, each D triggering in the shift register, other than the d type flip flop of rightmost
The output of device terminates to the input terminal of one d type flip flop in the right, and the output end access of the d type flip flop of rightmost is described relatively to be exported
One data input pin of module, data input pin of the input terminal of leftmost d type flip flop as shift register.Such as Fig. 2
Shown, the data in the shift register successively move to right by turn under the driving effect of the high frequency clock signal CLK_US
When, the output of each d type flip flop other than the 6th d type flip flop D6 terminates to the input terminal D of one d type flip flop in the right, the
The input terminal D of one d type flip flop D1 accesses pwm signal PWM_IN to be processed.
As another embodiment, each D touching in the shift register, other than leftmost d type flip flop
The output of hair device terminates to the input terminal of one d type flip flop in the left side, and the output end access of leftmost d type flip flop is described more defeated
A data input pin of module out, when the data in the shift register are in the driving of the high frequency clock signal CLK_US
When successively moving to left by turn under effect, the output end Q of each d type flip flop other than leftmost d type flip flop is connected to the left side one
The input terminal D of the input terminal D of a d type flip flop, the d type flip flop of rightmost access the pwm signal PWM_IN to be processed.
The shift register can not only registered data, and can make under the action of the high frequency clock signal CLK_US
Data therein are successively moved to left or are moved to right.Because since being added on trigger the rising edge of the high frequency clock signal CLK_US
One section of delay time is steadily set up to output end new state, so when the high frequency clock signal CLK_US adds simultaneously
When on to the d type flip flop of the preset quantity, received each d type flip flop is one, the left side (or the right) d type flip flop Central Plains
The data come, then the data in the shift register successively move to right (or moving to left) one.
The internal logic relationship of the relatively output module are as follows: when 6 data input pins of the relatively output module are complete
When being 0, i.e., when corresponding 6 bit signal Q [5:0]=0 of the output end of 6 triggers, the institute of the relatively output module output
Stating benchmark pwm signal Encoder is low level；When 6 data input pins of the relatively output module are all 1, i.e., 6 touchings
When sending out corresponding 6 bit signal Q [5:0]=6 ' b111111 of output end of device, the base of the relatively output module output
Quasi- pwm signal Encoder is high level；When existing 0 also has 1 in the relatively data input pin of the preset quantity of output module
When, i.e. Q [5:0]！=0 and Q [5:0]！When=6 ' b111111, the benchmark pwm signal of the relatively output module output
It is constant that Encoder retains original level state.
Preferably, the preset quantity is set as 6, so that the filter will be in the pwm signal PWM_IN to be processed
Level shake less than 5 clock cycle is all filtered as burr, wherein the clock cycle is the PWM letter to be processed
The pulse period of the jitter levels of number PWM_IN.If there is the arteries and veins less than one fixed width in the pwm signal PWM_IN to be processed
Punching needs to filter out, and when needing to filter out such as the jitter levels pulse of 1uS, the filter can be 0.2us's by 6 delay times
D type flip flop and a relatively output module are constituted, and the d type flip flop that 6 delay times are 0.2us constitutes 6 bits
Shift register.
As shown in figure 3, before the corresponding pwm signal PWM_IN to be processed disappears and trembles before the t0 moment, it is described relatively to export
The input terminal of the preset quantity of module is full 0, and the benchmark pwm signal Encoder of the relatively output module output is corresponding
Ground is low level.The t0 moment of Fig. 3 between the t1 moment, the time of t1-t0 are as follows: delay time is the 6th d type flip flop of 0.2us
It delay time of the output end Q [5] of D6 relative to the output end Q [0] for the first d type flip flop D1 that delay time is 0.2us, calculates
Know to be 5 times of 0.2us, i.e. the delay of 1us.During the pwm signal PWM_IN to be processed disappears and trembles, that is, correspond to the t0 moment extremely
The t2 moment.
As shown in figure 3, the input terminal of the relatively preset quantity of output module becomes from full 0 from the t0 moment to the t1 moment
It is complete 1.Since there is the low level Vibrating pulses of 1uS by the pwm signal PWM_IN to be processed, so by d type flip flop
After delayed-action, as shown in figure 3, the t1 moment, between the t2 moment, the input terminal of the relatively preset quantity of output module was both
There are 1 again there are 0, i.e. Q [5:0]！=0 and Q [5:0]！=6'b111111.It is closed according to the internal logic of the relatively output module
System, as shown in figure 3, the benchmark pwm signal Encoder of the relatively output module output becomes high level from low level,
Then it is constant to retain the high level state at t1 moment, just completes to postpone to disappear to tremble until the t2 moment, Q [5:0] becomes 6 ' b0, so that
The benchmark pwm signal Encoder becomes low level from high level.And t1 to benchmark pwm signal Encoder described during t2 can
Determine to be stable level signal during this, so that the noise restraint to the pwm signal PWM_IN to be processed is completed, so that small
It will be all filtered out in the level shake of 5 system clock cycles, it can be to greater or lesser arteries and veins although sacrificing delay time
The level Vibrating pulse of wide scope is filtered effect, advantageously reduces the electromagnetic interference of all kinds of electric systems, has very strong
Practicability and expansion.
As shown in Figure 1, the embodiment of the present invention provides a kind of processing circuit of pwm signal, the processing circuit includes that PWM is adopted
Sample detection module and PWM generation module；The input end of clock of the PWM sample detecting module and the PWM generation module when
Clock input terminal is connected；The signal input part of the PWM sample detecting module is used to capture the pwm signal PWM_ to be processed of input
IN, the input end of clock of the PWM sample detecting module are used to receive the high frequency clock letter of external system clock generator output
Number CLK_US, under the embodiment of the present invention, the frequency range of pwm signal PWM_IN to be processed is greater than 32Hz and is less than 2KHz,
The high frequency clock signal CLK_US of external system clock generator output is the clock signal for being 0.2us in the period, passes through corresponding essence
The counting of degree plays signal and disappears the effect of trembling；The PWM sample detecting module is used to export the pulse speed based on pwm signal to be processed
Signal speed and corresponding pulse step size signal are spent for external electric system, are used as feedback quantity.Relative to existing skill
Art expands the application function of pwm signal output circuit.The PWM generation module is defeated for receiving external system clock generator
Sampling clock Clk out, and export the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk；The PWM
Sample detecting module and the PWM generation module are commonly connected to the sampling clock Clk；Wherein, sampling clock Clk can be with
Bus clock on external ahb bus, corresponding clock frequency size include 80MHz, 40MHz or 20MHz, so that
The PWM output signal PWM_OUT meets the application demand of various electric machine control systems.When the PWM sample detecting module is
When external electric system provides impulse speed signal speed and corresponding pulse step size signal, external electric system according to
Aforementioned sample signal is adjusted, and specifically adjusts the frequency size of the sampling clock Clk of output, pwm signal PWM_ to be processed
Then IN and high frequency clock signal CLK_US controls the PWM output signal PWM_ of the PWM generation module output duty ratio corresponding
OUT, to complete the rotational speed regulation control to external electric system.
The PWM sample detecting module includes the filter, step-length counting submodule, signal pre-divider, speed inspection
Device and the first clock pre-divider are surveyed, the connection relationship of inside modules is: the signal output end of the filter while and step-length
The data input pin of counting submodule is connected with the input end of clock of signal pre-divider, the output terminal of clock of signal pre-divider
It is connected with the data input pin of speed detector；The clock of the input end of clock of speed detector and the first clock pre-divider
Output end is connected；Signal input part of the signal input part of the filter as PWM sample detecting module, speed detector
Output end of the speed signal output end as PWM sample detecting module.The signal input part of the filter is defeated for capturing
The pwm signal PWM_IN to be processed entered, the height of the clock input external system clock generator output of the filter
Frequency clock signal clk _ US, and under the driving effect of high frequency clock signal CLK_US, control pwm signal PWM_IN mistake to be processed
Filter, then from the signal output end outputting reference pwm signal Encoder of the filter.Since high frequency clock signal CLK_US is
It can configure, so, the level dither signal of distinct pulse widths in pwm signal PWM_IN to be processed may be implemented in the filter
Filter operation.The signal output end of the filter is divided with the data input pin and signal of step-length counting submodule in advance simultaneously
The input end of clock of device connects, and divides in advance for benchmark pwm signal Encoder to be transferred to step-length counting submodule and signal
Device；Signal pre-divider is used for received benchmark pwm signal Encoder scaling down processing to export the first pwm signal
Encoder1, wherein the frequency divider of 2 frequency dividings, 4 frequency dividings or 8 frequency dividings is supported and be can be configured to the signal pre-divider；The letter
The output terminal of clock of number pre-divider is connected with the data input pin of the speed detector, for by the first pwm signal
Encoder1 is transferred to the speed detector, to export the first pwm signal Encoder1 of different frequency to the speed
Detector.First clock pre-divider, the sampling clock Clk for controlling and receiving divide to obtain the first sub-frequency clock signal Clk_
Div1, and the first sub-frequency clock signal Clk_div1 is exported to speed detector, under the present embodiment, the first clock divides in advance
The frequency division coefficient of device is configured to 16.The input end of clock of the speed detector and the clock of the first clock pre-divider are defeated
Outlet is connected, and the speed detector passes through detection first under the driving effect of the first sub-frequency clock signal Clk_div1
Corresponding first point in each pulse period of the rising edge of pwm signal Encoder1 to count the first pwm signal Encoder1
The pulse number of frequency clock signal Clk_div1, the speed detector is using the first sub-frequency clock signal Clk_div1 come to
One pwm signal Encoder1 carries out sample detecting, and the pulse number is carried out intermediate value average treatment, completes the pulse
Then several noise reduction process exports impulse speed signal speed in the speed signal output end of the speed detector.Intermediate value is flat
Speed signal output end of the output end of equal module as the speed detector, the speed signal output of the speed detector
The output end as the PWM sample detecting module is held, the speed signal based on the output end can reduce noise signal and treat place
The influence of the impulse speed measured value of pwm signal PWM_IN is managed, to provide the pulse of higher precision for external electric system
Speed signal, so as to the feedback signal of the revolving speed of electric system.
It include step-length counter and direction register, the output of the direction register inside the step-length counting submodule
End is connect with the enable end of the step-length counter, and the terminal count output of step-length counter is as the step-length counting submodule
Output end, data input pin of the counting input end of step-length counter as the step-length counting submodule.The direction deposit
Device is for exporting add-subtract control signal, and as " adding " or the direction control signal of the switch of " subtracting ", the direction register is defeated
Add-subtract control signal out is connect with the step-length counter.If the add-subtract control signal is set to 1, the step-length counter
For making to add 1 to count in each pulse period, the step-length counting submodule detects the one of the benchmark pwm signal Encoder
When a rising edge signal, the step-length counter is since 0 plus 1 counts, while retaining current count value and counting to the step-length
In register built in device, to provide the step number based on the pwm signal PWM_IN to be processed for external motor control system
Value, represents the distance value that motor rotates；After the count value of the step-length counter reaches maximum value, the step-length is counted
Device overflows, and generates the Tick pulse signal of a clock cycle, the step-length counter restarts from 0 plus 1 counts.If described
When add-subtract control signal is set to 0, the step-length counter is used to make the counting that subtracts 1 in each pulse period, and the step-length counts son
When module detects a rising edge signal of the benchmark pwm signal Encoder, the step-length counter is opened from pre-set count value
Counting that beginning work subtracts 1, while retaining in the register built in current count value to the step-length counter, to be external motor control
System processed provides the step Numerical based on the pwm signal PWM_IN to be processed, represents the distance value of motor rotation；When the step-length
After the count value of counter is reduced to 0, the step-length counter overflow (i.e. current count value is 0) generates a clock cycle
Tick pulse signal, the step-length counter loads the pre-set count value, then restarts to subtract 1 counting.
Preferably, the step-length counter in the step-length counting submodule is set as 32 digit counters, does not need pair
Count value makees Symbol processing.
As shown in figure 4, the speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module,
For realizing the velocity amplitude of measurement motor rotation by the period for measuring the pwm signal PWM_IN to be processed, actually
Measure the time width between two rising edges of the pwm signal PWM_IN to be processed.Rising edge detection circuit includes a D
Trigger and one and door, input terminal of the input terminal of d type flip flop as rising edge detection circuit, the input terminal connection of trigger
With an input terminal of door, another input terminal of the reversed-phase output connection and door of d type flip flop；The clock end of pulsewidth counter
It is connected with the clock end of d type flip flop, rising edge detection circuit is connected by the reset terminal of output end and pulsewidth counter with door
It connects, the data input pin of the data output end connection intermediate value averaging module of pulsewidth counter, the output end of intermediate value averaging module is made
For the speed signal output end of the speed detector, number of the input terminal of rising edge detection circuit as the speed detector
According to input terminal.The input terminal D of d type flip flop is for receiving the first pwm signal Encoder1, first pwm signal
Encoder1 is that the benchmark pwm signal Encoder scaling down processing obtains；The clock end of d type flip flop is for receiving described the
One sub-frequency clock signal Clk_div1, the first sub-frequency clock signal Clk_div1 is the high frequency clock signal CLK_US points
What frequency obtained.The first pwm signal Encoder1 at the input terminal D of d type flip flop is when the first moment was low level signal, D
Flip/flops latch lives low level signal of the first pwm signal Encoder1 at the first moment, believes by first frequency-dividing clock
After a clock cycle of number Clk_div1, the reversed-phase output of d type flip flopHigh level signal is exported, if D under synchronization
The input terminal D of trigger becomes high level signal, i.e., is simultaneously high level signal with two input terminals of door, the rising edge inspection
Slowdown monitoring circuit can determine that the first pwm signal Encoder1 is rising edge signal, and export by exporting high level signal with door at this time
To the reset terminal reset of the pulsewidth counter.
Under the driving of the first sub-frequency clock signal Clk_div1, when the pulsewidth counter sample detecting is described in
When the rising edge signal of the first pwm signal Encoder1, counted the rising edge signal as reset signal input, often
A reset signal is inputted, the pulsewidth counter is according to the pulse number of the first sub-frequency clock signal Clk_div1
It counts once, thus when obtaining the corresponding described first frequency dividing in a pulse period of the first pwm signal Encoder1
The pulse number of clock signal Clk_div1.As shown in figure 5, the pulsewidth counter often detects first pwm signal
A rising edge signal of Encoder1, the first sub-frequency clock signal Clk_div1 has passed over 4 clock cycle, described
Pulsewidth counter adds 4 on the basis of original count value, as current count value；The two of the first pwm signal Encoder1
Between a rising edge signal, the pulse number of the first sub-frequency clock signal Clk_div1 is 4, and the pulsewidth counter uses
The clock cycle of 4 the first sub-frequency clock signal Clk_div1 removes first pwm signal of one pulse period of sampling
Encoder1.In Fig. 5, confined 4 of the corresponding dotted line of two rising edge signals of the first pwm signal Encoder1
The pulse of the first sub-frequency clock signal Clk_div1, the mark as the pulsewidth for measuring the first pwm signal Encoder1
Standard, and then measure the corresponding motor speed of the pwm signal PWM_IN to be processed.Made under the conditions of the prior art using clock edge
The mode of energy signal drives the pulsewidth counter to be counted, but can have the nonsynchronous problem of clock, the embodiment of the present invention
Drive the pulsewidth counter to the pulsewidth meter of the first pwm signal Encoder1 by the rising edge detection circuit
Number really drives the pulsewidth counter to be counted under high frequency clock signal by Edge check enable signal, so that
Clock is synchronous, improves the precision of the pulse period sampling of the first pwm signal Encoder1.
Preferably, the bit wide numerical value power of the 2 pulsewidth counter is greater than the input end of clock of the pulsewidth counter
Signal frequency and the d type flip flop input terminal D signal frequency ratio.The first sub-frequency clock signal Clk_div1
Highest input frequency be 80MHz, the first sub-frequency clock signal Clk_div1 is set as under the embodiment of the present invention
20MHz.In order to realize that the first pwm signal Encoder1's described in the first sub-frequency clock signal Clk_div1 synchronized sampling is upper
It rises along signal, the ratio and the arteries and veins of the first sub-frequency clock signal Clk_div1 and the first pwm signal Encoder1
The bit wide of wide counter is there are power side's relationship, when the first pwm signal Encoder1 clock frequency is 32Hz, then described the
The clock frequency of one sub-frequency clock signal Clk_div1 and the ratio of the clock frequency of the first pwm signal Encoder1 are
625000.Because 2 20 power are bigger than 625000,20 bits are set by the bit wide of the pulsewidth counter, thus
The bit wide numerical value power for meeting the 2 pulsewidth counter is greater than the clock frequency of the first sub-frequency clock signal Clk_div1
With the ratio of the clock frequency of the first pwm signal Encoder1；Due to the high frequency clock signal CLK_US maximum clock
Frequency is 80MHz, is 4 times of 20MHz, so when the high frequency clock signal CLK_US mono- frequency dividing obtains the described first frequency dividing
Clock signal Clk_div1, and when the first pwm signal Encoder1 clock frequency is left as 32Hz, it need to be by the pulsewidth meter
The bit wide of number device increases 2 bits, and the bit wide numerical value is set as 22 bits, this is as the correlation built in the pulsewidth counter
Register carries out configuration of reservations, and loads corresponding bit wide numerical value under the premise of high frequency clock signal CLK_US input.
The frequency that the d type flip flop of the rising edge detection circuit receives the first sub-frequency clock signal Clk_div1 is higher, Ke Yizeng
The efficiency of strong rising edge detection, although the clutter of jump cannot be filtered off, the first pwm signal Encoder1, which has been subjected to disappear, to be trembled
Processing, therefore clutter influences less.
The data output end of the pulsewidth counter connects the data input pin of the intermediate value averaging module, the pulsewidth meter
The signal of the pulse number of number device output is connected to the intermediate value averaging module, and the output end of the intermediate value averaging module is made
For the speed signal output end of the speed detector.It include a counting sample register inside the intermediate value averaging module,
The pulse number for the output of pulsewidth counter described in real-time storage；The intermediate value averaging module connects the pulsewidth and counts
Device, the intermediate value averaging module control the arteries and veins of the second preset quantity of the pulse number and the counting sample register storage
It rushes number and carries out size comparison, and be ranked up according to comparison result, its intermediate value is then selected to represent the impulse speed signal
speed；Wherein, the pulse number of second preset quantity is examined by sampling in the first pwm signal Encoder1
The pulse of the corresponding first sub-frequency clock signal Clk_div1 in the pulse period for second preset quantity surveyed
Number.The intermediate value averaging module under the present embodiment is conducive to eliminate influence of the signal noise to the pulse number, avoids surveying
There is excessive or too small phenomenon in the pulsewidth of the first pwm signal Encoder1 obtained, to be external motor system acquisition
Stable speed signal.
As shown in Figure 1, the PWM generation module includes second clock pre-divider and pwm signal generator, inside modules
Connection relationship be: the output terminal of clock of second clock pre-divider is connected with the data input pin of pwm signal generator,
Input end of clock of the input end of clock of two clock pre-dividers as the PWM generation module, the output end conduct of comparator
The data output end of pwm signal generator.Specifically, the in second clock pre-divider and the PWM sample detecting module
One clock pre-divider is connected, for receiving sampling clock Clk；Second clock pre-divider, when for by received sampling
Clock Clk scaling down processing is to export the second sub-frequency clock signal Clk_div2, under the present embodiment, the second sub-frequency clock signal Clk_
The clock frequency of div2 can be 72MHz, 40MHz, 20MHz or 10MHz.Second clock pre-divider and pwm signal generator
It is connected, for the second sub-frequency clock signal Clk_div2 to be transferred to pwm signal generator；Pwm signal generator, for connecing
Reference level signal level is received, and according to the frequency division value of the second sub-frequency clock signal Clk_div2 and reference level signal level
Comparison result generate PWM output signal PWM_OUT, specifically, pwm signal generator is by counter by the second frequency-dividing clock
Signal Clk_div2 scaling down processing, then again compared with reference level signal level carries out level, when the second frequency-dividing clock
When the frequency division value of signal Clk_div2 is greater than the level value of reference level signal level, PWM output signal PWM_OUT is high electricity
Flat, otherwise, PWM output signal PWM_OUT is low level.
As shown in fig. 6, the pwm signal generator includes output frequency divider and comparator, the output frequency divider when
Clock output end input terminal compared with one of the comparator connects, and the input terminal of output frequency divider is raw as the pwm signal
The data input pin grown up to be a useful person, data output end of the output end of comparator as the pwm signal generator.The output frequency division
Device divides the second sub-frequency clock signal Clk_div2 for receiving the second sub-frequency clock signal Clk_div2
Frequency is handled.It include a counter inside the output frequency divider under the embodiment of the present invention, which is 10bit
The counter of bit wide, frequency division coefficient 1024, therefore the output frequency divider is by the second sub-frequency clock signal Clk_div2
1024 scaling down processings are carried out, when the clock frequency of the second sub-frequency clock signal Clk_div2 is 72MHz, the output point
The frequency division value of frequency device output is 72MHz/1024=70KHz, can be used as highest output frequency to be compared, so that the pwm signal
The signal of generator output is low-frequency PWM output signal as unit of KHz.
As shown in fig. 6, the comparison input terminal of the comparator be separately connected the frequency division value of the output frequency divider with it is described
Reference level signal level, for the frequency division value and the reference level according to the second sub-frequency clock signal Clk_div2
The level comparison result of signal level exports the PWM output signal PWM_OUT of corresponding level, when the frequency dividing
When value is greater than the level value of the reference level signal level, PWM output signal PWM_OUT is high level；When the frequency division value
When level value less than the reference level signal level, PWM output signal PWM_OUT is low level.Due to the output point
The frequency division coefficient of frequency device and the second sub-frequency clock signal Clk_div2 of input are adjustable, thus PWM export letter
The duty ratio of number PWM_OUT is controllable, while the PWM generation module also generates interrupt signal output, and the PWM is assisted to adopt
The revolving speed of electric system outside the control of sample detection module.
A kind of chip, the chip interior integrate aforementioned processing circuit, the processing circuit include PWM sample detecting module and
PWM generation module；The pwm signal PWM_IN to be processed of the PWM sample detecting module capture chip exterior input, receives chip
The high frequency clock signal CLK_US of internal system clock generator output, and believed to chip exterior output based on PWM to be processed
Number impulse speed signal speed.The PWM generation module is used to receive adopting for the system clock generator output of chip interior
Sample clock Clk, and export the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk, the PWM sampling inspection
It surveys module and the PWM generation module is commonly connected to the sampling clock Clk.Compared with the existing technology, the chip interior collection
At aforesaid filters, it to be used for resampling filter pwm signal PWM_IN to be processed.
Device embodiments described above are only schematical, wherein the unit as illustrated by the separation member
It may or may not be physically separated, component shown as a unit may or may not be physics list
Member, it can it is in one place, or may be distributed over multiple network units.It can be selected according to the actual needs
In some or all of the modules realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property labour in the case where, it can understand and implement.
Claims (10)
1. a kind of filter based on pwm signal, which is applied to the pwm signal of filtering external input, which is characterized in that
The filter includes the d type flip flop and a comparison output module of preset quantity, and the d type flip flop of preset quantity constitutes one in advance
If the shift register of number of bits position, the clock end of the d type flip flop of preset quantity is connected to the clock input of the filter
End, the output end (Q) of the d type flip flop of preset quantity are connected respectively to the data input pin for comparing the preset quantity of output module,
Signal input part of the data input pin of shift register as filter compares the data output end of output module as filtering
The signal output end of device.
2. filter according to claim 1, which is characterized in that in the shift register, in addition to the D triggering of rightmost
The output of each d type flip flop except device terminates to the input terminal of one d type flip flop in the right, the output of the d type flip flop of rightmost
A data input pin into the relatively output module is terminated, the input terminal of leftmost d type flip flop is as shift register
Data input pin.
3. filter according to claim 1, which is characterized in that in the shift register, in addition to leftmost D is triggered
The output of each d type flip flop except device terminates to the input terminal of one d type flip flop in the left side, the output of leftmost d type flip flop
A data input pin into the relatively output module is terminated, the input terminal of the d type flip flop of rightmost is as shift register
Data input pin.
4. filter according to claim 1, which is characterized in that the preset quantity is set as 6, so that the filter will
Level shake in the pwm signal to be processed (PWM_IN) of input less than 5 clock cycle is all filtered as burr, wherein
The clock cycle is the pulse period of the jitter levels of the pwm signal to be processed (PWM_IN).
5. a kind of processing circuit of pwm signal, which is applied to the electric system outside adjusting, which is characterized in that institute
Stating processing circuit includes PWM sample detecting module and PWM generation module；The input end of clock and PWM of PWM sample detecting module are raw
It is connected at the input end of clock of module；
PWM sample detecting module includes that step-length counting submodule, signal pre-divider, speed detector, the first clock divide in advance
Any one of device and the Claims 1-4 filter, wherein the signal input part of the filter is as PWM sample detecting mould
The signal input part of block, output end of the speed signal output end of speed detector as PWM sample detecting module；
The connection relationship of PWM sample detecting inside modules is: the signal output end of the filter counts submodule with step-length simultaneously
The data input pin of block is connected with the input end of clock of signal pre-divider, and the output terminal of clock and speed of signal pre-divider are examined
The data input pin for surveying device is connected；The output terminal of clock phase of the input end of clock of speed detector and the first clock pre-divider
Connection；
PWM generation module includes second clock pre-divider and pwm signal generator, and the connection relationship of inside modules is: second
The output terminal of clock of clock pre-divider is connected with the data input pin of pwm signal generator, second clock pre-divider
The data output end of input end of clock of the input end of clock as PWM generation module, pwm signal generator generates mould as PWM
The output end of block.
6. processing circuit according to claim 5, which is characterized in that include that step-length counts inside the step-length counting submodule
The output end of device and direction register, direction register is connect with the enable end of step-length counter, and the counting of step-length counter is defeated
The counting input end of output end of the outlet as the step-length counting submodule, step-length counter counts submodule as the step-length
The data input pin of block.
7. processing circuit according to claim 5, which is characterized in that the speed detector include rising edge detection circuit,
Pulsewidth counter and intermediate value averaging module；
Rising edge detection circuit includes a d type flip flop and one and door, and the input terminal of d type flip flop is as rising edge detection circuit
Input terminal, input terminal connection and the input terminal of door of trigger, the reversed-phase output connection of d type flip flop is another with door
A input terminal；The clock end of pulsewidth counter is connected with the clock end of d type flip flop, and rising edge detection circuit passes through defeated with door
Outlet is connect with the reset terminal of pulsewidth counter, the data input of the data output end connection intermediate value averaging module of pulsewidth counter
End, speed signal output end of the output end of intermediate value averaging module as the speed detector, rising edge detection circuit it is defeated
Enter data input pin of the end as the speed detector.
8. processing circuit according to claim 7, which is characterized in that the bit wide numerical value power of the 2 pulsewidth counter is big
In the ratio of the signal frequency of the input terminal of the signal frequency and d type flip flop of the input end of clock of the pulsewidth counter.
9. processing circuit according to claim 5, which is characterized in that the pwm signal generator include output frequency divider and
Comparator, the output terminal of clock of output frequency divider input terminal compared with one of comparator connect, the input terminal of output frequency divider
As the data input pin of the pwm signal generator, the output end of comparator is defeated as the data of the pwm signal generator
Outlet.
10. a kind of chip, which is characterized in that the chip interior includes any one of claim 5 to 9 processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811501490.8A CN109391247B (en) | 2018-12-10 | Filter, processing circuit and chip based on PWM signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811501490.8A CN109391247B (en) | 2018-12-10 | Filter, processing circuit and chip based on PWM signal |
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| CN109391247A true CN109391247A (en) | 2019-02-26 |
| CN109391247B CN109391247B (en) | 2024-05-03 |
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| CN113945834A (en) * | 2021-09-30 | 2022-01-18 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
| CN109412582B (en) * | 2018-12-10 | 2024-05-03 | 珠海一微半导体股份有限公司 | PWM signal sampling detection circuit, processing circuit and chip |
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