CN108039883A - A kind of detection method and equipment of phaselocked loop output stable clock signal degree - Google Patents
A kind of detection method and equipment of phaselocked loop output stable clock signal degree Download PDFInfo
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- CN108039883A CN108039883A CN201711164145.5A CN201711164145A CN108039883A CN 108039883 A CN108039883 A CN 108039883A CN 201711164145 A CN201711164145 A CN 201711164145A CN 108039883 A CN108039883 A CN 108039883A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
Abstract
The present invention relates to the detection method and equipment of a kind of phaselocked loop output stable clock signal degree, this method includes：The clock signal for entering the first clock domain is detected, if there is rising edge, sampled signal is obtained, it is transferred to second clock domain, step-by-step counting of the counter to sampled signal out of first clock domain；First clock domain is fed back to, generation stops count signal, and is sent from the first clock domain to second clock domain and stop count signal, and control counter stops counting, and by the count value got storage into counter；The adjacent count value twice got is compared by digital comparator, until the difference of count value twice is less than pre-set value.By synchronous counting twice, if the difference counted twice is less than preset value, shows that phaselocked loop signal output frequency is stablized, avoid the frequent switching of clock frequency, and then solve the problems, such as that pll clock signal output is unstable in integrated circuit.
Description
Technical field
The present invention relates to field, more particularly to a kind of detection method of phaselocked loop output stable clock signal degree, go back at the same time
It is related to a kind of detection device of phaselocked loop output stable clock signal degree.
Background technology
Usually in large-scale digital circuit, key signal that clock signal is run as drive circuit, it is believed
Can number relationship between quality correctly run to circuit.
In the prior art, by taking system-on-chip (SoC) as an example, disparate modules can be operated under different clock domains, so that
Meet to reduce the dynamic power consumption brought by signal upset on the premise of calculated performance requirement as much as possible.What is more, some mould
Block can switch clock frequency because of the change of calculated load in the process of running.
Since in integrated circuit operational process, the frequent switching of clock frequency, causes unstable there are clock signal output
The problem of determining.
The content of the invention
The technical problems to be solved by the invention are to export unstable defect for clock signal of the prior art, there is provided
A kind of detection method of phaselocked loop output stable clock signal degree, also provides a kind of inspection of phaselocked loop output stable clock signal degree
Measurement equipment
The technical solution that the present invention solves above-mentioned technical problem is as follows：
A kind of detection method of phaselocked loop output stable clock signal degree provided by the invention, this method include：
S101：After clock signal enters the first clock domain, when detecting that the clock signal rising edge occurs for the first time,
The clock signal is sampled and obtains sampled signal, the sampled signal is transferred to out of described first clock domain
Two clock domains, control the second counter in the second clock domain to count clock cycle number；
The sampled signal, is fed back to first clock domain by S102, and generation stops count signal, and from described first
Clock domain sends the stopping count signal to the second clock domain, and second meter is controlled by the stopping count signal
Number device stops counting, and the count value got storage is performed step again into the first counter of the first clock domain
S101；
The adjacent count value twice got is compared by digital comparator, until the difference of count value twice
Less than pre-set value.
The beneficial effects of the invention are as follows：
By synchronous counting twice, if the difference counted twice is less than preset value, show phaselocked loop signal output frequency
Stablize.
Based on the above technical solutions, the present invention can also be improved as follows：
Further, the clock frequency of the first counter described in the clock frequency ratio of second counter is high.
Further, the process that control second counter counts the clock cycle number, including：
Within the default unit interval, the clock cycle in the second clock domain is obtained by second counter
Number.
Further, the process that sampled signal is transferred to second clock domain out of first clock domain, described will adopt
Sample signal returns the process of first clock domain from the internal feedback of second clock domain, including：Different multi-level registers is respectively adopted
Realize.
Further, the generation stops the process of count signal, including：
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is trailing edge
When, then generate the stopping count signal；
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is rising edge
When, then after moment progress signal upset, the sampled signal is changed into low level from high level, and generates the stopping and count letter
Number.
Further, the count value of the acquisition stores the process to first counter, including：
Storage signal is got according to the trailing edge；
The count value of acquisition is stored to first counter according to the storage signal.
Further, after first counter gets count value, further include：
Synchronize set operation.
The present invention is using the above-mentioned further beneficial effect of scheme：By multi-level register by signal from low-speed clock domain
Be transferred in high speed clock domain, and stop counting in a manner of changing level so that counter is more accurate must be to pulsimeter
Number, reduces the error of count value twice.
Further, after the stable output, further include：Export original locking signal；
To the original locking signal after the filtering of continuous pre-determined number, locking signal is exported.
The present invention is using the above-mentioned further beneficial effect of scheme：By detecting stable clock signal, output is most
Whole locking signal, solves the problems, such as to export jitter in phase-locked loop circuit.
Present invention also offers a kind of detection device of phaselocked loop output stable clock signal degree, which includes：Count
Device, during for after clock signal enters the first clock domain, detecting that the clock signal rising edge occurs for the first time, to institute
State clock signal to be sampled and obtain sampled signal, when the sampled signal is transferred to second out of described first clock domain
Clock domain, controls the counter in the second clock domain to count clock cycle number；
Storage device, will for the sampled signal to be fed back to first clock domain and generates stopping count signal
The stopping count signal being transferred to the second clock domain out of described first clock domain, passes through the stopping tally control institute
The stopping for stating the counter in second clock domain counts, and the count value got is stored the counter to the first clock domain
In；
Digital comparator, for being compared by digital comparator to the adjacent count value twice got, until
The difference of count value is less than pre-set value twice.
Further, which further includes：Wave filter；
The counting device includes sampling unit, the first multi-level register, synchronous set unit, the first counter, second
Counter and the 3rd counter；
Stating storage device includes the second multi-level register；
First counter and second counter are connected with the digital comparator respectively, and described first counts
Device, second counter and the 3rd counter are sequentially connected in series, the digital comparator respectively with first counter
Connected with second counter, first counter, second counter and second multi-level register by with
Door is connected with the sampling unit, and the sampling unit is connected with first multi-level register, first counter,
Second counter is connected with first multi-level register, first multi-level register and second multi-level register
Connection, the 3rd counter are posted with the synchronous set unit, first multi-level register and second multistage respectively
Storage connects, and the wave filter is connected with the digital comparator.
The beneficial effects of the invention are as follows：By synchronous counting twice, if the difference counted twice is less than preset value, signal
Output frequency is stablized, and avoids the frequent switching of clock frequency in circuit operational process, and then improve pll output signal
Quality.
The advantages of aspect that the present invention adds, will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by present invention practice.
Brief description of the drawings
Fig. 1 is the testing process signal that a kind of phaselocked loop that the embodiment of the present invention one provides exports stable clock signal degree
Figure；
Fig. 2 is that the detection device logic that a kind of phaselocked loop provided by Embodiment 2 of the present invention exports stable clock signal degree is shown
It is intended to；
Fig. 3 is the detection device logic that another phaselocked loop provided by Embodiment 2 of the present invention exports stable clock signal degree
Schematic diagram；
Fig. 4 is a kind of phase-locked loop intergrated circuit structure diagram that the embodiment of the present invention three provides；
Fig. 5 is the letter in a kind of detection process for phaselocked loop output stable clock signal degree that the embodiment of the present invention three provides
Number time diagram.
Embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
Fig. 1 is that a kind of phaselocked loop of the offer of the embodiment of the present invention one exports the detection method of stable clock signal degree, the party
Method includes：
S101, after clock signal enters the first clock domain, when detecting that the clock signal rising edge occurs for the first time,
The clock signal is sampled and obtains sampled signal, the sampled signal is transferred to out of described first clock domain
Two clock domains, control the second counter in the second clock domain to count the clock cycle number；
The sampled signal, is fed back to first clock domain by S102, and generation stops count signal, and from described first
Clock domain sends the stopping count signal to the second clock domain, and second meter is controlled by the stopping count signal
Number device stops counting, and by the count value got storage into the first counter of the first clock domain；Step is performed again
S101；
S103, by digital comparator be compared the adjacent count value twice got, until count value twice
Difference be less than pre-set value.
In the embodiment, in the first clock domain, clock signal transmission is adopted into the first clock domain when to clock signal
During collection, when getting clock signal for the first time and rising edge occur, inputted at this time from high level equivalent to clock signal, the present invention
Using 50% duty cycle, and a cycle of clock signal is obtained, in the present invention, 1 cycle being sampled in the first clock domain
Clock signal equivalent to the signal in first counter in 4 cycles.
After controlling the second counter in the second clock domain to count clock cycle number, and adopted described
Sample signal feeds back to the first clock domain, and according to the state of sampled signal, (sampling is believed when returning to the first clock domain from second clock domain
Number edge whether be trailing edge) generation stop count signal.By the way that this step S101, S102 is performed a plurality of times, by it is adjacent twice
Count value be synchronized in digital comparator, after being compared, until the difference of count value twice is less than pre-set value.Then will
The filtered processing of clock signal after stabilization, exports stable clock signal after stablizing by continuous several times.
Sampled signal in the embodiment is with high level, low level, high level, low level ... in transmitting procedure
Transmission, wherein, 1 clock cycle equivalent to by since a high level to the first time before a high level.
The beneficial effect of the embodiment of the present invention is：By synchronous counting twice, if the difference counted twice is less than preset value,
Then signal output frequency is stablized, and avoids the frequent switching of clock frequency in circuit operational process.
Wherein, alternatively, the clock frequency of second counter is more than the clock frequency of first counter.
In the embodiment, which shares two
A clock domain, i.e. the first clock domain and second clock domain, wherein containing low speed counter in the first clock domain, in present specification
Lclk, that is, low speed counter, lclk (low-speed clock, low speed counter), contain meter at a high speed wherein in second clock domain
(high-speed counter by low speed counter frequency multiplication, such as the clock frequency of the first counter is 1MHz to number device, by frequency multiplication
The clock frequency of technical limit spacing to the second counter is 8MHz), hclk, that is, high-speed counter in present specification, hclk
(high-speed clock, high-speed counter).The first clock domain is low-speed clock domain in the present invention, and 4MHz is chosen in the present invention
RC clocks (i.e. 4MHz low speed counter, be named as clk_4m), when some microcontrollers can carry out generation system without external crystal-controlled oscillation
Clock, can produce clock, i.e. RC clocks by internal RC oscillating circuits.Second clock domain is high speed clock domain in the present invention, the present invention
Choose 96MHz pll clocks (i.e. 96MHz high-speed counters, be named as clk_96m), actually pll clock be phase-locked loop or
Phaselocked loop, for unified integration time pulse signal, enables memory correctly to access data, PLL is used for the feedback technique in oscillator.
It should be noted that clock is equal to counter in the present invention, will not be to the present invention using counter or clock
Scheme impacts, and is only the replacement of title, in order to clearly illustrate technical scheme, using counter.When
No matter much clock frequency is, and the present invention program will not be impacted.Such as the clock frequency of low-speed clock can be 40MHz,
65MHz etc..
Alternatively, the process that sampled signal is transferred to second clock domain out of first clock domain, it is described will sampling
Signal returns the process of first clock domain from the internal feedback of second clock domain, including：It is real that different multi-level registers is respectively adopted
It is existing.
It can be the d type flip flop of multiple series connection that multi-level register is referred in the embodiment, will be sampled and believed by multiple d type flip flops
Number sampled rapidly in second clock domain out of first clock domain.The first clock domain is fed back to from second clock domain by sampled signal
Also can be realized by the d type flip flop of multiple series connection, the setting of multi-level register can be controlled exactly, to prevent metastable state
Interference.
Preferably, the process that control second counter counts the pulse number of the sampled signal,
Including：
Within the default unit interval, the second clock domain clock cycle number is obtained by the counter.
In the embodiment, the lclk in 4 cycles is counted using hclk, and obtains the pulse of the sampled signal in 1 cycle
Number is counted, and determines that hclk stablizes if the continuous a period of time error of counter is less than certain value (of substantially equal), i.e. pll
Lock.
The periodic quantity used in the present invention is not unique, its periodicity may be greater than 1 any integer, no matter using how many
In the cycle, the effect that it brings is within protection scope of the present invention.
It should be noted that hclk (pll clock) is by lclk (lclk_4m) frequency multiplication.Usually school is carried out in chip
RC maximum deviations reachable ± 20% before just, it is contemplated that chip carries out rear end design according to the speed of service of 100MHz, if RC
Upper inclined 20%, it is possible to cause the internal moulds of the sys_pll_lock (phase-lock-ring output frequency stability detection circuit) in Fig. 3
Block setup configurations are unsatisfactory for condition, therefore use high-speed counting of the two divided-frequency clock of hclk as sys_pll_lock modules
Device.Count the clock signal of 1MHz using 48MHz clocks (clock signal can be square-wave signal).Regardless of whether how inclined RC is
The frequency multiplication multiple of difference, hclk and lclk are constant, therefore count value is always 48 or so.
Preferably, the generation stops the process of count signal, including：
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is trailing edge
When, then generate the stopping count signal；
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is rising edge
When, then after moment progress signal upset, the sampled signal is changed into low level from high level, and generates the stopping and count letter
Number.
In the embodiment, when sampled signal feeds back to the first clock domain from second clock domain, sampling in the first clock domain
The edge of signal is likely to occur trailing edge or rising edge, when being just trailing edge, you can directly makes sampled signal to stop
Count signal.During if rising edge, then need carry out signal upset (i.e. high level is changed into low level), at this time, sampled signal by
High level is changed into low level, its edge is changed into trailing edge from rising edge, then makes sampled signal to stop count signal.
Preferably, the count value of the acquisition stores the process to first counter, including：
Storage signal is got according to the trailing edge；
The count value of acquisition is stored to first counter according to the storage signal.
In the embodiment, the present invention is triggered using trailing edge, i.e., when sampled signal is from second clock domain feedback meeting first
During clock domain, the edge for detecting sampled signal is trailing edge, then obtains trigger command, and then gets storage signal, performs general
The count value of acquisition is stored into first counter.
Preferably, after first counter gets count value, further include：
Synchronize set operation.
The synchronous set of the embodiment is mainly used for being zeroed out the count value that the register in the first clock domain stores
Operation.Specific synchronization set process can middle embodiment three parts as detailed below.
Alternatively, after the stable output, further include：Export original locking signal；
To the original locking signal after the filtering of continuous pre-determined number, locking signal is exported.
In the embodiment, 1MHz clock signals (i.e. duty cycle 50% is counted using 48MHz high-speed counters hclk_div
Square-wave signal), obtained by 4 scaling down processings), therefore the second counter should count up to 48 or so, count value stability criterion is error
Less than 8 (low 3 of count difference value absolute value is 0 twice, and error criterion can be configured by register by software).
Count value judge be less than error amount after, clock signal be filtered again after stabilization, it is necessary to continuous several times filter,
And export pll_lock (i.e. phase lock loop locks).
It should be noted that the numerical value 8 used, numerical value 4 are only the data of currently preferred one embodiment, if adopting
His data are allowed to reach identical effect with it, within protection scope of the present invention.
In addition, sys_pll_lock (i.e. phase-locked loop intergrated circuit) of the present invention provides asynchronous reset and enable signal, system
PLL likewise enters dormancy during dormancy, and enable signal is set to 0 for resetting pll_lock (phase lock loop locks) at this time.
The beneficial effect of the embodiment of the present invention is：By synchronous counting twice, if the difference counted twice is less than preset value,
Then signal output frequency is stablized, and avoids the frequent switching of clock frequency in circuit operational process.
Fig. 2 embodiment of the present invention two additionally provides a kind of detection device of phaselocked loop output stable clock signal degree, it is special
Sign is that the device includes：
Counting device 11, for after clock signal enters the first clock domain, detecting that the clock signal goes out for the first time
During existing rising edge, the clock signal is sampled and obtains sampled signal, by the sampled signal from first clock
Second clock domain is transferred in domain, controls the counter in the second clock domain to count clock cycle number；
Storage device 12, stops count signal for the sampled signal to be fed back to the first clock domain generation, will
The stopping count signal being transferred to the second clock domain out of described first clock domain, passes through the stopping count signal control
Make the counter in the second clock domain to stop counting, and the count value got is stored into the counter to the first clock domain
In；
Digital comparator 13, for being compared by digital comparator to the adjacent count value twice got, directly
Difference to count value twice is less than pre-set value.
Preferably, as shown in Figure 3, there is provided a kind of detection device of phaselocked loop output stable clock signal degree, the device
Further include：Wave filter 14；
The counting device 11 includes sampling unit 111, the first multi-level register 112, synchronous set unit 113, first
Counter 114, the second counter 115 and the 3rd counter 116；
Stating storage device 12 includes the second multi-level register 121；
First counter 114 and second counter 115 are connected with the digital comparator 13 respectively, and described
One counter 114, second counter 115 and the 3rd counter 116 are sequentially connected in series, and the digital comparator 13 is distinguished
Connected with first counter 114 and second counter 115, first counter 114, second counter
115 and second multi-level register 121 by being connected with door 15 with the sampling unit 111, the sampling unit 111
Connected with first multi-level register 112, first counter 114, second counter 115 and described first are multistage
Register 112 connects, and first multi-level register 112 and second multi-level register 121 connect, the 3rd counter
116 connect with the synchronous set unit 113, first multi-level register 112 and second multi-level register 121 respectively
Connect, the wave filter 14 and the digital comparator 13 connect.
In the embodiment, after clock signal enters the first clock domain, sampling unit 111 detects clock signal for the first time
When there is rising edge, sampling unit 111 samples clock signal and obtains sampled signal, and sampling unit 111, which will sample, to be believed
Number second clock domain being transferred to out of first clock domain, (sampled signal is transferred to the first multi-level register 112 by sampling unit 111
Afterwards, then sampled signal is transferred to second clock domain by the first multi-level register 112 again), which controls in second clock domain
The second counter 115 clock cycle number is counted；Sampled signal is fed back to first clock domain and (adopted by the equipment
After sampled signal is transferred to the second multi-level register 121 by sample unit 111, then the second multi-level register 121 again believes sampling
Number it is transferred to second clock domain), the generation of sampling unit 111 stops count signal, and sampling unit 111 will stop count signal from the
Second clock domain (process is same as above, and is repeated no more) is transferred in one clock domain, which controls the 3rd according to count signal is stopped
Counter 116 stops counting, and the first counter 114 and second of the count value got storage to the first clock domain is counted
In device 115.
Digital comparator 13 is compared the adjacent count value twice got, until the difference of count value twice is small
In pre-set value.Then after stable clock signal is handled by wave filter 14, locking signal is exported.
Wherein, synchronous set unit 113 can remove the count value of the second counter storage, in order to carry out second of counting.
In the embodiment, sampling unit 111 can be a d type flip flop, and the first multi-level register 112 can be the D of 3 series connection
Trigger, synchronous set unit 113 can be the d type flip flop of two series connection, and two multi-level registers 121 can be the D triggerings of 3 series connection
Device.There are sampling unit 111, the first counter 114, the second counter 115, digital comparator and wave filter in first clock domain；
There is synchronous 113 and the 3rd counter 116 of set unit in second clock domain.
It should be noted that the specific device used in above-described embodiment is only preferred embodiment scheme, if other
There are similar combination of devices or identical design within the protection domain of the present invention program.
The beneficial effect of the embodiment of the present invention is：By synchronous counting twice, if the difference counted twice is less than preset value,
Then signal output frequency is stablized, and avoids the frequent switching of clock frequency in circuit operational process.
For the technological thought that the present invention is further explained, below in conjunction with the attached drawing in the present invention, in the present invention
Technical solution carries out clear, complete description.
The embodiment of the present invention three provides a kind of detection method of phaselocked loop output stable clock signal degree.
In the embodiment of the present invention, the first clock domain is the low speed counter of 4MHz, and second clock domain is the high speed meter of 96MHz
Number device, as shown in Figure 3.
In a preferred embodiment of the invention, it is first determined a counter is low speed counter, then by its clock times
Frequency obtains that the counter of a 4MHz is determined as low speed in another clock, i.e. high-speed counter, such as the present invention after handling
Counter, then by will obtain the counter of another 96MHz after its process of frequency multiplication, which is high-speed counter.
Integrated circuit flow diagram is illustrated in figure 3, segmentation by a dotted line obtains A, B, C three parts workspace, wherein A
Part works in low-speed clock domain lclk, and two N bit counter in part A are the first counter (low speed counter),
For storing adjacent count value twice.The device that "=" is indicated in figure is digital comparator, and lock filter are wave filter.C
The N bit counter that work in high speed clock domain hclk, C of part are the second counter (high-speed counter), the counter
Different from the counter in part A, the counter in the part is used to count and store, and the counter in part A is only used for
Storage, is also useful for the register of synchronous set operation.Part B is mainly the reliable synchronization of the clock signal between A, B, is used at the same time
In control signal beat, part B is the d type flip flop of multiple series connection.
Specific high-speed counter is as follows to the pulse number counting operation of clock signal：
The process of clock signal synchronization in first clock domain (low-speed clock domain) to second clock domain (high speed clock domain)：
sample_l→sample_l1h→sample_l2h→sample_h.(clock signal is gathered in low-speed clock domain, is adopted
Sample signal sample_l, then samples to high speed clock domain by multistage d type flip flop, that is, is changed into sample_h)
Sample_h2l → hclk_cnt_clear_buf [0] → hclk_cnt_clear_buf [1] is (herein synchronously to put
Bit manipulation, during sampled signal sample_h is fed back to low-speed clock domain from high speed clock domain, passes through in sampled signal
During the d type flip flop of the second level, by the synchronous set operation of trailing edge triggering of sampled signal sample_h2l, here by high electricity
Flat, i.e., 1 control second counter resets behaviour
Make, wherein 0 represents low level, when running into low level, to be directly changed to high level).
Sampled signal sample_h in high speed clock domain is synchronized to the process in low-speed clock domain：
Sample_h → sample_h1l → sample_h2l → sample_h3l is (with above-mentioned synchronizing process, herein no longer
Repeat)
If sample_l==1'b0＆＆sample_h3l==1'b0, (1'b0 can regard low level as) makes
Sample_l=1'b1 (can regard high level as), start once sample, sample_l by three-level d type flip flop sampled rapidly to
sample_h.When getting sample_h==1'b1, sample_h is since in high speed clock domain, hclk_cnt is (at a high speed
Counter) start counting up, and sampled back in lclk clock domains.If sample_h3l==1'b1, makes sample_l=
1'b0, stops counting.Sample_l (signal has become to stop count signal at this time) is sampled rapidly by three-level register
To sample_h.When getting sample_h==1'b0, hclk_cnt stops counting., will using sample_l trailing edges
In hclk_cnt count value (at this time, hclk_cnt has stopped counting) storage arrive to lclk_cnt (i.e. low speed counter, this
In be two low speed counters, the neighbouring twice count value of storage, as shown in Figure 3).
After counting, set operation is synchronized, sample_h2l trailing edges are synchronized to hclk_cnt_clear_
buf[1].Hclk_cnt is reset using hclk_cnt_clear_buf [1] trailing edge.
Count value twice is compared finally by digital comparator, if error is less than pre-set value, access value here
8, for example the first count value is 95, the second count value is 99, error amount 4,4<8, then clock signal output frequency is stablized, and obtains
Original locking signal, by continuously for several times after filtering process, exporting locking signal.
Fig. 4 is the oscillogram in clock signal samples counting process, and the signal of two clock domains is respectively divided in figure
Two group, wherein u0group belong to low-speed clock domain (lclk domains).When signal name the last letter shows its place
Clock domain, or driven for clock.Such as sample_l for sampled signal in low-speed clock domain, l therein represents low-speed clock domain,
And sample_l1h, h herein are not represented in high speed clock domain, but clock drive part, that is, sampled signal is more
Transmission in level d type flip flop, l1h is actually the conversion process in multistage d type flip flop transmitting procedure here, for the ease of clear
The process is expressed, and uses l/h+ numerical value (which time)+h/l to be indicated.
In Fig. 4, mark sample area by two transversals, it can be seen that each signal of sample area oscillogram and
The numerical value situation of count value memory storage, for example, 005 (005 is label, sees Fig. 4) lclk is the oscillogram of low speed counter output,
And the oscillogram that 006sample_l is sampled signal, four cycles of its oscillogram exported for low speed counter, and sample
Region acquires the clock signal in 1 cycle.015sample_l2h is sampled to high-frequency clock for sampled signal from low-speed clock domain
During the process in domain, by the signal waveforms after the d type flip flop of the second level, 018 is that high-speed counter corresponding digital 60 is counting
Value, 010 for low speed count value 60 is exactly the count value stored, equivalent to being synchronized to low speed counter from high-speed counter
In, it 60 is hexadecimal, switchs to the decimal system for 96, i.e. 96MH counters must after handling the pulse number of clock signal
To 96, switch to hexadecimal, i.e., 60.
Two-stage register in low-speed clock domain exports original locking signal after relatively, by the filter with lag function
Final locking signal is exported after ripple device.
Extremely small-scale totally digital circuit and PLL reference clocks (low speed counter) and frequency multiplication is used only in the embodiment of the present invention
Clock (high-speed counter), to judge PLL frequency stabilities；Frequency stability criterion supports software configuration, can change；Locking letter
Number filtering has lagging characteristics, can export lock=0 after PLL losing locks immediately, and need to stablize a period of time after locking just can be defeated
Go out lock=1；Wave filter supports software configuration for signal stabilization time length, for PLL Clock Multiplier Factors, reference clock speed
Deng no requirement (NR).
More than, it is only embodiment of the invention, but protection scope of the present invention is not limited thereto, and it is any to be familiar with
Those skilled in the art the invention discloses technical scope in, various equivalent modifications or substitutions can be readily occurred in,
These modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be wanted with right
Subject to the protection domain asked.
Claims (10)
1. a kind of detection method of phaselocked loop output stable clock signal degree, it is characterised in that this method includes：
S101：After clock signal enters the first clock domain, when detecting that the clock signal rising edge occurs for the first time, to institute
State clock signal to be sampled and obtain sampled signal, when the sampled signal is transferred to second out of described first clock domain
Clock domain, controls the second counter in the second clock domain to count clock cycle number；
S102：The sampled signal is fed back into first clock domain, generation stops count signal, and from first clock
Domain sends the stopping count signal to the second clock domain, and second counter is controlled by the stopping count signal
Stop counting, and the count value got storage is performed into step S101 again into the first counter of the first clock domain；
The adjacent count value twice got is compared by digital comparator, until the difference of count value twice is less than
Pre-set value.
2. according to the method described in claim 1, it is characterized in that, the clock frequency in the second clock domain is more than described first
The clock frequency of clock domain.
3. according to the method described in claim 1, it is characterized in that, the second counter of the control carries out clock cycle number
The process of counting, including：
Within the default unit interval, the clock cycle number in second clock domain is obtained by second counter.
4. according to the method described in claim 1, it is characterized in that, described be transferred to sampled signal out of first clock domain
The process of two clock domains, the process that sampled signal is returned to first clock domain from the internal feedback of second clock domain, including：Point
Cai Yong not respective multi-level register realization.
5. according to the method described in claim 1, it is characterized in that, it is described generation stop count signal process, including：
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is trailing edge,
Then get the stopping count signal；
When the sampled signal is transferred to first clock domain, if the edge for detecting the sampled signal is rising edge,
After then carrying out signal upset, the sampled signal is changed into low level from high level, and generates the stopping count signal.
6. according to the method described in claim 5, it is characterized in that, the count value of the acquisition is stored to first counter
Process, including：
Storage signal is got according to the trailing edge；
The count value of acquisition is stored to first counter according to the storage signal.
7. according to the method described in claim 1, it is characterized in that, after first counter gets count value, also wrap
Include：
Synchronize set operation.
8. according to the method described in claim 1, it is characterized in that, after the stable output, further include：Export original locking letter
Number；
To the original locking signal after the filtering of continuous pre-determined number, locking signal is exported.
9. a kind of detection device of phaselocked loop output stable clock signal degree, it is characterised in that the equipment includes：
Counting device, when detecting that the clock signal rising edge occurs for the first time, is sampled and is obtained to the clock signal
To sampled signal, the sampled signal is transferred to second clock domain out of described first clock domain, controls the second clock
Counter in domain counts clock cycle number；
Storage device, for the sampled signal to be fed back to first clock domain and generates stopping count signal, by described in
Stop count signal and the second clock domain is transferred to out of described first clock domain, by the described in the stopping tally control
The stopping of counter in two clock domains counts, and by the count value got storage into the counter of the first clock domain；
Digital comparator, for being compared by digital comparator to the adjacent count value twice got, until twice
The difference of count value is less than pre-set value.
10. equipment according to claim 9, it is characterised in that the device further includes：Wave filter；
The counting device includes sampling unit, the first multi-level register, synchronous set unit, the first counter, the second counting
Device and the 3rd counter；
The storage device includes the second multi-level register；
First counter and second counter are connected with the digital comparator respectively, first counter, institute
State the second counter and the 3rd counter be sequentially connected in series, the digital comparator respectively with first counter and described
Second counter connect, first counter, second counter and second multi-level register by with door
It is connected with the sampling unit, the sampling unit is connected with first multi-level register, first counter, described
Two counters are connected with first multi-level register, and first multi-level register is connected with second multi-level register,
3rd counter connects with the synchronous set unit, first multi-level register and second multi-level register respectively
Connect, the wave filter is connected with the digital comparator.
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