CN106357266A - Locked detecting circuit, method and phase-locked circuit - Google Patents
Locked detecting circuit, method and phase-locked circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
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Abstract
The invention discloses a locked detecting circuit, a method and a phase-locked circuit. The locked detecting circuit is respectively connected with a reference signal input terminal and a feedback signal input terminal of a phase-locked loop, and a controller. The locked detecting circuit comprises a phase comparison circuit and a state detection circuit. The phase comparison circuit is used for receiving reference signals from a reference signal input terminal of the phase-locked loop, receiving feedback signals from a feedback signal input terminal of the phase-locked loop, and receiving operation mode signals from the controller. Besides, phase comparison circuit is also able to generate comparison signals based on the reference signals, the feedback signals, and the operation mode signals. The state detection circuit is used for acquiring clock signals and comparing the clock signals, detecting the operation status of the phase-locked loop. The locked detecting circuit has a simple structure.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a lock detection circuit, a lock detection method, and a phase lock circuit.
Background
A phase-locked loop is a closed-loop control circuit that can maintain the same frequency and a constant phase difference between an output feedback signal and an input reference signal in a normal operating state (i.e., a locked state), and is generally used in the technical fields of broadcasting, communication, frequency synthesis, clock synchronization, and the like. A conventional phase-locked loop generally includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider. Since a system using the phase-locked loop is prone to malfunction when the phase-locked loop is in an abnormal operating state (i.e., an out-of-lock state), a special lock detection circuit is required to determine the operating state of the phase-locked loop, so as to detect and maintain the phase-locked loop in the out-of-lock state in time.
The lock detection circuit in the related art includes many devices, and generally includes two frequency dividers, two counters, and a comparator, and the lock detection circuit has a complicated structure.
Disclosure of Invention
To solve the problems in the related art, the present invention provides a lock detection circuit, a lock detection method, and a phase lock circuit that simplify the structure of the lock detection circuit. The technical scheme is as follows:
in one aspect, a lock detection circuit is provided, the lock detection circuit being coupled to a reference signal input and a feedback signal input of a phase locked loop, respectively, and a controller, the lock detection circuit comprising: a phase comparison circuit and a state detection circuit coupled to the phase comparison circuit; the phase comparison circuit is configured to receive a reference signal from a reference signal input of the phase-locked loop, a feedback signal from a feedback signal input of the phase-locked loop, and an operation mode signal from the controller, respectively, wherein the operation mode signal indicates an operation mode of the phase-locked loop in an ideal locking state, the operation mode including a first operation mode in which a phase of the reference signal lags a phase of the feedback signal and a second operation mode in which the phase of the feedback signal lags the phase of the reference signal; the phase comparison circuit is further configured to generate a comparison signal according to the reference signal, the feedback signal and the operating mode signal, where the comparison signal indicates whether a phase relationship of the phase-locked loop in an actual operating state is the same as a phase relationship of the phase-locked loop in the ideal locking state, where the phase relationship of the phase-locked loop in the actual operating state is the phase relationship of the reference signal and the feedback signal; the state detection circuit is used for acquiring a clock signal and the comparison signal and detecting the working state of the phase-locked loop according to the clock signal and the comparison signal, wherein the working state comprises a locking state or an unlocking state. The locking detection circuit provided by the invention can realize the detection of the working state of the phase-locked loop through the phase comparison circuit and the state detection circuit, and the locking detection circuit has fewer elements and simpler circuit structure.
Optionally, the phase comparison circuit may include: a Data flip-flop (English; D flip-flop for short) and a logic gate; the clock signal input end of the D flip-flop is used for receiving the reference signal, the data signal input end of the D flip-flop is used for receiving the feedback signal, the output end of the D flip-flop is connected with the first input end of the logic gate, and the D flip-flop is used for sampling the level of the feedback signal by taking the reference signal as a sampling clock signal to obtain a sampling signal; the logic gate is used for receiving the sampling signal through a first input end, receiving the working mode signal through a second input end, and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
Optionally, the phase comparison circuit may include: d flip-flop and logic gate; the clock signal input end of the D flip-flop is used for receiving the feedback signal, the data signal input end of the D flip-flop is used for receiving the reference signal, the output end of the D flip-flop is connected with the first input end of the logic gate, and the D flip-flop is used for sampling the level of the reference signal to obtain a sampling signal by taking the feedback signal as a sampling clock signal; the logic gate is used for receiving the sampling signal through a first input end and receiving the working mode signal through a second input end, and the logic gate is used for carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
Optionally, the logical operation is one of an exclusive-or operation or an exclusive-or operation.
Optionally, the state detection circuit may include: a counter and a comparator; the input end of the counter is used for receiving the comparison signal, the clock signal end of the counter is used for receiving the clock signal, the output end of the counter is connected with the input end of the comparator, and the counter is used for counting the preset level in the comparison signal within the preset counting period according to the clock signal to obtain a counting result and sending the counting result to the comparator; the comparator is used for comparing the counting result with a preset counting threshold value and detecting the working state of the phase-locked loop according to the comparison result.
Optionally, when the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the first working mode with a high level and the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the second working mode with a low level, the preset level is the high level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal and the comparison signal is generated by the logic gate through an xor operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a low level.
Optionally, when the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the first working mode with a low level and the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the second working mode with a high level, the preset level is the low level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal and the comparison signal is generated by the logic gate through an xor operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a high level.
Optionally, the comparator is specifically configured to: comparing the counting result with a preset counting threshold, and determining that the working state of the phase-locked loop is in an out-of-lock state when the counting result is greater than the counting threshold; and when the counting result is not greater than the counting threshold value, determining that the working state of the phase-locked loop is a locking state.
Optionally, the clock signal acquired by the state detection circuit may be the reference signal; alternatively, the lock detection circuit may further include: a clock generator, the state detection circuit may also obtain the clock signal from the clock generator.
In a second aspect, a lock detection method is provided, which is applied to a lock detection circuit, and the lock detection circuit includes: a phase comparison circuit and a state detection circuit coupled to the phase comparison circuit, the lock detection circuit being coupled to a reference signal input and a feedback signal input of a phase locked loop, respectively, and to a controller, the method comprising: receiving a reference signal from a reference signal input of the phase locked loop, a feedback signal from a feedback signal input of the phase locked loop, and an operating mode signal from the controller, respectively, wherein the operating mode signal indicates an operating mode of the phase locked loop in an ideal locked state, the operating mode including a first operating mode in which a phase of the reference signal lags a phase of the feedback signal and a second operating mode in which the phase of the feedback signal lags the phase of the reference signal; generating a comparison signal according to the reference signal, the feedback signal and the working mode signal, wherein the comparison signal indicates whether the phase relationship of the phase-locked loop in the actual working state is the same as the phase relationship of the phase-locked loop in the ideal locking state, and the phase relationship of the phase-locked loop in the actual working state is the phase relationship of the reference signal and the feedback signal; acquiring a clock signal and a comparison signal, and detecting the working state of the phase-locked loop according to the clock signal and the comparison signal, wherein the working state comprises a locking state or an unlocking state. The locking detection method provided by the invention can receive the working mode signal from the controller and detect the working state of the phase-locked loop based on the working mode signal, and the detection process is simpler and the detection efficiency is higher.
Optionally, the specific process of generating the contrast signal according to the reference signal, the feedback signal and the operating mode signal may include: taking the reference signal as a sampling clock signal, and sampling the level of the feedback signal to obtain a sampling signal; and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
Optionally, the specific process of generating the comparison signal according to the reference signal, the feedback signal and the working mode signal may further include: taking the feedback signal as a sampling clock signal, and sampling the level of the reference signal to obtain a sampling signal; and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
Optionally, the logical operation may be one of an exclusive-or operation or an exclusive-or operation.
Optionally, the process of detecting the working state of the phase-locked loop according to the clock signal and the comparison signal may specifically include: counting the preset level of the comparison signal within a preset counting period according to the clock signal to obtain a counting result; and comparing the counting result with a preset counting threshold value, and detecting the working state of the phase-locked loop according to the comparison result.
Optionally, when the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the first working mode with a high level and the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the second working mode with a low level, the preset level is the high level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal and the comparison signal is generated by the logic gate through an xor operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a low level.
Optionally, when the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the first working mode with a low level and the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the second working mode with a high level, the preset level is the low level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal and the comparison signal is generated by the logic gate through an xor operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a high level.
Optionally, the comparing the counting result with a preset counting threshold, and detecting the operating state of the phase-locked loop according to the comparing result includes: comparing the counting result with a preset counting threshold, and determining that the working state of the phase-locked loop is in an out-of-lock state when the counting result is greater than the counting threshold; and when the counting result is not greater than the counting threshold value, determining that the working state of the phase-locked loop is a locking state.
Optionally, the clock signal may be the reference signal; alternatively, the clock signal may be a signal generated by a clock generator.
In a third aspect, a phase-locked circuit is provided, which includes: a phase locked loop, a controller and a lock detection circuit as described in the first aspect, the lock detection circuit being coupled to a reference signal input and a feedback signal input of the phase locked loop, respectively, and to the controller; the phase-locked loop is used for sending a reference signal to the locking detection circuit through the reference signal input end and sending a feedback signal to the locking detection circuit through the feedback signal input end; the controller is configured to send an operating mode signal to the lock detection circuit, the operating mode signal indicating an operating mode of the phase locked loop in an ideal locked state, the operating mode including a first operating mode in which the phase of the reference signal lags the phase of the feedback signal and a second operating mode in which the phase of the feedback signal lags the phase of the reference signal.
In summary, the technical scheme provided by the invention has the following beneficial effects:
the invention provides a lock detection circuit, a lock detection method and a phase-locked circuit, wherein the lock detection circuit comprises a phase comparison circuit and a state detection circuit, the phase comparison circuit can generate a comparison signal for indicating the phase relation between a reference signal and a feedback signal according to a working mode signal, and the state detection circuit can generate a state detection signal according to the reference signal and the comparison signal. Compared with the lock detection circuit in the related art, the lock detection circuit provided by the invention only comprises one trigger, one logic gate, one counter and one comparator, and the lock detection circuit has fewer elements and simpler circuit structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A is a schematic structural diagram of a phase-locked loop according to an embodiment of the present invention;
fig. 1B is a schematic diagram of a partial structure of a phase-locked loop according to an embodiment of the present invention;
fig. 1C is a schematic structural diagram of another phase-locked loop according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an application scenario of a lock detection circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a lock detection circuit according to an embodiment of the present invention;
FIG. 4A is a schematic diagram of another lock detection circuit according to an embodiment of the present invention;
FIG. 4B is a timing relationship diagram of a reference signal and a feedback signal according to an embodiment of the present invention;
FIG. 4C is a timing diagram of another reference signal and feedback signal according to an embodiment of the present invention;
fig. 5 is a flowchart of a lock detection method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1A is a schematic structural diagram of a phase-locked loop according to an embodiment of the present invention, and as shown in fig. 1A, the phase-locked loop may include a crystal buffer 101, a phase frequency detector 102, a charge pump 103, a low-pass filter 104, a voltage-controlled oscillator 105, and a frequency divider 106. The crystal oscillator buffer 101 is configured to buffer a crystal oscillator signal input by a crystal oscillator input terminal to generate a reference signal, and output the reference signal to the phase frequency detector 102, the phase frequency detector 102 is configured to detect a phase difference between the reference signal and a feedback signal, and output a pulse control signal to the charge pump 103 according to the phase difference, the charge pump 103 is configured to generate a charging current or a discharging current according to the pulse control signal, the low-pass filter 104 is configured to output a control voltage to the voltage controlled oscillator 105 according to the charging current or the discharging current, and the voltage controlled oscillator 105 may generate an oscillation voltage according to the control voltage, so that the frequency divider 106 divides the oscillation voltage to generate the feedback signal, and inputs the feedback signal to the phase frequency detector 102. As can be seen from fig. 1A, the phase frequency detector, the charge pump, the low pass filter, the voltage controlled oscillator, and the frequency divider in the phase locked loop may form a feedback system that can adjust the frequency and phase of the feedback signal such that the frequency and phase of the feedback signal "lock" to the frequency and phase of the reference signal. That is, when the phase-locked loop is in a locked state, the frequency and the phase of the reference signal and the frequency of the feedback signal are the same, or the frequency of the reference signal and the frequency of the feedback signal are the same, and the phase difference is constant.
Fig. 1B is a schematic diagram of a partial structure of a phase-locked loop according to an embodiment of the present invention, and as shown in fig. 1B, in order to avoid the nonlinearity of the charge pump 103 in the phase-locked loop from affecting the operating state of the phase-locked loop, a compensation current (I) may be added to an output terminal of the charge pump 103 in generalOffset)31 to improve the non-linearity of the charge pump 103, the phase locked loop that adds compensation current is also referred to as an Offset CP phase locked loop. When the Offset CP phase-locked loop is in a locked state, a certain phase difference exists between the reference signal and the feedback signal. FIG. 1C is a schematic representation of the present inventionAnother exemplary embodiment provides a schematic structure of a phase-locked loop, as shown in fig. 1C, where the phase-locked loop includes a crystal buffer 21, a phase detector 22, a low-pass filter 23, a voltage-controlled oscillator 24, and a frequency divider 25, and a charge pump is not provided in the phase-locked loop, and the phase-locked loop of this Type is also referred to as a Type-I phase-locked loop, and when the Type-I phase-locked loop is in a locked state, a fixed phase difference is also provided between a reference signal and a feedback signal. For the phase-locked loop with a fixed phase difference between the reference signal and the feedback signal when in the locked state, two operation modes can be included: in the first mode of operation, the phase of the reference signal lags the phase of the feedback signal, and in the second mode of operation, the phase of the feedback signal lags the phase of the reference signal.
Fig. 2 is a schematic view of an application scenario of a lock detection circuit according to an embodiment of the present invention, and referring to fig. 2, the lock detection circuit 00 may be coupled to a reference signal input terminal a and a feedback signal input terminal b of a phase-locked loop 10, and a controller 20, respectively. Fig. 3 is a schematic structural diagram of a lock detection circuit according to an embodiment of the present invention, and as shown in fig. 3, the lock detection circuit may include: a phase comparator circuit 01 and a state detector circuit 02 coupled to the phase comparator circuit.
The phase comparison circuit 01 is configured to receive a reference signal from a reference signal input terminal a of the phase locked loop 10, a feedback signal from a feedback signal input terminal b of the phase locked loop 10, and an operation mode signal from the controller 20, wherein the operation mode signal indicates an operation mode of the phase locked loop in an ideal locking state, and the operation mode includes a first operation mode in which a phase of the reference signal lags a phase of the feedback signal and a second operation mode in which the phase of the feedback signal lags the phase of the reference signal.
The phase comparison circuit 01 is further configured to generate a comparison signal according to the reference signal, the feedback signal and the operating mode signal, where the comparison signal indicates whether a phase relationship of the phase-locked loop in an actual operating state is the same as a phase relationship of the phase-locked loop in the ideal locking state, where the phase relationship of the phase-locked loop in the actual operating state is the phase relationship of the reference signal and the feedback signal.
The state detection circuit 02 is configured to obtain a clock signal and the comparison signal, and detect an operating state of the phase-locked loop according to the clock signal and the comparison signal, where the operating state includes a locked state or an unlocked state.
Wherein the operation mode of the phase-locked loop 10 can be controlled by the controller 20, for example, for the Offset CP phase-locked loop shown in fig. 1B, the operation mode of the phase-locked loop in the ideal locking state can be controlled by controlling the direction of the Offset current, specifically, when the direction of the Offset current is controlled to flow from the charge pump 103 to the low-pass filter 104, the operation mode of the phase-locked loop in the ideal locking state is the first operation mode; when the direction of the Offset current is controlled to flow from the low pass filter to the charge pump (i.e., the flow direction shown in fig. 1B), the operation mode of the phase-locked loop in the ideal locking state is the second operation mode. For different types of phase-locked loops, the control method of the controller for the operating mode is also different, which is not limited in the embodiment of the present invention.
Fig. 4A is a schematic structural diagram of another lock detection circuit according to an embodiment of the present invention, and as shown in fig. 4A, in an alternative implementation manner of the present invention, the phase comparison circuit 01 may include: d flip-flop 011 and logic gate 012.
On the one hand, the clock signal input terminal CK of the D flip-flop 011 is configured to receive the reference signal, the data signal input terminal D of the D flip-flop is configured to receive the feedback signal, the output terminal Q of the D flip-flop is connected to the first input terminal of the logic gate 012, and the D flip-flop 011 is configured to sample the level of the feedback signal by using the reference signal as a sampling clock signal to obtain a sampling signal.
On the other hand, the clock signal input terminal CK of the D flip-flop 011 can also receive the feedback signal, the data signal input terminal D of the D flip-flop 011 receives the reference signal, and the output terminal of the D flip-flop 011 is connected to the first input terminal of the logic gate, at this time, the D flip-flop can sample the level of the reference signal by using the feedback signal as the sampling clock signal to obtain the sampling signal.
Referring to fig. 4A, the logic gate 012 is configured to receive the sampling signal output by the D flip-flop through the first input terminal, receive the operation mode signal through the second input terminal, and perform a logic operation according to the sampling signal and the operation mode signal to generate a comparison signal. Specifically, the logic gate may be an exclusive or gate, and the exclusive or gate may perform an exclusive or operation on the sampling signal and the working mode signal to generate the comparison signal; alternatively, the logic gate may be an exclusive nor gate, and the exclusive nor gate may perform an exclusive nor operation on the sampling signal and the operation mode signal to generate the comparison signal.
In practical applications, the phase comparison circuit 01 may further include a plurality of logic gates 012, such as and gates, or nand gates, which can achieve the logic effect of exclusive or gates or exclusive or gates.
Further, referring to fig. 4A, in an alternative implementation manner of the present invention, the state detection circuit 02 may include: a counter 021 and a comparator 022.
The input end of the counter 021 is configured to receive the comparison signal, the clock signal end CK of the counter 021 is configured to receive a clock signal, the output end of the counter 021 is connected to the input end of the comparator 022, and the counter 021 is configured to count a preset level in the comparison signal in a preset counting period according to the clock signal to obtain a counting result, and send the counting result to the comparator 022.
With reference to fig. 4A, the lock detection circuit may further include: the clock generator 03, the clock signal received by the counter 021 may be a digital clock signal generated by the clock generator 03, and the frequency of the clock signal may be preset according to actual conditions; alternatively, the reference signal input terminal of the phase-locked loop may be directly coupled to the clock signal terminal of the counter 021, that is, the reference signal of the phase-locked loop is used as the clock signal of the counter 021. In addition, the preset counting period in the counter 021 can be flexibly set according to the actual situation of the lock detection circuit, and generally, the longer the counting period is, the higher the detection precision of the lock detection circuit is.
The comparator 022 is configured to compare the counting result sent by the counter 021 with a preset counting threshold, and generate the state detection signal according to the comparison result. Specifically, when the counting result is greater than the counting threshold, the working state of the phase-locked loop is determined to be an out-of-lock state; and when the counting result is not greater than the counting threshold value, determining that the working state of the phase-locked loop is a locking state.
It should be noted that, in practical applications, the counter 021 may be provided with an input for receiving a counting period, the comparator 022 may also be provided with an input for receiving a counting threshold and a counting period, and the comparator 022 may compare a counting result received in the counting period with a preset counting threshold.
In an alternative implementation manner of the present invention, assuming that the phase-locked loop is in the first operation mode (i.e. the phase of the reference signal lags behind the phase of the feedback signal), the operation mode signal output by the controller is at the high level, and when the phase-locked loop is in the second operation mode (i.e. the phase of the feedback signal lags behind the phase of the reference signal), the operation mode signal is at the low level, referring to fig. 4A, the clock signal terminal CK of the D flip-flop 011 receives the reference signal, the data signal terminal D receives the feedback signal, and the logic gate 012 is an xor gate, for example, to describe the operation principle of the lock detection circuit in detail. Since the clock signal terminal CK of the D flip-flop 011 receives a reference signal, the D flip-flop 011 can sample the feedback signal inputted from the data signal terminal D with the reference signal as a sampling clock signal, that is, output the level of the feedback signal to the first input terminal of the logic gate 012 at the rising edge of the reference signal.
Fig. 4B and fig. 4C are timing diagrams of a reference signal and a feedback signal of a phase locked loop in different operation modes according to an embodiment of the present invention. Wherein fig. 4B is a timing diagram of the reference signal and the feedback signal when the pll is in the first operating mode (i.e., the phase of the reference signal lags the phase of the feedback signal), and assuming that the reference signal and the feedback signal are valid at a high level, it can be seen from fig. 4B that when the phase of the reference signal lags the phase of the feedback signal, if the phase relationship between the reference signal and the feedback signal is stable (i.e., when the pll is in a locked state), the D flip-flop 011 samples the feedback signal at a rising edge of the reference signal, and the obtained sampling signal is at a high level (i.e., the level at point a in fig. 4B), and then the D flip-flop outputs 1; if the phase relationship between the reference signal and the feedback signal is unstable (i.e. when the pll is in an out-of-lock state), the sampling signal of the feedback signal output by the D flip-flop 011 may be 1 or may further include 0.
Fig. 4C is a timing diagram of the reference signal and the feedback signal when the phase of the phase-locked loop is in the second operation mode (i.e. the phase of the feedback signal lags behind the phase of the reference signal), and it can be seen from fig. 4C that when the phase of the feedback signal lags behind the phase of the reference signal, if the phase relationship between the reference signal and the feedback signal is stable, the D flip-flop 011 samples the feedback signal at the rising edge of the reference signal, and the sampled signal is at a low level (i.e. the level at point B in fig. 4C), i.e. the D flip-flop outputs 0; if the phase relationship between the reference signal and the feedback signal is unstable, the sampling signal of the feedback signal output by the D flip-flop may be 0, and may also include 1.
The working principle of the exclusive or gate is shown in table 1, that is, when the input levels of the two input ends are different, the output is 1, and when the input levels of the two input ends are the same, the output is 0.
TABLE 1
| A first input terminal | Second input terminal | Output end |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Therefore, when the phase-locked loop is in the first operating mode, if the phase relationship between the reference signal and the feedback signal is stable, the signal output by the D flip-flop 011 to the first input terminal of the xor gate 012 should be 1, and since the operating mode signal input by the second input terminal of the xor gate 012 is 1 at this time, the comparison signals output by the output terminal of the xor gate 012 should all be 0; if the phase relationship between the reference signal and the feedback signal is unstable, the signal output by the D flip-flop 011 to the first input terminal of the xor gate 012 is also unstable, that is, the signal output by the D flip-flop 011 to the first input terminal of the logic gate 012 may be 1 or 0 at this time, and therefore the comparison signal output by the xor gate 012 is 1 or 0 at this time.
When the operating mode of the phase-locked loop in an ideal locking state is the second operating mode, that is, the phase of the feedback signal lags behind the phase of the reference signal, if the phase relationship between the reference signal and the feedback signal is stable, the signal output by the D flip-flop 011 to the first input end of the xor gate 012 should be 0, and since the operating mode signal input by the second input end of the xor gate 012 is 0 at this time, the comparison signal output by the output end of the xor gate 012 should also be 0; if the phase relationship between the reference signal and the feedback signal is unstable, the xor gate 012 outputs a contrast signal of 1 or 0.
As can be seen from the above analysis, when the operation mode signal indicates that the operation mode of the pll under the ideal locking state is the first operation mode at a high level, and the operation mode signal indicates that the operation mode of the pll under the ideal locking state is the second operation mode at a low level, the clock signal terminal CK of the D flip-flop receives the reference signal, and the logic gate 012 is an xor gate, when the pll is in the locking state, the comparison signals output by the xor gate 012 should be all 0, and when the pll is in the out-of-lock state, the comparison signals output by the xor gate 012 may be 1 or 0. Therefore, after the counter 021 receives the contrast signal, the counted preset level in the contrast signal may be a high level, that is, the counter 021 may count the high level of the contrast signal in a preset counting period with the reference signal as a clock signal, for example, if the counting period is 1s and the period of the reference signal is 0.1s, the counter 021 may sample 10 level signals and count the high level in the 10 level signals in the counting period, and if the counter 021 counts that the 10 level signals include 5 high levels in the counting period 1s, the counter 021 may send a counting result 5 to the comparator 022. If the preset count threshold value in the comparator 022 is 3, when the comparator 022 receives the count result 5, it may be determined that the count result 5 is greater than the count threshold value 3, and then it may be determined that the phase relationship between the reference signal and the feedback signal in the phase-locked loop is unstable, and it is determined that the phase-locked loop is in an out-of-lock state.
In the embodiment of the present invention, when the phase-locked loop is in the first operating mode, the operating mode signal may be at a low level, and correspondingly, when the phase-locked loop is in the second operating mode, the operating mode signal is at a high level, and the clock signal terminal in the D flip-flop is connected to the reference signal or the feedback signal, and the logic operation performed by the logic gate on the sampling signal and the operating mode signal may be an exclusive-or operation or an exclusive-or operation. Therefore, the preset level counted by the counter can be set according to the level of the working mode signal in different working modes, the signal type accessed by the clock signal end in the D flip-flop, and the type of the logic gate (i.e., the type of logic operation).
As shown in table 2, on one hand, when the working mode signal indicates that the working mode of the pll under the ideal locking state is the first working mode with a high level and the working mode signal indicates that the working mode of the pll under the ideal locking state is the second working mode with a low level, the preset level is the high level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as the sampling clock signal and the comparison signal is generated by the logic gate through the xor operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a low level.
On the other hand, when the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the first working mode with a low level and the working mode signal indicates that the working mode of the phase-locked loop in the ideal locking state is the second working mode with a high level, the preset level is a low level when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal and the comparison signal is generated by the logic gate through an exclusive or operation; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or, when the sampling signal is obtained by sampling the D flip-flop with the reference signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or, when the sampling signal is obtained by sampling the D flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a high level.
TABLE 2
It should be noted that, in the above embodiments of the present invention, the active levels of the reference signal and the feedback signal are taken as high levels, and in practical applications, the active levels of the reference signal and the feedback signal may also be taken as low levels, and the preset levels shown in table 2 are also adjusted accordingly.
It should be further noted that, in practical applications, phase-locked loops having a fixed phase difference between a reference signal and a feedback signal may all use the lock detection circuit provided in the embodiment of the present invention to detect the operating state in the phase-locked loop, and an application scenario of the lock detection circuit in the embodiment of the present invention is not limited. Furthermore, all of the above alternative implementations may be combined arbitrarily to form alternative embodiments of the invention.
In summary, an embodiment of the present invention provides a lock detection circuit, which includes a phase comparison circuit and a state detection circuit, wherein the phase comparison circuit can generate a comparison signal indicating a phase relationship between a reference signal and the feedback signal according to an operating mode signal, and the state detection circuit can detect an operating state of the phase-locked loop according to the reference signal and the comparison signal. The locking detection circuit provided by the embodiment of the invention consists of a D trigger, a logic gate, a counter and a comparator, and the locking detection circuit has fewer elements and simpler circuit structure.
Fig. 5 is a flowchart of a lock detection method according to an embodiment of the present invention, which may be applied to the lock detection circuit shown in fig. 3 or fig. 4A, and as can be seen from fig. 3 or fig. 4A, the lock detection circuit includes: a phase comparison circuit 01 and a state detection circuit 02 coupled to the phase comparison circuit, the lock detection circuit being coupled to a reference signal input and a feedback signal input of a phase locked loop, respectively, and to a controller, as shown in fig. 5, the method may include:
step 501, receiving a reference signal from a reference signal input end of a phase-locked loop, a feedback signal from a feedback signal input end of the phase-locked loop, and a working mode signal from a controller, respectively.
Wherein the operating mode signal indicates an operating mode of the phase locked loop in an ideal locking state, the operating mode including a first operating mode in which the phase of the reference signal lags the phase of the feedback signal and a second operating mode in which the phase of the feedback signal lags the phase of the reference signal.
Step 502, generating a contrast signal according to the reference signal, the feedback signal and the working mode signal.
The comparison signal indicates whether the phase relationship of the phase-locked loop in the actual operating state is the same as the phase relationship of the phase-locked loop in the ideal locking state, wherein the phase relationship of the phase-locked loop in the actual operating state is the phase relationship of the reference signal and the feedback signal.
Step 503, acquiring a clock signal and the comparison signal, and detecting a working state of the phase-locked loop according to the clock signal and the comparison signal, where the working state includes a locked state or an unlocked state.
The method shown in steps 501 and 502 can be implemented by the phase comparison circuit 01 in the lock detection circuit, and the method shown in step 503 can be implemented by the state detection circuit 02 in the lock detection circuit. For the specific implementation process of the lock detection method shown in steps 501 to 503, reference may be made to the foregoing description on the working principle of the lock detection circuit, and details of the embodiment of the present invention are not repeated.
An embodiment of the present invention further provides a phase-locked circuit, and referring to fig. 2, the phase-locked circuit may include: a phase locked loop 10, a controller 20 and a lock detection circuit 00 as described in the first aspect, the lock detection circuit 00 being coupled to a reference signal input a and a feedback signal input b of the phase locked loop 10 and the controller 20, respectively.
The phase locked loop 10 is configured to send a reference signal to the lock detection circuit through the reference signal input terminal a, and send a feedback signal to the lock detection circuit through the feedback signal input terminal b.
The controller 20 is configured to control an operation mode of the phase locked loop 10 and send an operation mode signal to the lock detection circuit 00, the operation mode signal indicating an operation mode of the phase locked loop 10 in an ideal lock state, the operation mode including a first operation mode in which the phase of the reference signal lags the phase of the feedback signal and a second operation mode in which the phase of the feedback signal lags the phase of the reference signal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (19)
1. A lock detection circuit, wherein the lock detection circuit is coupled to a reference signal input and a feedback signal input of a phase locked loop, respectively, and a controller, the lock detection circuit comprising: a phase comparison circuit and a state detection circuit coupled to the phase comparison circuit;
the phase comparison circuit is configured to receive a reference signal from a reference signal input of the phase-locked loop, a feedback signal from a feedback signal input of the phase-locked loop, and an operation mode signal from the controller, respectively, wherein the operation mode signal indicates an operation mode of the phase-locked loop in an ideal locking state, and the operation mode includes a first operation mode in which a phase of the reference signal lags a phase of the feedback signal and a second operation mode in which the phase of the feedback signal lags the phase of the reference signal;
the phase comparison circuit is further configured to generate a comparison signal according to the reference signal, the feedback signal and the operating mode signal, where the comparison signal indicates whether a phase relationship of the phase-locked loop in an actual operating state is the same as a phase relationship of the phase-locked loop in an ideal locking state, where the phase relationship of the phase-locked loop in the actual operating state is the phase relationship of the reference signal and the feedback signal;
the state detection circuit is used for acquiring a clock signal and the comparison signal and detecting the working state of the phase-locked loop according to the clock signal and the comparison signal, wherein the working state comprises a locking state or an unlocking state.
2. The lock detection circuit according to claim 1, wherein the phase comparison circuit comprises: data flip-flops and logic gates;
the clock signal input end of the data trigger is used for receiving the reference signal, the data signal input end of the data trigger is used for receiving the feedback signal, the output end of the data trigger is connected with the first input end of the logic gate, and the data trigger is used for sampling the level of the feedback signal by taking the reference signal as a sampling clock signal to obtain a sampling signal;
the logic gate is used for receiving the sampling signal through the first input end, receiving the working mode signal through the second input end of the logic gate, and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
3. The lock detection circuit according to claim 1, wherein the phase comparison circuit comprises: data flip-flops and logic gates;
the clock signal input end of the data trigger is used for receiving the feedback signal, the data signal input end of the data trigger is used for receiving the reference signal, the output end of the data trigger is connected with the first input end of the logic gate, and the data trigger is used for sampling the level of the reference signal by taking the feedback signal as a sampling clock signal to obtain a sampling signal;
the logic gate is used for receiving the sampling signal through the first input end, receiving the working mode signal through the second input end of the logic gate, and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
4. The lock detection circuit according to claim 2 or 3,
the logical operation is one of an exclusive-or operation or an exclusive-or operation.
5. The lock detection circuit according to claim 4, wherein the state detection circuit comprises: a counter and a comparator;
the input end of the counter is used for receiving the comparison signal, the clock signal end of the counter is used for receiving the clock signal, the output end of the counter is connected with the input end of the comparator, and the counter is used for counting a preset level in the comparison signal within a preset counting period according to the clock signal to obtain a counting result and sending the counting result to the comparator;
and the comparator is used for comparing the counting result with a preset counting threshold value and detecting the working state of the phase-locked loop according to the comparison result.
6. The lock detection circuit of claim 5,
in case the operation mode signal indicates with a high level that the operation mode of the phase locked loop in the ideal locking state is the first operation mode and the operation mode signal indicates with a low level that the operation mode of the phase locked loop in the ideal locking state is the second operation mode,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data trigger and the comparison signal is generated by the logic gate through an exclusive-or operation, the preset level is a high level; or,
when the sampling signal is obtained by sampling the data trigger by taking the feedback signal as a sampling clock signal and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data flip-flop and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or,
and when the sampling signal is obtained by sampling the data trigger by taking the feedback signal as a sampling clock signal and the comparison signal is generated by the logic gate through an exclusive-or operation, the preset level is a low level.
7. The lock detection circuit of claim 5,
in case the operation mode signal indicates with a low level that the operation mode of the phase locked loop in the ideal locking state is the first operation mode and the operation mode signal indicates with a high level that the operation mode of the phase locked loop in the ideal locking state is the second operation mode,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data trigger and the comparison signal is generated by the logic gate through an exclusive-or operation, the preset level is a low level; or,
when the sampling signal is obtained by sampling the data trigger by taking the feedback signal as a sampling clock signal and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level; or,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data flip-flop and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level; or,
and when the sampling signal is obtained by sampling the data trigger by taking the feedback signal as a sampling clock signal and the comparison signal is generated by the logic gate through XOR operation, the preset level is a high level.
8. The lock-in detection circuit according to any of claims 5 to 7, wherein the comparator is specifically configured to:
comparing the counting result with a preset counting threshold, and determining that the working state of the phase-locked loop is in an out-of-lock state when the counting result is greater than the counting threshold;
and when the counting result is not greater than the counting threshold, determining that the working state of the phase-locked loop is a locking state.
9. The lock detection circuit according to any one of claims 1 to 8, wherein the clock signal obtained by the state detection circuit is the reference signal;
alternatively, the lock detection circuit further includes: a clock generator, the state detection circuit further to obtain the clock signal from the clock generator.
10. A lock detection method applied to a lock detection circuit, the lock detection circuit comprising: a phase comparison circuit and a state detection circuit coupled to the phase comparison circuit, the lock detection circuit being coupled to a reference signal input and a feedback signal input of a phase locked loop, respectively, and to a controller, the method comprising:
receiving a reference signal from a reference signal input of the phase locked loop, a feedback signal from a feedback signal input of the phase locked loop, and an operating mode signal from the controller, respectively, wherein the operating mode signal indicates an operating mode of the phase locked loop in an ideal locked state, the operating mode including a first operating mode in which a phase of the reference signal lags a phase of the feedback signal and a second operating mode in which the phase of the feedback signal lags the phase of the reference signal;
generating a comparison signal according to the reference signal, the feedback signal and the working mode signal, wherein the comparison signal indicates whether the phase relationship of the phase-locked loop in the actual working state is the same as the phase relationship of the phase-locked loop in the ideal locking state, and the phase relationship of the phase-locked loop in the actual working state is the phase relationship of the reference signal and the feedback signal;
acquiring a clock signal and the comparison signal, and detecting the working state of the phase-locked loop according to the clock signal and the comparison signal, wherein the working state comprises a locking state or an unlocking state.
11. The method of claim 10, wherein generating a contrast signal based on the reference signal, the feedback signal, and the operating mode signal comprises:
taking the reference signal as a sampling clock signal, and sampling the level of the feedback signal to obtain a sampling signal;
and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
12. The method of claim 10, wherein generating a contrast signal based on the reference signal, the feedback signal, and the operating mode signal comprises:
taking the feedback signal as a sampling clock signal, and sampling the level of the reference signal to obtain a sampling signal;
and carrying out logic operation according to the sampling signal and the working mode signal to generate the comparison signal.
13. The method of claim 11 or 12, wherein the logical operation is one of an exclusive or operation or an exclusive or operation.
14. The method of claim 13, wherein detecting the operating state of the phase locked loop based on the clock signal and the comparison signal comprises:
counting the preset level of the comparison signal within a preset counting period according to the clock signal to obtain a counting result;
and comparing the counting result with a preset counting threshold value, and detecting the working state of the phase-locked loop according to the comparison result.
15. The method of claim 14,
in case the operation mode signal indicates with a high level that the operation mode of the phase locked loop in the ideal locking state is the first operation mode and the operation mode signal indicates with a low level that the operation mode of the phase locked loop in the ideal locking state is the second operation mode,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data trigger and the comparison signal is generated by the logic gate through an exclusive-or operation, the preset level is a high level;
or, when the sampling signal is obtained by sampling the data flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level;
or, when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data flip-flop and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level;
or, when the sampling signal is obtained by sampling the data flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a low level.
16. The method of claim 14,
in case the operation mode signal indicates with a low level that the operation mode of the phase locked loop in the ideal locking state is the first operation mode and the operation mode signal indicates with a high level that the operation mode of the phase locked loop in the ideal locking state is the second operation mode,
when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data trigger and the comparison signal is generated by the logic gate through an exclusive-or operation, the preset level is a low level;
or, when the sampling signal is obtained by sampling the data flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a low level;
or, when the sampling signal is obtained by sampling the reference signal as a sampling clock signal by the data flip-flop and the comparison signal is generated by the logic gate through an exclusive nor operation, the preset level is a high level;
or, when the sampling signal is obtained by sampling the data flip-flop with the feedback signal as a sampling clock signal, and the comparison signal is generated by the logic gate through an exclusive or operation, the preset level is a high level.
17. The method according to any one of claims 14 to 16, wherein comparing the counting result with a preset counting threshold and detecting the operating state of the phase-locked loop according to the comparison result comprises:
comparing the counting result with a preset counting threshold, and determining that the working state of the phase-locked loop is in an out-of-lock state when the counting result is greater than the counting threshold;
and when the counting result is not greater than the counting threshold, determining that the working state of the phase-locked loop is a locking state.
18. The method of any of claims 10 to 17, wherein the clock signal is the reference signal; alternatively, the clock signal is a signal generated by a clock generator.
19. A phase-locked circuit, comprising: a phase locked loop, a controller and a lock detection circuit as claimed in any one of claims 1 to 9, the lock detection circuit being coupled to a reference signal input and a feedback signal input of the phase locked loop, respectively, and to the controller;
the phase-locked loop is used for sending a reference signal to the locking detection circuit through the reference signal input end and sending a feedback signal to the locking detection circuit through the feedback signal input end;
the controller is configured to send an operating mode signal to the lock detection circuit, the operating mode signal indicating an operating mode of the phase-locked loop in an ideal lock state, the operating mode including a first operating mode in which the phase of the reference signal lags the phase of the feedback signal and a second operating mode in which the phase of the feedback signal lags the phase of the reference signal.
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| CN114201440B (en) * | 2021-12-14 | 2024-06-07 | 上海微阱电子科技有限公司 | Clock detection method, circuit, serial port communication system, medium and equipment |
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