CN106357266A - Locked detecting circuit, method and phase-locked circuit - Google Patents
Locked detecting circuit, method and phase-locked circuit Download PDFInfo
- Publication number
- CN106357266A CN106357266A CN201610737928.7A CN201610737928A CN106357266A CN 106357266 A CN106357266 A CN 106357266A CN 201610737928 A CN201610737928 A CN 201610737928A CN 106357266 A CN106357266 A CN 106357266A
- Authority
- CN
- China
- Prior art keywords
- signal
- mode
- sampled
- lock
- phaselocked loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
Abstract
The invention discloses a locked detecting circuit, a method and a phase-locked circuit. The locked detecting circuit is respectively connected with a reference signal input terminal and a feedback signal input terminal of a phase-locked loop, and a controller. The locked detecting circuit comprises a phase comparison circuit and a state detection circuit. The phase comparison circuit is used for receiving reference signals from a reference signal input terminal of the phase-locked loop, receiving feedback signals from a feedback signal input terminal of the phase-locked loop, and receiving operation mode signals from the controller. Besides, phase comparison circuit is also able to generate comparison signals based on the reference signals, the feedback signals, and the operation mode signals. The state detection circuit is used for acquiring clock signals and comparing the clock signals, detecting the operation status of the phase-locked loop. The locked detecting circuit has a simple structure.
Description
Technical field
The present invention relates to communication technical field, particularly to a kind of lock detecting circuit, method and phase lock circuitry.
Background technology
Phaselocked loop be a kind of under normal operating conditions (i.e. lock-out state), feedback signal and the input of output can be made
Reference signal keeps the closed control circuit of identical frequency and constant phase contrast, is generally used for broadcast, communication, frequency
The technical field such as synthesis and clock synchronization.Traditional phaselocked loop is typically by phase frequency detector, charge pump, loop filter, pressure
Controlled oscillator and frequency divider composition.Should due to when phaselocked loop is in abnormal operating state (i.e. out-of-lock condition), being easily caused
With the system malfunctions of this phaselocked loop it is therefore desirable to special lock detecting circuit determines the working condition of phaselocked loop, with
Just in time the phaselocked loop being in out-of-lock condition is detected and keeped in repair.
The device that lock detecting circuit in correlation technique is comprised is more, generally comprises two frequency dividers, two countings
Device and a comparator, the structure of this lock detecting circuit is complex.
Content of the invention
For the problem in correlation technique, the invention provides a kind of lock-in detection electricity simplifying lock detecting circuit structure
Road, method and phase lock circuitry.Described technical scheme is as follows:
On the one hand, there is provided a kind of lock detecting circuit, this lock detecting circuit is respectively with the reference signal of phaselocked loop is defeated
Enter end and feedback signal input terminal, and controller be coupled, this lock detecting circuit includes: phase-comparison circuit and with this
The state detection circuit that phase-comparison circuit is coupled；This phase-comparison circuit is used for defeated from the reference signal of this phaselocked loop respectively
Enter end and receive reference signal, receive feedback signal from the feedback signal input terminal of this phaselocked loop, and receive work from this controller
Operation mode signal, wherein, this mode of operation signal designation mode of operation under preferable lock-out state for this phaselocked loop, this work
Pattern includes the first mode of operation and the second mode of operation, and under this first mode of operation, the phase place of this reference signal lags behind
The phase place of this feedback signal, in this second mode of operation, the phase place of this feedback signal lags behind the phase place of this reference signal；Should
Phase-comparison circuit is additionally operable to, according to this reference signal, this feedback signal and this mode of operation signal, generate contrast signal, should
Contrast signal is indicated phase relation under actual working state for this phaselocked loop and is closed with the phase place under this preferable lock-out state
Whether system is identical, wherein, the phase of phase relation under actual working state for the phaselocked loop i.e. this reference signal and this feedback signal
Position relation；This state detection circuit is used for obtaining clock signal and this contrast signal, and is believed according to this clock signal and this contrast
Number, the working condition of this phaselocked loop is detected, this working condition includes lock-out state or out-of-lock condition.The present invention provides
Lock detecting circuit passes through phase-comparison circuit and state detection circuit can achieve the detection of the working condition to phaselocked loop, should
Element included in lock detecting circuit is less, and circuit structure is relatively simple.
Optionally, this phase-comparison circuit may include that data trigger (English: data flip-flop；Referred to as: d touches
Send out device) and gate；The clock signal input terminal of this d trigger is used for receiving this reference signal, the data signal of this d trigger
Input is used for receiving this feedback signal, and the outfan of this d trigger is connected with the first input end of this gate, and this d triggers
Device is used for this reference signal as sampled clock signal, carries out sampling to the level of this feedback signal and obtains sampled signal；This is patrolled
Collect door to be used for receiving this sampled signal by first input end, and this mode of operation signal is received by the second input, and
Logical operationss are carried out according to this sampled signal and this mode of operation signal, generates this contrast signal.
Optionally, this phase-comparison circuit may include that d trigger and gate；The clock signal input of this d trigger
Hold for receiving this feedback signal, the data signal input of this d trigger is used for receiving this reference signal, this d trigger
Outfan is connected with the first input end of this gate, and this d trigger is used for this feedback signal as sampled clock signal, to this
The level of reference signal carries out the sampled signal obtaining of sampling；This gate is used for receiving this sampling letter by first input end
Number, and this mode of operation signal is received by the second input, this gate is used for according to this sampled signal and this mode of operation
Signal carries out logical operationss, generates this contrast signal.
Optionally, this logical operations be XOR with or one of computing.
Optionally, this state detection circuit may include that enumerator and comparator；The input of this enumerator is used for receiving
This contrast signal, the clock signal terminal of this enumerator is used for receiving this clock signal, the outfan of this enumerator and this comparator
Input connect, this enumerator be used for according to this clock signal, to pre- in this contrast signal within the default counting cycle
If level carries out counting to get count results, and count results are sent to this comparator；This comparator is used for tying this counting
Fruit is compared with default count threshold, and according to comparative result, the working condition of this phaselocked loop is detected.
Optionally, indicate mode of operation under preferable lock-out state for this phaselocked loop with high level in this mode of operation signal
For the first mode of operation, and this mode of operation signal indicates Working mould under preferable lock-out state for this phaselocked loop with low level
In the case that formula is the second mode of operation, when this sampled signal is to be believed as sampling clock using this reference signal by this d trigger
Number carrying out sampling obtains, and when this contrast signal is to be generated by XOR by this gate, this predetermined level is high level；
Or, when this sampled signal is to carry out sampling using this feedback signal as sampled clock signal by this d trigger to obtain, and this is right
Than signal be by this gate pass through with or computing generate when, this predetermined level be high level；Or, when this sampled signal be by
This d trigger carries out sampling using this reference signal as sampled clock signal and obtains, and this contrast signal is to be led to by this gate
Cross with or computing generate when, this predetermined level be low level；Or, when this sampled signal is with this feedback letter by this d trigger
Number carrying out sampling as sampled clock signal obtains, and when this contrast signal is to be generated by XOR by this gate, should
Predetermined level is low level.
Optionally, indicate mode of operation under preferable lock-out state for this phaselocked loop with low level in this mode of operation signal
For the first mode of operation, and this mode of operation signal indicates Working mould under preferable lock-out state for this phaselocked loop with high level
In the case that formula is the second mode of operation, when this sampled signal is to be believed as sampling clock using this reference signal by this d trigger
Number carrying out sampling obtains, and when this contrast signal is to be generated by XOR by this gate, this predetermined level is low level；
Or, when this sampled signal is to carry out sampling using this feedback signal as sampled clock signal by this d trigger to obtain, and this is right
Than signal be by this gate pass through with or computing generate when, this predetermined level be low level；Or, when this sampled signal be by
This d trigger carries out sampling using this reference signal as sampled clock signal and obtains, and this contrast signal is to be led to by this gate
Cross with or computing generate when, this predetermined level be high level；Or, when this sampled signal is with this feedback letter by this d trigger
Number carrying out sampling as sampled clock signal obtains, and when this contrast signal is to be generated by XOR by this gate, should
Predetermined level is high level.
Optionally, this comparator specifically for: this count results is compared with default count threshold, when this counting
When result is more than this count threshold, determine that the working condition of this phaselocked loop is out-of-lock condition；When this count results is not more than this meter
During number threshold value, determine that the working condition of this phaselocked loop is lock-out state.
Optionally, this clock signal that this state detection circuit obtains can be this reference signal；Or, this lock-in detection
Circuit can also include: clock generator, then this state detection circuit can also obtain this clock signal from this clock generator.
Second aspect, provides a kind of lock detecting method, is applied to lock detecting circuit, and this lock detecting circuit includes:
Phase-comparison circuit and the state detection circuit being coupled with this phase-comparison circuit, this lock detecting circuit respectively with, lock
The reference signal input of phase ring and feedback signal input terminal, and controller is coupled, the method includes: respectively from this lock phase
The reference signal input of ring receives reference signal, receives feedback signal, Yi Jicong from the feedback signal input terminal of this phaselocked loop
This controller receives mode of operation signal, and wherein, this phaselocked loop of this mode of operation signal designation is under the preferable lock-out state
Mode of operation, this mode of operation includes the first mode of operation and the second mode of operation, and under this first mode of operation, this reference is believed
Number phase place lag behind the phase place of this feedback signal, in this second mode of operation, the phase place of this feedback signal lags behind this ginseng
Examine the phase place of signal；According to this reference signal, this feedback signal and this mode of operation signal, generate contrast signal, this contrast
Signal designation phase relation under actual working state for this phaselocked loop and the phase relation stated at this under preferable lock-out state
Whether identical, wherein, the phase of phase relation under actual working state for this phaselocked loop i.e. this reference signal and this feedback signal
Position relation；Obtain clock signal and contrast signal, and according to this clock signal and the work shape to this phaselocked loop for this contrast signal
State is detected, this working condition includes lock-out state or out-of-lock condition.The lock detecting method that the present invention provides can be from control
Device processed receives mode of operation signal, and detects, this detected based on this mode of operation signal to the working condition of phaselocked loop
Journey is relatively simple, and detection efficiency is higher.
Optionally, according to this reference signal, this feedback signal and this mode of operation signal, generate the concrete of contrast signal
Process may include that this reference signal as sampled clock signal, the level of this feedback signal is sampled, is sampled
Signal；Logical operationss are carried out according to this sampled signal and this mode of operation signal, generates this contrast signal.
Optionally, according to this reference signal, this feedback signal and this mode of operation signal, generate contrast signal and obtain specifically
Process can also include: using this feedback signal as sampled clock signal, the level of this reference signal is sampled, is adopted
Sample signal；Logical operationss are carried out according to this sampled signal and this mode of operation signal, generates this contrast signal.
Optionally, this logical operations can for XOR with or one of computing.
Optionally, concrete according to the process working condition of phaselocked loop being detected according to clock signal and contrast signal
May include that according to this clock signal, within the default counting cycle, the predetermined level of this contrast signal is counted to get
Count results；This count results is compared with default count threshold, and according to comparative result, the work to this phaselocked loop
State is detected.
Optionally, indicate mode of operation under preferable lock-out state for this phaselocked loop with high level in this mode of operation signal
For the first mode of operation, and this mode of operation signal indicates Working mould under preferable lock-out state for this phaselocked loop with low level
In the case that formula is the second mode of operation, when this sampled signal is to be believed as sampling clock using this reference signal by this d trigger
Number carrying out sampling obtains, and when this contrast signal is to be generated by XOR by this gate, this predetermined level is high level；
Or, when this sampled signal is to carry out sampling using this feedback signal as sampled clock signal by this d trigger to obtain, and this is right
Than signal be by this gate pass through with or computing generate when, this predetermined level be high level；Or, when this sampled signal be by
This d trigger carries out sampling using this reference signal as sampled clock signal and obtains, and this contrast signal is to be led to by this gate
Cross with or computing generate when, this predetermined level be low level；Or, when this sampled signal is with this feedback letter by this d trigger
Number carrying out sampling as sampled clock signal obtains, and when this contrast signal is to be generated by XOR by this gate, should
Predetermined level is low level.
Optionally, indicate mode of operation under preferable lock-out state for this phaselocked loop with low level in this mode of operation signal
For the first mode of operation, and this mode of operation signal indicates Working mould under preferable lock-out state for this phaselocked loop with high level
In the case that formula is the second mode of operation, when this sampled signal is to be believed as sampling clock using this reference signal by this d trigger
Number carrying out sampling obtains, and when this contrast signal is to be generated by XOR by this gate, this predetermined level is low level；
Or, when this sampled signal is to carry out sampling using this feedback signal as sampled clock signal by this d trigger to obtain, and this is right
Than signal be by this gate pass through with or computing generate when, this predetermined level be low level；Or, when this sampled signal be by
This d trigger carries out sampling using this reference signal as sampled clock signal and obtains, and this contrast signal is to be led to by this gate
Cross with or computing generate when, this predetermined level be high level；Or, when this sampled signal is with this feedback letter by this d trigger
Number carrying out sampling as sampled clock signal obtains, and when this contrast signal is to be generated by XOR by this gate, should
Predetermined level is high level.
Optionally, this count results is compared by this with default count threshold, and according to comparative result, to this lock phase
The working condition of ring is detected, comprising: be compared this count results with default count threshold, when this count results is big
When this count threshold, determine that the working condition of this phaselocked loop is out-of-lock condition；When this count results is not more than this count threshold
When, determine that the working condition of this phaselocked loop is lock-out state.
Optionally, this clock signal can be this reference signal；Or, this clock signal can generate for clock generator
Signal.
A kind of third aspect, there is provided phase lock circuitry, this phase lock circuitry includes: phaselocked loop, controller and as first party
Lock detecting circuit described in face, this lock detecting circuit is respectively with the reference signal input of phaselocked loop is defeated with feedback signal
Enter end, and controller is coupled；This phaselocked loop is used for sending ginseng by this reference signal input to this lock detecting circuit
Examine signal, and feedback signal is sent to this lock detecting circuit by this feedback signal input terminal；This controller is used for this lock
Regular inspection slowdown monitoring circuit sends mode of operation signal, the work under preferable lock-out state for this phaselocked loop of this mode of operation signal designation
Pattern, this mode of operation includes the first mode of operation and the second mode of operation, in the first operation mode, the phase of this reference signal
After the phase place of this feedback signal, in this second mode of operation, the phase place of this feedback signal lags behind this reference signal to steric retardation
Phase place.
In sum, the technical scheme that the present invention provides has the benefit that
The invention provides a kind of lock detecting circuit, method and phase lock circuitry, this lock detecting circuit includes phase place ratio
Compared with circuit and state detection circuit, wherein phase-comparison circuit can generate for instruction with reference to letter according to mode of operation signal
The contrast signal of the phase relation number and this feedback signal between, state detection circuit can be believed according to reference signal and this contrast
Number, generate state detection signal.In the lock detecting circuit providing compared to the lock detecting circuit in correlation technique, the present invention
Only comprise a trigger, a gate, an enumerator and a comparator, the element that this lock detecting circuit is comprised
Less, circuit structure is relatively simple.
Brief description
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, will make to required in embodiment description below
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 a is a kind of structural representation of phaselocked loop provided in an embodiment of the present invention；
Fig. 1 b is a kind of partial structural diagram of phaselocked loop provided in an embodiment of the present invention；
Fig. 1 c is the structural representation of another kind phaselocked loop provided in an embodiment of the present invention；
Fig. 2 is a kind of application scenarios schematic diagram of lock detecting circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation of lock detecting circuit provided in an embodiment of the present invention；
Fig. 4 a is the structural representation of another kind lock detecting circuit provided in an embodiment of the present invention；
Fig. 4 b is the sequential relationship schematic diagram of a kind of reference signal provided in an embodiment of the present invention and feedback signal；
Fig. 4 c is the sequential relationship schematic diagram of another kind reference signal provided in an embodiment of the present invention and feedback signal；
Fig. 5 is a kind of flow chart of lock detecting method provided in an embodiment of the present invention.
Specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 a is a kind of structural representation of phaselocked loop provided in an embodiment of the present invention, and as shown in Figure 1a, this phaselocked loop can
To include crystal oscillator buffer 101, phase frequency detector 102, charge pump 103, low pass filter 104, voltage-controlled vibrator 105 and frequency dividing
Device 106.Wherein, this crystal oscillator buffer 101 is used for the crystal oscillation signal of crystal oscillator input input is entered and generates with reference to letter after row buffering
Number, and this reference signal is exported to phase frequency detector 102, this phase frequency detector 102 is used for detecting this reference signal and feedback
The phase contrast of signal, and pulse control signal is exported to charge pump 103 according to this phase contrast, this charge pump 103 is used for basis should
Pulse control signal produces charging current or discharge current, and low pass filter 104 is used for according to this charging current or electric discharge electricity
Flow to voltage controlled oscillator 105 output control voltage, voltage controlled oscillator 105 can generate oscillating voltage according to this control voltage, with
Just generate feedback signal after frequency divider 106 divides to this oscillating voltage, and input to this phase frequency detector 102.From Fig. 1 a
In as can be seen that phase frequency detector in this phaselocked loop, charge pump, low pass filter, voltage controlled oscillator and frequency divider can be with shapes
Become a feedback system, this feedback system can adjust the feedback frequency of signal and phase place so that the frequency of this feedback signal and
Phase place is " locked " in the frequency and phase place of this reference signal.That is to say, when this phaselocked loop is in the lock state, this reference is believed
Number with the frequency of this feedback signal and phase place all same, or both frequencies are identical, constant phase difference.
Fig. 1 b is a kind of partial structural diagram of phaselocked loop provided in an embodiment of the present invention, as shown in Figure 1 b, in order to keep away
The non-linear working condition to phaselocked loop exempting from charge pump 103 in phaselocked loop impacts, typically can also be in charge pump 103
Outfan increases compensation electric current (ioffset) 31 improving the non-linear of this charge pump 103, this increase compensates the phaselocked loop of electric current
Referred to as offset cp phaselocked loop.When this offset cp phaselocked loop is in the lock state, have between reference signal and feedback signal
There is certain phase contrast.Fig. 1 c is the structural representation of another kind phaselocked loop provided in an embodiment of the present invention, as illustrated in figure 1 c, should
Phaselocked loop includes crystal oscillator buffer 21, phase discriminator 22, low pass filter 23, voltage controlled oscillator 24 and frequency divider 25, this lock phase
It is not provided with charge pump, the phaselocked loop of the type is also referred to as type-i phaselocked loop, when this type-i phaselocked loop is in locking shape in ring
During state, between reference signal and feedback signal, also there is fixing phase contrast.During for above-mentioned being in the lock state, reference signal
There is and feedback signal between the phaselocked loop of fixed skew, two kinds of mode of operations can be included: under the first mode of operation, reference
The phase place of signal lags behind the phase place of feedback signal, and in the second operation mode, the phase place of feedback signal lags behind reference signal
Phase place.
Fig. 2 is a kind of application scenarios schematic diagram of lock detecting circuit provided in an embodiment of the present invention, with reference to Fig. 2, this lock
Regular inspection slowdown monitoring circuit 00 can respectively with phaselocked loop 10 reference signal input a and feedback signal input terminal b, and controller 20
It is coupled.Fig. 3 is a kind of structural representation of lock detecting circuit provided in an embodiment of the present invention, as shown in figure 3, this locking inspection
Slowdown monitoring circuit may include that phase-comparison circuit 01 and the state detection circuit 02 being coupled with this phase-comparison circuit.
This phase-comparison circuit 01 is used for receiving reference signal from the reference signal input a of this phaselocked loop 10 respectively, from
The feedback signal input terminal b of this phaselocked loop 10 receives feedback signal, and receives mode of operation signal from this controller 20, its
In, this mode of operation signal designation mode of operation under preferable lock-out state for this phaselocked loop, this mode of operation includes first
Mode of operation and the second mode of operation, under this first mode of operation, the phase place of this reference signal lags behind this feedback signal
Phase place, in this second mode of operation, the phase place of this feedback signal lags behind the phase place of this reference signal.
This phase-comparison circuit 01 is additionally operable to according to this reference signal, this feedback signal and this mode of operation signal, raw
In contrast with signal, this contrast signal indicates phase relation under actual working state for this phaselocked loop and states preferable locking with this
Whether the phase relation under state is identical, wherein, phase relation under actual working state for this phaselocked loop i.e. this reference signal
Phase relation with this feedback signal.
This state detection circuit 02 is used for obtaining clock signal and this contrast signal, and according to this clock signal and this contrast
Signal, detects to the working condition of this phaselocked loop, this working condition includes lock-out state or out-of-lock condition.
Wherein, the mode of operation of this phaselocked loop 10 can be controlled by this controller 20, and example, for Fig. 1 b
Shown offset cp phaselocked loop, can control this phaselocked loop in preferable locking shape by controlling offset sense of current
Mode of operation under state, specifically, is to flow to low pass filter 104 from charge pump 103 when controlling this offset sense of current
When, mode of operation under preferable lock-out state for this phaselocked loop is the first mode of operation；When this offset sense of current of control
It is Working mould under preferable lock-out state for this phaselocked loop when low pass filter flow to charge pump (flow direction shown in Fig. 1 b)
Formula is the second mode of operation.For different types of phaselocked loop, controller is also different to the control method of its mode of operation, this
Bright embodiment does not limit to this.
Fig. 4 a is the structural representation of another kind lock detecting circuit provided in an embodiment of the present invention, as shown in fig. 4 a,
In a kind of optional implementation of the present invention, this phase-comparison circuit 01 may include that d trigger 011 and gate 012.
On the one hand, the clock signal input terminal ck of this d trigger 011 is used for receiving this reference signal, the number of this d trigger
It is used for receiving this feedback signal according to signal input part d, the outfan q of this d trigger is connected with the first input end of this gate 012
Connect, this d trigger 011 is used for this reference signal as sampled clock signal, sampling is carried out to the level of this feedback signal and obtains
Sampled signal.
On the other hand, the clock signal input terminal ck of this d trigger 011 can also receive this feedback signal, then this d triggering
The data signal input d of device 011 receives this reference signal, and the outfan of this d trigger 011 inputs with the first of this gate
End connects, and now, this d trigger can be adopted with this feedback signal as sampled clock signal to the level of this reference signal
Sample obtains sampled signal.
With reference to Fig. 4 a, this gate 012 is used for receiving the sampled signal of this d trigger output by this first input end,
And this mode of operation signal is received by the second input of this gate, and believed according to this sampled signal and this mode of operation
Number carry out logical operationss, generate contrast signal.Specifically, this gate can be XOR gate, then now this XOR gate can be right
This sampled signal and this mode of operation signal generate this contrast signal after carrying out XOR；Or, this gate can also be
Same OR gate, this can carry out to this sampled signal and this mode of operation signal generating this contrast signal after same or computing with OR gate.
It should be noted that in actual applications, it is also provided with multiple gates in this phase-comparison circuit 01
012, such as, with door, OR gate or NAND gate etc., the plurality of gate is capable of XOR gate or the logical effect with OR gate,
The embodiment of the present invention is not specifically limited to the number of gate in this phase-comparison circuit and type.
Further, with reference to Fig. 4 a, in a kind of optional implementation of the present invention, this state detection circuit 02 can wrap
Include: enumerator 021 and comparator 022.
The input of this enumerator 021 is used for receiving this contrast signal, and the clock signal terminal ck of this enumerator 021 is used for connecing
Receive clock signal, the outfan of this enumerator 021 is connected with the input of this comparator 022, this enumerator 021 is used for basis should
Clock signal, carried out counting to get count results to the predetermined level in this contrast signal within the default counting cycle, and will
This count results sends to this comparator 022.
Wherein, with reference to Fig. 4 a, this lock detecting circuit can also include: clock generator 03, this enumerator 021 is received
Clock signal can be the dagital clock signal being produced by this clock generator 03, the frequency of this clock signal can according to
Practical situation pre-sets；Or can also be directly by the reference signal input in this phaselocked loop and this enumerator 021
Clock signal terminal is coupled, and that is to say, using the reference signal in this phaselocked loop as this enumerator 021 clock signal.Additionally,
In this enumerator 021, the default counting cycle flexibly can be arranged according to the practical situation of lock detecting circuit, general counting week
Phase is longer, and the accuracy of detection of this lock detecting circuit is higher.
The count results that this comparator 022 is used for sending this enumerator 021 are compared with default count threshold, and
This state detection signal is generated according to comparative result.Specifically, when this count results is more than this count threshold, determine this lock phase
The working condition of ring is out-of-lock condition；When this count results is not more than this count threshold, determine the working condition of this phaselocked loop
For lock-out state.
It should be noted that in actual applications, can be provided with defeated for the count pick up cycle in this enumerator 021
Enter end, the input that can also be provided with this comparator 022 for count pick up threshold value and count the cycle, this comparator 022
The count results receiving within this counting cycle and default count threshold can be compared.
It is assumed that this phaselocked loop is in the first mode of operation (i.e. reference signal in a kind of optional implementation of the present invention
Phase place lag behind the phase place of feedback signal) when, the mode of operation signal of controller output is high level, and this phaselocked loop is in the
During two mode of operations (i.e. the phase place of feedback signal lags behind the phase place of reference signal), this mode of operation signal is low level, ginseng
Examine Fig. 4 a, reference signal is received with the clock signal terminal ck of this d trigger 011, data signal end d receives feedback signal, and this is patrolled
Collect door 012 for, as a example XOR gate, being described in detail to the operation principle of this lock detecting circuit.Due to this d trigger 011
Clock signal terminal ck receives reference signal, and therefore this d trigger 011 can be with this reference signal as sampled clock signal, logarithm
Feedback signal according to signal end d input is sampled, and that is to say, in the rising edge of this reference signal, to the of this gate 012
One input exports the level of this feedback signal.
Fig. 4 b and Fig. 4 c is phaselocked loop provided in an embodiment of the present invention reference signal and feedback letter under different working modes
Number timing diagram.Wherein Fig. 4 b is that in the first mode of operation, (i.e. the phase place of reference signal lags behind feedback signal to phaselocked loop
Phase place) under, the sequential chart of reference signal and feedback signal it is assumed that this reference signal and feedback signal in high level effectively,
Then it is seen from fig. 4b that when the phase place of reference signal lag behind feedback signal phase place when, if this reference signal and feedback letter
Phase relation between number is stable (i.e. when phaselocked loop is in the lock state), and d trigger 011 is in the rising edge pair of reference signal
Feedback signal is when being sampled, and the sampled signal obtaining is the high level level of a point (i.e. in Fig. 4 b), and now this d trigger is defeated
Go out 1；If the phase relation unstable (i.e. when phaselocked loop is in out-of-lock condition) between this reference signal and feedback signal, this d
The sampled signal of this feedback signal of trigger 011 output then may be for 1 it is also possible to also comprise 0.
Fig. 4 c is phaselocked loop under the second mode of operation (i.e. the phase place of feedback signal lags behind the phase place of reference signal), ginseng
Examine signal and the sequential chart of feedback signal, can be seen that from Fig. 4 c and lag behind the phase place of reference signal when the phase place of feedback signal
When, if the phase relation between this reference signal and feedback signal is stable, d trigger 011 reference signal rising edge to anti-
When feedback signal is sampled, the signal that obtains of sampling is the low level level of b point (i.e. in Fig. 4 c), i.e. this d trigger output 0；
If the phase relation between this reference signal and feedback signal is unstable, the sampling letter of this feedback signal of this d trigger output
Number then may be for 0 it is also possible to also comprise 1.
The operation principle of XOR gate as shown in table 1, when that is, the level of two input inputs is different, is output as 1, two defeated
When entering to hold the level of input identical, it is output as 0.
Table 1
| First input end | Second input | Outfan |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Therefore, when phaselocked loop is in the first mode of operation, if the phase relation between this reference signal and feedback signal
Stable, then the signal of the first input end output to XOR gate 012 for this d trigger 011 should be 1, due to now this XOR gate 012
The mode of operation signal of the second input input is 1, then the contrast signal of XOR gate 012 outfan output should be all 0；If this ginseng
The phase relation examined between signal and feedback signal is unstable, then this d trigger 011 is defeated to the first input end of XOR gate 012
The signal going out is also unstable, and that is, the signal of the now first input end output to gate 012 for this d trigger 011 may be 1
May be 0, the contrast signal of therefore now this XOR gate 012 output is 1 or 0.
When mode of operation under preferable lock-out state for the phaselocked loop is the second mode of operation, that is, feed back the delayed phase of signal
When the phase place of reference signal, if the phase relation between this reference signal and feedback signal is stable, this d trigger 011 is to different
The signal of the first input end output of OR gate 012 should be 0, due to the Working mould of now this XOR gate 012 second input input
Formula signal is 0, then the contrast signal of XOR gate 012 outfan output also should be 0；If between this reference signal and feedback signal
Phase relation unstable, then this XOR gate 012 output contrast signal be 1 or 0.
According to above-mentioned analysis, in mode of operation signal, work under preferable lock-out state for the phaselocked loop is indicated with high level
Operation mode is the first mode of operation, and mode of operation signal indicates work under preferable lock-out state for this phaselocked loop with low level
Operation mode is the second mode of operation, and the clock signal terminal ck of this d trigger receives reference signal, and this gate 012 is XOR
In the case of door, when this phaselocked loop is lock-out state, the contrast signal of this XOR gate 012 output should be all 0, when this lock phase
When ring is out-of-lock condition, the contrast signal of this XOR gate 012 output can be 1 or 0.Therefore, enumerator 021 is receiving this
After contrast signal, the predetermined level in this contrast signal being counted can be high level, that is to say, this enumerator 021 is permissible
With this reference signal as clock signal, within the default counting cycle, the high level of this contrast signal is counted, example
It is assumed that the cycle of counting is 1s, cycle of this reference signal is 0.1s, then, within this counting cycle, this enumerator 021 can be adopted
Sample obtains 10 level signals, and the high level in this 10 level signals is counted, if in this counting cycle 1s, meter
Number device 021 statistics obtains this 10 level signals and includes 5 high level, then count results 5 can be sent by this enumerator 021
To comparator 022.If default count threshold is 3 in this comparator 022, when comparator 022 receives count results 5,
Can determine that this count results 5 is more than count threshold 3, and then can determine in this phaselocked loop between reference signal and feedback signal
Phase relation unstable, and determine this phaselocked loop be out-of-lock condition.
In embodiments of the present invention, due to when phaselocked loop is in the first mode of operation, this mode of operation signal can be
Low level, accordingly, when phaselocked loop is in as the second mode of operation, this mode of operation signal is high level, and this d trigger
What middle clock signal terminal was accessed can also can be feedback signal for reference signal, and this gate is to sampled signal and Working mould
The logical operationss that formula signal is carried out can also be able to be same or computing for XOR.Therefore, what this enumerator was counted is pre-
If level can be according to clock signal termination in level under different working modes for this mode of operation signal height, d trigger
The signal type entering, and the type (i.e. the type of logical operationss) of this gate is configured.
Specifically as shown in table 2, on the one hand, to indicate this phaselocked loop in preferable locking shape in this mode of operation signal with high level
Mode of operation under state is the first mode of operation, and this mode of operation signal indicates this phaselocked loop in preferable locking with low level
In the case that mode of operation under state is the second mode of operation, when this sampled signal is with this reference signal by this d trigger
Carry out sampling as sampled clock signal to obtain, and when this contrast signal is to be generated by XOR by this gate, this is pre-
If level is high level；Or, when this sampled signal is to be carried out as sampled clock signal using this feedback signal by this d trigger
Sampling obtains, and when this contrast signal is to pass through same or computing generation by this gate, this predetermined level is high level；Or,
When this sampled signal is to carry out sampling using this reference signal as sampled clock signal by this d trigger to obtain, and this contrast letter
Number it is to be passed through with by this gate or when computing generates, this predetermined level is low level；Or, when this sampled signal is by this d
Trigger carries out sampling using this feedback signal as sampled clock signal and obtains, and this contrast signal is by different by this gate
Or during computing generation, this predetermined level is low level.
On the other hand, indicate Working mould under preferable lock-out state for this phaselocked loop with low level in this mode of operation signal
Formula is the first mode of operation, and this mode of operation signal indicates work under preferable lock-out state for this phaselocked loop with high level
In the case that pattern is the second mode of operation, when this sampled signal is using this reference signal as sampling clock by this d trigger
Signal carries out sampling and obtains, and when this contrast signal is to be generated by XOR by this gate, this predetermined level is low electricity
Flat；Or, when this sampled signal is to carry out sampling using this feedback signal as sampled clock signal by this d trigger to obtain, and
When this contrast signal is to pass through same or computing generation by this gate, this predetermined level is low level；Or, when this sampled signal
It is to carry out sampling using this reference signal as sampled clock signal by this d trigger to obtain, and this contrast signal is by this logic
When door passes through with or computing generates, this predetermined level is high level；Or, when this sampled signal is anti-with this by this d trigger
Feedback signal carries out sampling as sampled clock signal and obtains, and this contrast signal is to be generated by XOR by this gate
When, this predetermined level is high level.
Table 2
It should be noted that the above embodiment of the present invention is all with the significant level of reference signal and feedback signal for high electricity
Illustrate as a example flat, in actual applications, the significant level of this reference signal and feedback signal can also be low level, then
The height of the predetermined level shown in above-mentioned table 2 also needs to be adjusted accordingly.
Also, it should be noted in actual applications, having the lock of fixed skew between reference signal and feedback signal
Xiang Huan, all can be detected to the working condition in phaselocked loop using lock detecting circuit provided in an embodiment of the present invention, this
The application scenarios of this lock detecting circuit of inventive embodiments do not limit.Additionally, above-mentioned all optional implementations, Ke Yiren
Meaning combines to form the alternative embodiment of the present invention.
In sum, embodiments provide a kind of lock detecting circuit, this lock detecting circuit includes phase place ratio
Compared with circuit and state detection circuit, wherein phase-comparison circuit can generate for instruction with reference to letter according to mode of operation signal
The contrast signal of the phase relation number and this feedback signal between, state detection circuit can be believed according to reference signal and this contrast
Number, the working condition of this phaselocked loop is detected.Lock detecting circuit provided in an embodiment of the present invention is by d trigger, logic
Door, an enumerator and a comparator composition, the element that this lock detecting circuit is comprised is less, and circuit structure is more simple
Single.
Fig. 5 is a kind of flow chart of lock detecting method provided in an embodiment of the present invention, and the method can apply to as Fig. 3
Or in the lock detecting circuit shown in Fig. 4 a, as can be seen that this lock detecting circuit includes from Fig. 3 or Fig. 4 a: phase bit comparison
Circuit 01 and the state detection circuit 02 being coupled with this phase-comparison circuit, this lock detecting circuit can respectively with, lock
The reference signal input of phase ring and feedback signal input terminal, and controller is coupled, as shown in figure 5, the method can be wrapped
Include:
Step 501, receive reference signal from the reference signal input of phaselocked loop respectively, defeated from the feedback signal of phaselocked loop
Enter end and receive feedback signal, and receive mode of operation signal from controller.
Wherein, this mode of operation signal designation mode of operation under preferable lock-out state for this phaselocked loop, this Working mould
Formula includes the first mode of operation and the second mode of operation, and under this first mode of operation, the phase place of this reference signal lags behind this
The phase place of feedback signal, in this second mode of operation, the phase place of this feedback signal lags behind the phase place of this reference signal.
Step 502, according to this reference signal, this feedback signal and this mode of operation signal, generate contrast signal.
This contrast signal indicates phase relation under actual working state for this phaselocked loop and states preferable locking shape with this
Whether the phase relation under state identical, wherein, phase relation under actual working state for this phaselocked loop i.e. this reference signal and
The phase relation of this feedback signal.
Step 503, acquisition clock signal and this contrast signal, and according to this clock signal and this contrast signal to this lock phase
The working condition of ring is detected, this working condition includes lock-out state or out-of-lock condition.
Method shown in step 501 and step 502 can be by the phase-comparison circuit 01 in above-mentioned lock detecting circuit
Realize, the method shown in step 503 can be realized by the state detection circuit 02 in this lock detecting circuit.Above-mentioned steps
Lock detecting method shown in 501 to step 503 implement process may be referred to aforementioned for lock detecting circuit work
The description of principle, the embodiment of the present invention repeats no more.
The embodiment of the present invention additionally provides a kind of phase lock circuitry, with reference to Fig. 2, this phase lock circuitry may include that phaselocked loop 10,
Controller 20 and lock detecting circuit as described in relation to the first aspect 00, this lock detecting circuit 00 is respectively with phaselocked loop 10
Reference signal input a and feedback signal input terminal b, and controller 20 is coupled.
This phaselocked loop 10 is used for sending reference signal by this reference signal input a to this lock detecting circuit, and leads to
Cross this feedback signal input terminal b and send feedback signal to this lock detecting circuit.
This controller 20 is used for controlling the mode of operation of this phaselocked loop 10, and sends Working mould to this lock detecting circuit 00
Formula signal, this mode of operation under preferable lock-out state for the phaselocked loop 10 of this mode of operation signal designation, this mode of operation bag
Include the first mode of operation and the second mode of operation, in the first operation mode, the phase place of this reference signal lags behind this feedback letter
Number phase place, in this second mode of operation, the phase place of this feedback signal lags behind the phase place of this reference signal.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement made etc., should be included within the scope of the present invention.
Claims (19)
1. a kind of lock detecting circuit is it is characterised in that described lock detecting circuit is respectively with the reference signal of phaselocked loop inputs
End and feedback signal input terminal, and controller is coupled, described lock detecting circuit includes: phase-comparison circuit and with institute
State the state detection circuit that phase-comparison circuit is coupled；
Described phase-comparison circuit is used for receiving reference signal from the reference signal input of described phaselocked loop respectively, from described lock
The feedback signal input terminal of phase ring receives feedback signal, and receives mode of operation signal, wherein, described work from described controller
Operation mode signal designation mode of operation under preferable lock-out state for the described phaselocked loop, described mode of operation includes the first work
Pattern and the second mode of operation, in this first operative mode, the phase place of described reference signal lags behind described feedback signal
Phase place, under described second mode of operation, the phase place of described feedback signal lags behind the phase place of described reference signal；
Described phase-comparison circuit is additionally operable to according to described reference signal, described feedback signal and described mode of operation signal,
Generate contrast signal, described contrast signal indicates phase relation under actual working state for the described phaselocked loop and in described reason
Think whether the phase relation under lock-out state is identical, wherein, phase relation under actual working state for the described phaselocked loop is institute
State reference signal and the phase relation of described feedback signal；
Described state detection circuit is used for obtaining clock signal and described contrast signal, and according to described clock signal and described right
Ratio signal, detects to the working condition of described phaselocked loop, described working condition includes lock-out state or out-of-lock condition.
2. lock detecting circuit according to claim 1 is it is characterised in that described phase-comparison circuit, comprising: data is touched
Send out device and gate；
The clock signal input terminal of described data trigger is used for receiving described reference signal, the data letter of described data trigger
Number input is used for receiving described feedback signal, and the first input end of the outfan of described data trigger and described gate is even
Connect, described data trigger is used for described reference signal as sampled clock signal, the level of described feedback signal is adopted
Sample obtains sampled signal；
Described gate is used for receiving described sampled signal by described first input end, and by described gate second is defeated
Enter end and receive described mode of operation signal, and logical operationss are carried out according to described sampled signal and described mode of operation signal,
Generate described contrast signal.
3. lock detecting circuit according to claim 1 is it is characterised in that described phase-comparison circuit, comprising: data is touched
Send out device and gate；
The clock signal input terminal of described data trigger is used for receiving described feedback signal, the data letter of described data trigger
Number input is used for receiving described reference signal, and the first input end of the outfan of described data trigger and described gate is even
Connect, described data trigger is used for, with described feedback signal as sampled clock signal, the level of described reference signal being adopted
Sample obtains sampled signal；
Described gate is used for receiving described sampled signal by described first input end, and by described gate second is defeated
Enter end and receive described mode of operation signal, and logical operationss are carried out according to described sampled signal and described mode of operation signal,
Generate described contrast signal.
4. the lock detecting circuit according to Claims 2 or 3 it is characterised in that
Described logical operationss be XOR with or one of computing.
5. lock detecting circuit according to claim 4 is it is characterised in that described state detection circuit, comprising: enumerator
And comparator；
The input of described enumerator is used for receiving described contrast signal, and the clock signal terminal of described enumerator is used for receiving described
Clock signal, the outfan of described enumerator is connected with the input of described comparator, described enumerator be used for according to described when
Clock signal, carried out counting to get count results to the predetermined level in described contrast signal within the default counting cycle, and will
Described count results send to described comparator；
Described comparator is used for being compared described count results with default count threshold, and according to comparative result, to institute
The working condition stating phaselocked loop is detected.
6. lock detecting circuit according to claim 5 it is characterised in that
In described mode of operation signal with high level instruction mode of operation under preferable lock-out state for the described phaselocked loop for first
Mode of operation, and described mode of operation signal is with low level instruction mode of operation under preferable lock-out state for the described phaselocked loop
In the case of the second mode of operation,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is high level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described feedback signal by described data trigger
Arrive, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is high level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is low level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described feedback signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is low level.
7. lock detecting circuit according to claim 5 it is characterised in that
In described mode of operation signal with low level instruction mode of operation under preferable lock-out state for the described phaselocked loop for first
Mode of operation, and described mode of operation signal is with high level instruction mode of operation under preferable lock-out state for the described phaselocked loop
In the case of the second mode of operation,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is low level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described feedback signal by described data trigger
Arrive, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is low level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is high level；Or,
When described sampled signal is to carry out sampling as sampled clock signal using described feedback signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is high level.
8. according to the arbitrary described lock detecting circuit of claim 5 to 7 it is characterised in that described comparator, specifically for:
Described count results are compared with default count threshold, when described count results are more than described count threshold,
Determine described phaselocked loop working condition be out-of-lock condition；
When described count results are not more than described count threshold, determine that the working condition of described phaselocked loop is lock-out state.
9. according to the arbitrary described lock detecting circuit of claim 1 to 8 it is characterised in that described state detection circuit obtains
Described clock signal be described reference signal；
Or, described lock detecting circuit also includes: clock generator, and described state detection circuit is additionally operable to send out from described clock
Raw device obtains described clock signal.
10. it is characterised in that being applied to lock detecting circuit, described lock detecting circuit includes a kind of lock detecting method: phase
Bit comparison circuit and the state detection circuit being coupled with described phase-comparison circuit, described lock detecting circuit respectively with,
The reference signal input of phaselocked loop and feedback signal input terminal, and controller is coupled, methods described includes:
Receive reference signal from the reference signal input of described phaselocked loop respectively, from the feedback signal input terminal of described phaselocked loop
Receive feedback signal, and receive mode of operation signal from described controller, wherein, described mode of operation signal designation is described
Mode of operation under preferable lock-out state for the phaselocked loop, described mode of operation includes the first mode of operation and the second mode of operation,
In this first operative mode, the phase place of described reference signal lags behind the phase place of described feedback signal, in described second work
Under operation mode, the phase place of described feedback signal lags behind the phase place of described reference signal；
According to described reference signal, described feedback signal and described mode of operation signal, generate contrast signal, described contrast letter
Number indicate phase relation under actual working state for the described phaselocked loop and the phase relation under described ideal lock-out state
Whether identical, wherein, phase relation under actual working state for the described phaselocked loop is described reference signal and described feedback letter
Number phase relation；
Obtain clock signal and described contrast signal, and according to described clock signal and described contrast signal to described phaselocked loop
Working condition is detected, described working condition includes lock-out state or out-of-lock condition.
11. methods according to claim 10 it is characterised in that described according to described reference signal, described feedback signal
And described mode of operation signal, generate contrast signal, comprising:
Using described reference signal as sampled clock signal, the level of described feedback signal is sampled, obtains sampled signal；
Logical operationss are carried out according to described sampled signal and described mode of operation signal, generates described contrast signal.
12. methods according to claim 10 it is characterised in that described according to described reference signal, described feedback signal
And described mode of operation signal, generate contrast signal, comprising:
Using described feedback signal as sampled clock signal, the level of described reference signal is sampled, obtains sampled signal；
Logical operationss are carried out according to described sampled signal and described mode of operation signal, generates described contrast signal.
13. methods according to claim 11 or 12 are it is characterised in that described logical operationss are XOR or same or fortune
One of calculate.
14. methods according to claim 13 it is characterised in that described according to described clock signal with described contrast signal
The working condition of described phaselocked loop is detected, comprising:
According to described clock signal, the predetermined level of described contrast signal is carried out counting to get meter within the default counting cycle
Number result；
Count results are compared with default count threshold, and according to comparative result, the working condition to described phaselocked loop
Detected.
15. methods according to claim 14 it is characterised in that
In described mode of operation signal with high level instruction mode of operation under preferable lock-out state for the described phaselocked loop for first
Mode of operation, and described mode of operation signal is with low level instruction mode of operation under preferable lock-out state for the described phaselocked loop
In the case of the second mode of operation,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is high level；
Or, when described sampled signal is to be adopted as sampled clock signal using described feedback signal by described data trigger
Sample obtains, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is high level；
Or, when described sampled signal is to be adopted as sampled clock signal using described reference signal by described data trigger
Sample obtains, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is low level；
Or, when described sampled signal is to be adopted as sampled clock signal using described feedback signal by described data trigger
Sample obtains, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is low level.
16. methods according to claim 14 it is characterised in that
In described mode of operation signal with low level instruction mode of operation under preferable lock-out state for the described phaselocked loop for first
Mode of operation, and described mode of operation signal is with high level instruction mode of operation under preferable lock-out state for the described phaselocked loop
In the case of the second mode of operation,
When described sampled signal is to carry out sampling as sampled clock signal using described reference signal by described data trigger
Arrive, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is low level；
Or, when described sampled signal is to be adopted as sampled clock signal using described feedback signal by described data trigger
Sample obtains, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is low level；
Or, when described sampled signal is to be adopted as sampled clock signal using described reference signal by described data trigger
Sample obtains, and when described contrast signal is to pass through same or computing generation by described gate, described predetermined level is high level；
Or, when described sampled signal is to be adopted as sampled clock signal using described feedback signal by described data trigger
Sample obtains, and when described contrast signal is to be generated by XOR by described gate, described predetermined level is high level.
17. according to the arbitrary described method of claim 14 to 16 it is characterised in that described by described count results with default
Count threshold is compared, and according to comparative result, the working condition of described phaselocked loop is detected, comprising:
Described count results are compared with default count threshold, when described count results are more than described count threshold,
Determine described phaselocked loop working condition be out-of-lock condition；
When described count results are not more than described count threshold, determine that the working condition of described phaselocked loop is lock-out state.
18. according to the arbitrary described method of claim 10 to 17 it is characterised in that described clock signal be described with reference to letter
Number；Or, the signal that described clock signal generates for clock generator.
A kind of 19. phase lock circuitries are it is characterised in that described phase lock circuitry includes: phaselocked loop, controller and as claim 1
To 9 arbitrary described lock detecting circuits, described lock detecting circuit respectively with, the reference signal input of phaselocked loop and feedback
Signal input part, and controller is coupled；
Described phaselocked loop is used for sending reference signal by described reference signal input to described lock detecting circuit, and passes through
Described feedback signal input terminal sends feedback signal to described lock detecting circuit；
Described controller is used for sending mode of operation signal, described mode of operation signal designation institute to described lock detecting circuit
State mode of operation under preferable lock-out state for the phaselocked loop, described mode of operation includes the first mode of operation and the second Working mould
Formula, in the first operation mode, the phase place of described reference signal lags behind the phase place of described feedback signal, in the described second work
Under pattern, the phase place of described feedback signal lags behind the phase place of described reference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610737928.7A CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610737928.7A CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106357266A true CN106357266A (en) | 2017-01-25 |
| CN106357266B CN106357266B (en) | 2019-07-23 |
Family
ID=57855905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610737928.7A Active CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106357266B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107786202A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of lock indicator circuit that function is eliminated with error code |
| CN108183708A (en) * | 2018-01-17 | 2018-06-19 | 上海艾为电子技术股份有限公司 | PGC demodulation detection method and its circuit, phaselocked loop |
| CN108712168A (en) * | 2018-07-26 | 2018-10-26 | 四川知微传感技术有限公司 | A kind of lock detecting circuit suitable for analog phase-locked look |
| WO2020103775A1 (en) * | 2018-11-23 | 2020-05-28 | 深圳市中兴微电子技术有限公司 | Method and device for smooth transition of reference clock under lock state of analog phase-locked loop |
| CN111435827A (en) * | 2020-01-14 | 2020-07-21 | 珠海市杰理科技股份有限公司 | Quick oscillation starting circuit and method, crystal oscillator and integrated chip |
| CN112037362A (en) * | 2020-09-04 | 2020-12-04 | 北京骑胜科技有限公司 | Shared vehicle abnormality detection method, shared vehicle abnormality detection device, shared vehicle, and storage medium |
| CN113412573A (en) * | 2019-04-25 | 2021-09-17 | 华为技术有限公司 | Charge pump, phase-locked loop circuit and clock control device |
| WO2022037216A1 (en) * | 2020-08-20 | 2022-02-24 | 长鑫存储技术有限公司 | Detection circuit and detection method |
| CN114201440A (en) * | 2021-12-14 | 2022-03-18 | 上海微阱电子科技有限公司 | Clock detection method, circuit, serial port communication system, medium and device |
| CN114421957A (en) * | 2022-03-29 | 2022-04-29 | 长芯盛（武汉）科技有限公司 | Lock loss detection circuit and lock loss detection method |
| US11402431B2 (en) | 2020-08-20 | 2022-08-02 | Changxin Memory Technologies, Inc. | Detection circuit and detection method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388666A (en) * | 2008-10-10 | 2009-03-18 | 哈尔滨工业大学 | Non-linear frequency and phase discriminator without phase discriminating blind zone |
| CN101741380A (en) * | 2009-12-22 | 2010-06-16 | 北京中星微电子有限公司 | Method and system for locking detection of phase-locked loop and phase-locked loop circuit |
| US20120183104A1 (en) * | 2011-01-13 | 2012-07-19 | Jong-Phil Hong | Digital phase frequency detector, digital phase locked loop including the same and method of detecting phase and frequency of output signal |
| US20150078501A1 (en) * | 2013-09-18 | 2015-03-19 | Analog Devices, Inc. | Lock detector for phase-locked loop |
| CN104485946A (en) * | 2014-12-05 | 2015-04-01 | 中国航天科技集团公司第九研究院第七七一研究所 | PLL (phase-locked loop) locking state detection circuit |
-
2016
- 2016-08-26 CN CN201610737928.7A patent/CN106357266B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388666A (en) * | 2008-10-10 | 2009-03-18 | 哈尔滨工业大学 | Non-linear frequency and phase discriminator without phase discriminating blind zone |
| CN101741380A (en) * | 2009-12-22 | 2010-06-16 | 北京中星微电子有限公司 | Method and system for locking detection of phase-locked loop and phase-locked loop circuit |
| US20120183104A1 (en) * | 2011-01-13 | 2012-07-19 | Jong-Phil Hong | Digital phase frequency detector, digital phase locked loop including the same and method of detecting phase and frequency of output signal |
| US20150078501A1 (en) * | 2013-09-18 | 2015-03-19 | Analog Devices, Inc. | Lock detector for phase-locked loop |
| CN104485946A (en) * | 2014-12-05 | 2015-04-01 | 中国航天科技集团公司第九研究院第七七一研究所 | PLL (phase-locked loop) locking state detection circuit |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107786202B (en) * | 2017-11-09 | 2021-10-01 | 上海华力微电子有限公司 | Locking indicator circuit with error code eliminating function |
| CN107786202A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of lock indicator circuit that function is eliminated with error code |
| CN108183708A (en) * | 2018-01-17 | 2018-06-19 | 上海艾为电子技术股份有限公司 | PGC demodulation detection method and its circuit, phaselocked loop |
| CN108183708B (en) * | 2018-01-17 | 2022-04-15 | 上海艾为电子技术股份有限公司 | Phase locking detection method and circuit thereof, and phase-locked loop |
| CN108712168A (en) * | 2018-07-26 | 2018-10-26 | 四川知微传感技术有限公司 | A kind of lock detecting circuit suitable for analog phase-locked look |
| CN108712168B (en) * | 2018-07-26 | 2023-09-26 | 四川知微传感技术有限公司 | Lock detection circuit suitable for analog phase-locked loop |
| WO2020103775A1 (en) * | 2018-11-23 | 2020-05-28 | 深圳市中兴微电子技术有限公司 | Method and device for smooth transition of reference clock under lock state of analog phase-locked loop |
| US11601129B2 (en) | 2019-04-25 | 2023-03-07 | Huawei Technologies Co., Ltd. | Charge pump, phase-locked loop circuit, and clock control apparatus |
| CN113412573A (en) * | 2019-04-25 | 2021-09-17 | 华为技术有限公司 | Charge pump, phase-locked loop circuit and clock control device |
| CN113412573B (en) * | 2019-04-25 | 2023-05-09 | 华为技术有限公司 | Charge pump, phase-locked loop circuit and clock control device |
| CN111435827A (en) * | 2020-01-14 | 2020-07-21 | 珠海市杰理科技股份有限公司 | Quick oscillation starting circuit and method, crystal oscillator and integrated chip |
| CN111435827B (en) * | 2020-01-14 | 2023-11-28 | 珠海市杰理科技股份有限公司 | Quick oscillation starting circuit, method, crystal oscillator and integrated chip |
| WO2022037216A1 (en) * | 2020-08-20 | 2022-02-24 | 长鑫存储技术有限公司 | Detection circuit and detection method |
| US11402431B2 (en) | 2020-08-20 | 2022-08-02 | Changxin Memory Technologies, Inc. | Detection circuit and detection method |
| CN112037362A (en) * | 2020-09-04 | 2020-12-04 | 北京骑胜科技有限公司 | Shared vehicle abnormality detection method, shared vehicle abnormality detection device, shared vehicle, and storage medium |
| CN114201440A (en) * | 2021-12-14 | 2022-03-18 | 上海微阱电子科技有限公司 | Clock detection method, circuit, serial port communication system, medium and device |
| CN114421957A (en) * | 2022-03-29 | 2022-04-29 | 长芯盛（武汉）科技有限公司 | Lock loss detection circuit and lock loss detection method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106357266B (en) | 2019-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106357266A (en) | Locked detecting circuit, method and phase-locked circuit | |
| US8258831B1 (en) | Method and apparatus for clock generator lock detector | |
| US8536910B2 (en) | System and method for reducing power consumption in a phased-locked loop circuit | |
| CN100508399C (en) | Phase and frequency detection circuits | |
| US7920665B1 (en) | Symmetrical range controller circuit and method | |
| US5483558A (en) | Method and apparatus for detecting phase or frequency lock | |
| US8040156B2 (en) | Lock detection circuit and lock detecting method | |
| CN109639271B (en) | Lock indication circuit and phase-locked loop formed by same | |
| US7676014B2 (en) | Digital lock detector for phase-locked loop | |
| CN101977053A (en) | Locked detection circuit applied to phase locked loop (PLL) with dynamic reconfigurable frequency dividing ratio | |
| CN102361456A (en) | Clock phase alignment and adjustment circuit | |
| CN111953339B (en) | Phase-locked loop fast locking frequency discrimination circuit | |
| WO2006044123A1 (en) | Reducing metastable-induced errors from a frequency detector that is used in a phase-locked loop | |
| US7859313B2 (en) | Edge-missing detector structure | |
| US7755397B2 (en) | Methods and apparatus for digital phase detection with improved frequency locking | |
| US6404240B1 (en) | Circuit and method of a three state phase frequency lock detector | |
| CN111464180B (en) | Phase-locked loop circuit with locking detection function | |
| US8456205B2 (en) | Phase-frequency comparator and serial transmission device | |
| US8059774B2 (en) | Frequency lock detection | |
| CN106209079A (en) | A kind of phase-locked loop circuit reducing the loop-locking time | |
| CN103986460B (en) | SoC chip internal clock generation circuit using unlocking indicating phase-locked loop | |
| CN113489488A (en) | Phase-locked detection circuit | |
| CN102006062B (en) | Phase locked loop with zero phase error | |
| CN103675648B (en) | A kind of device being applied to phaselocked loop irradiation experiment | |
| US8432201B1 (en) | Phase-locked loop (PLL) circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |