CN108768393B - Cycle slip suppression circuit for PLL frequency synthesizer - Google Patents
Cycle slip suppression circuit for PLL frequency synthesizer Download PDFInfo
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- CN108768393B CN108768393B CN201711373561.6A CN201711373561A CN108768393B CN 108768393 B CN108768393 B CN 108768393B CN 201711373561 A CN201711373561 A CN 201711373561A CN 108768393 B CN108768393 B CN 108768393B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
Abstract
The invention provides a cycle slip suppression circuit for a PLL frequency synthesizer, which comprises a cycle slip detector, a frequency selector, a cycle slip counting controller and a decoder. The cycle slip detector detects the phase difference between a reference signal Fref and a feedback signal Fdiv, and when the phase difference exceeds the phase discrimination range of the phase frequency discriminator PFD, the cycle slip detector generates an advanced detection pulse signal U _ CS or a lagging detection pulse signal D _ CS and outputs the advanced detection pulse signal U _ CS or the lagging detection pulse signal D _ CS to the frequency selector and the cycle slip counting controller; the frequency selector selects the leading detection pulse signal U _ CS or the lagging detection pulse signal D _ CS as a cycle slip pulse signal Fs to be output to the cycle slip counting controller, the cycle slip counting controller accumulates or subtracts cycle slip pulses to obtain decoder control words, and the current of a charge pump of the PLL frequency synthesizer is controlled to be turned on or turned off, so that locking of the PLL frequency synthesizer is accelerated.
Description
Technical Field
The invention relates to a cycle slip suppression circuit for a PLL frequency synthesizer, and belongs to the technical field of wireless communication radio frequency.
Background
The phase-locked loop frequency synthesizer is an important component module of a communication system, and the main index locking speed of the module determines the channel switching and the system starting speed of the communication system. Especially in Time Division Multiple Access (TDMA) and spread spectrum frequency hopping communication systems, the locking speed is the most critical index for determining the performance of the frequency synthesizer. For a common Charge Pump Phase Locked Loop (CPPLL), the requirements of phase noise, spurs, and locking speed on the loop bandwidth are always contradictory, and increasing the locking speed generally requires the phase locked loop to have a wide loop bandwidth, while obtaining good spurs and phase noise performance requires the phase locked loop to have a narrow loop bandwidth. When the loop bandwidth is narrower than the PFD frequency, the pll will cycle slip, which is caused by the accumulation of the phase error of the PFD too fast, and the linear range of the currently used PFD circuit is ± 2 pi, and beyond this range, the pll will not be in time to correct, so that the charge pump will draw current in the wrong direction, which will greatly prolong the locking time of the loop and reduce the locking speed.
Various cycle slip detection techniques have been proposed by researchers. US patent US7003065B2 proposes a "phase locked loop cycle slip detection" interface with the PFD, which provides logic to detect and indicate the leading and lagging cycle slips as they occur in the PFD, and is typically implemented with fewer logic gates and flip-flop arrangements, and other US patents such as US6466058B1, US6856202B2 also use similar techniques. This type of technique detects the number of cycles that the PFD circuit loses when comparing two input frequencies by using flip-flops and logic circuits. The U.S. patent US6265902B1 proposes a "phase detector for slip detection and a method for improving the lock time of a phase-locked loop", which uses an improved digital PFD circuit to detect and compensate the cycle slip between a reference frequency and a feedback frequency, the circuit is composed of a flip-flop type PFD circuit, 2 counter circuits and a logic gate, etc., the cycle slip detection circuit detects the number of cycles lost by two input frequencies of the PFD, and generates a correction signal to compensate the detected cycle slip, thereby improving the lock time of the phase-locked loop. Still other patents adopt more complicated circuit structures, and need to add additional converter circuits, or add additional control circuits to the voltage-controlled oscillator and the frequency divider, which increases the difficulty of implementation and affects the loop.
Disclosure of Invention
The technical solution of the invention is as follows: a cycle slip suppression circuit for a PLL frequency synthesizer is provided, and by inserting a cycle slip suppression circuit module which is realized in a full digit manner between a traditional PFD and a charge pump, the linear range of the PFD can be expanded, the influence of the cycle slip on the loop locking is reduced, and the locking of a phase-locked loop is accelerated.
The technical solution of the invention is as follows: a cycle slip suppression circuit for a PLL frequency synthesizer, the circuit comprising a cycle slip detector, a frequency selector, a cycle slip count controller, a decoder, wherein:
the cycle slip detector detects the phase difference between a reference signal Fref and a feedback signal Fdiv according to an input reference signal Fref and the feedback signal Fdiv of the PLL frequency synthesizer, a first output signal UP and a second output signal DN of a phase frequency detector PFD of the PLL frequency synthesizer, and generates an advanced detection pulse signal U _ CS to output to the frequency selector and the cycle slip counting controller when the phase difference of the reference signal Fref advanced relative to the feedback signal Fdiv exceeds the phase discrimination range of the PFD; when the phase difference of the reference signal Fref lagging the feedback signal Fdiv exceeds the phase discrimination range of the phase frequency discriminator PFD, generating a lagging detection pulse signal D _ CS and outputting the lagging detection pulse signal D _ CS to the frequency selector, wherein one pulse in the leading detection pulse signal U _ CS and the lagging detection pulse signal D _ CS represents one cycle slip; the phase detection ranges of the different types of PFDs are different, for example, the phase detection range for the SR flip-flop type PFD is pi, and the phase detection range for the D flip-flop type PFD is pi of ± 2.
A frequency selector which takes the advanced detection pulse signal U _ CS as the cycle slip pulse signal Fs when the reference signal Fref is advanced from the feedback signal Fdiv; when the reference signal Fref lags behind the feedback signal Fdiv, taking the lagging detection pulse signal D _ CS as the cycle slip pulse signal Fs; outputting the cycle slip pulse signal Fs to a cycle slip counting controller;
a cycle slip counting controller for accumulating the number of the received cycle slip pulse signals Fs within a certain range when receiving one cycle slip pulse signal Fs when the lead detection pulse signal U _ CS is 1, and accumulating the number of the received cycle slip pulse signals Fs within a certain range when receiving one cycle slip pulse signal Fs when the lead detection pulse signal U _ CS is 0 to obtain a decoder control word ai: 0, and outputting the decoder control word ai to a decoder;
and the decoder is used for decoding the decoder control word to obtain a current control signal of the charge pump and controlling the charge pump current of the PLL frequency synthesizer to be switched on or switched off, so that the locking of the PLL frequency synthesizer is accelerated.
The cycle slip detector comprises a first not gate INV0, a second not gate INV1, a third not gate INV2, a fourth not gate INV3, a fifth not gate INV4, a first D flip-flop DF2, a second D flip-flop DF3, a third D flip-flop DF4, a third D flip-flop DF4, a first AND gate AD0, a second AND gate AD2, a third AND gate AD3, a first delay unit delay2, a first NOR gate NR0 and a second NOR gate NR 1; a first output signal UP of a phase detector PFD of the PLL frequency synthesizer is connected to an input of a first not gate INV1, a second output signal DN of the PFD is connected to an input of a second not gate INV2, an output of the second not gate INV2 and a first output signal UP of the PFD are connected to an input of a second nand gate AD2, an output of the second nand gate AD2 is connected to a D of a second D flip-flop DF3 and an input of a second nor gate NR1, another input of the second nor gate NR1 is connected to an output of a fifth not gate INV4, an input of the fifth not gate INV4 is connected to a Q of the second D flip-flop DF3 and a D of a third D flip-flop DF4, an RN of the second D flip-flop DF3 is connected to an output of a third and gate AD3, a CK of a second D flip-flop DF3 is connected to a CK of a first D flip-flop DF2, while an output of the first D0 is connected to an and an output of an and a gate DF 92 is connected to a sixth input of a gate fcv for detecting a pulse signal fvq, a delay signal 5, an output end of the sixth not gate INV5 is connected to one input end of the third and gate AD3, the other input end of the third and gate AD3 is connected to high level, a D end of the first D flip-flop DF2 is connected to the output end of INV1 and one input end of the first nor gate NR0, a reset end RN of the first D flip-flop DF2 is connected to high level, the other input end of the first nor gate NR0 is connected to the output end of the fourth not gate INV3, an input end of the fourth not gate INV3 is connected to the Q end of the first D flip-flop DF2, the Q end of the first D flip-flop DF2 is represented as a detection leading pulse signal U _ CS, the input end of the INV0 is connected to Fref, an output end of the first not gate INV0 is connected to the input end of the first delay unit delay2 and one input end of the first and gate AD0, the other input end of the first and gate AD0 is connected to the output end of the first delay unit delay2, an output of the first nor gate NR0 is fed back to a PLL output of the PLL data phase detector corresponding to the first output end of the PLL, the output of the second nor gate NR1 is fed back to the other data terminal of the phase detector PFD of the PLL frequency synthesizer corresponding to the second output signal DN.
The third and gate AD3 is connected to a high level and replaced by an externally input enable signal EN _ CS, and the reset terminal of the first D flip-flop DF2 is also connected to the externally input enable signal EN _ CS.
The frequency selector is an or gate with two input ends, the input ends are a lag detection pulse signal D _ CS and a lead detection pulse signal U _ CS, and the output end is a cycle slip pulse signal Fs.
When the cycle slip detector generates and outputs the leading detection pulse signal U _ CS, the lagging detection pulse signal D _ CS is 0, so that U _ CS can be directly output to the cycle slip counting controller; when the cycle slip detector generates the lagging detection pulse signal D _ CS, the leading detection pulse signal U _ CS is 0, so that D _ CS can be directly output to the cycle slip counting controller, and the selection of the output frequency is realized.
The charge pump of the PLL frequency synthesizer is composed of an additional X-path charge pump circuit besides a default one-path charge pump circuit, each path of charge pump circuit comprises a first current source and a second current source, wherein one end of the first current source is connected with the second current source in series, the other end of the first current source is connected with a power supply VCC through a first charge-discharge switch, the other end of the second current source is grounded through a second charge-discharge switch, and connection points between the first current source and the second current source of all the charge pump circuits are connected together to serve as an output signal CPout of the charge pump. The default current control signals of one path of charge pump circuit are UP and DN, the additional X path of charge pump current control signals comprise a first switch control signal UP _ B [ X:1] and a second switch control signal DN _ B [ X:1], the first charge and discharge switches and the second charge and discharge switches of all charge pump circuits are respectively controlled by the first switch control signal UP _ B [ X:1] and the second switch control signal DN _ B [ X:1], and X is the number of the charge pump circuits.
The cycle slip counting controller comprises a cycle slip number controller, i + 1D triggers and an adder, wherein:
the cycle slip number controller receives a result Si: 0 output by the adder and a result ai: 0 output by the D trigger, performs logic operation on the advanced detection pulse signal U _ CS and the advanced detection pulse signal U _ CS, and sends the Si: 0 to the i + 1D triggers when the Si: 0 is smaller than X; otherwise, sending X to the i + 1D triggers;
the i + 1D triggers synchronously latch and output the output result T [ i:0] of the cycle number controller and send the multi-bit wide data A [ i:0] obtained by latching to the adder;
an adder for receiving the multi-bit wide data A [ i:0], adding 1 to the multi-bit wide data A [ i:0] every time a cycle slip pulse signal Fs pulse is received when the leading detection pulse signal U _ CS is 1, and subtracting 1 from the multi-bit wide data A [ i:0] every time a cycle slip pulse signal Fs pulse is received when the leading detection pulse signal U _ CS is 0; the result Si: 0 is fed back to the input of the cycle number controller.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the phase-locked loop, the cycle slip suppression circuit is inserted between the phase frequency detector and the charge pump, the working states of the voltage-controlled oscillator and the frequency divider are not influenced, the linear range of the PFD is expanded, and the locking speed of the phase-locked loop is improved.
(2) The cycle slip counting control circuit can be realized at 1-X (X is less than or equal to 2)i+1) Accumulation in the range or from 2i+1To 2i+1The accumulation and subtraction in the range of X, and the size of X can be flexibly set according to the actual requirement of a system circuit.
(3) The cycle slip detector of the present invention can select either an on or off mode.
(4) The cycle slip suppression circuit scheme based on full digital realization has simple structure and small circuit scale. The method is very suitable for the field of wireless communication or frequency hopping communication with high integration level, low power consumption and quick locking.
(5) The invention does not require modification of other circuits in the loop. The control scheme is simple, the circuit scale is small, the power consumption is low, and the influence on a loop is small.
Drawings
FIG. 1 is a general block diagram of a cycle slip suppression method and circuit for a PLL frequency synthesizer according to the present invention;
FIG. 2 is a schematic diagram of a cycle slip detector incorporating a PFD of the present invention;
FIG. 3 is a schematic diagram of the charge pump circuit of the present invention;
fig. 4 is a timing diagram of a cycle slip suppression circuit for a PLL frequency synthesizer of the present invention.
Detailed Description
The charge pump type phase locked loop frequency synthesizer generally includes a Phase Frequency Detector (PFD)10, a charge pump 12, a loop filter 13, a voltage controlled oscillator 14 and a frequency divider 15. The input end of the PFD is Fref and Fdiv respectively, the output end is UP and DN respectively, the PFD compares the frequency and the phase of the input reference signal Fref and the feedback signal Fdiv, then outputs two paths of signals of UP and DN, selects different charging and discharging current values CPout and transmits the charging and discharging current values to the loop filter, the loop filter generates direct current voltage after low-pass filtering according to the charging and discharging current values CPout output by the charge pump and transmits the direct current voltage to the voltage-controlled oscillator, and the voltage-controlled oscillator generates corresponding output frequency to the frequency divider according to the direct current voltage transmitted by the loop filter; the frequency divider divides the output frequency of the voltage-controlled oscillator and feeds the frequency back to the input end Fdiv of the PFD to form a loop.
The invention provides a cycle slip suppression circuit for a PLL frequency synthesizer, wherein input ends Fref and Fdiv and output ends UP and DN of a PFD are connected to a cycle slip detector 111, the cycle slip is detected by the cycle slip detector, the cycle slip frequency is flexibly controlled according to the circuit requirement, the charge pump current is turned on or turned off according to the limited cycle slip frequency, the linear range of the PFD is expanded, and the locking of a phase-locked loop is accelerated. The following describes in detail embodiments of the present invention with reference to the drawings and examples.
As shown in fig. 1, the cycle slip suppression circuit for PLL frequency synthesizer of the present invention comprises a cycle slip detector 111, a frequency selector 112, a cycle slip count controller 110, and a decoder 113, wherein:
the cycle slip detector 111 detects the phase difference between the reference signal Fref and the feedback signal Fdiv according to the input reference signal Fref and the feedback signal Fdiv of the PLL frequency synthesizer, and the first output signal UP and the second output signal DN of the phase frequency detector PFD of the PLL frequency synthesizer, and generates an advanced detection pulse signal U _ CS to output to the frequency selector 112 and the cycle slip counting controller when the phase difference of the reference signal Fref advanced relative to the feedback signal Fdiv exceeds the phase detection range of the PFD; when the phase difference of the reference signal Fref lagging the feedback signal Fdiv exceeds the phase discrimination range of the phase frequency discriminator PFD, a lagging detection pulse signal D _ CS is generated and output to the frequency selector 112, and one pulse in the leading detection pulse signal U _ CS and the lagging detection pulse signal D _ CS represents one cycle slip; the phase detection ranges of the different types of PFDs are different, for example, the phase detection range of the SR flip-flop type PFD is ± pi, and the phase detection range of the D flip-flop type PFD is ± 2 pi;
a frequency selector 112 for setting the leading detection pulse signal U _ CS as the cycle slip pulse signal Fs when the reference signal Fref leads the feedback signal Fdiv; when the reference signal Fref lags behind the feedback signal Fdiv, taking the lagging detection pulse signal D _ CS as the cycle slip pulse signal Fs; outputting the cycle slip pulse signal Fs to a cycle slip counting controller;
the cycle slip counting controller accumulates the number of the received cycle slip pulse signals Fs within a certain range when receiving one cycle slip pulse signal Fs when the lead detection pulse signal U _ CS is 1, and accumulates the number of the received cycle slip pulse signals Fs within a certain range when receiving one cycle slip pulse signal Fs when the lead detection pulse signal U _ CS is 0 to obtain a decoder control word and outputs the decoder control word to the decoder;
the decoder 113 decodes the decoder control word to obtain a current control signal of the charge pump, and controls the charge pump current of the PLL frequency synthesizer to be turned on or off, thereby accelerating the locking of the PLL frequency synthesizer.
As shown in fig. 2, the cycle slip detector 111 includes a first not gate INV0, a second not gate INV1, a third not gate INV2, a fourth not gate INV3, a fifth not gate INV4, a first D flip-flop DF2, a second D flip-flop DF3, a third D flip-flop DF4, a third D flip-flop DF4, a first and gate AD0, a second and gate AD2, a third and gate AD3, a first delay unit delay2, a first nor gate NR0, a second nor gate NR 1; a first output signal UP of a phase detector PFD of the PLL frequency synthesizer is connected to an input of a first not gate INV1, a second output signal DN of the PFD is connected to an input of a second not gate INV2, an output of the second not gate INV2 and a first output signal UP of the PFD are connected to an input of a second nand gate AD2, an output of the second nand gate AD2 is connected to a D of a second D flip-flop DF3 and an input of a second nor gate NR1, another input of the second nor gate NR1 is connected to an output of a fifth not gate INV4, an input of the fifth not gate INV4 is connected to a Q of the second D flip-flop DF3 and a D of a third D flip-flop DF4, an RN of the second D flip-flop DF3 is connected to an output of a third and gate AD3, a CK of a second D flip-flop DF3 is connected to a CK of a first D flip-flop DF2, while an output of the first D0 is connected to an and an output of an and a gate DF 92 is connected to a sixth input of a gate fcv for detecting a pulse signal fvq, a delay signal 5, an output end of the sixth not gate INV5 is connected to one input end of the third and gate AD3, the other input end of the third and gate AD3 is connected to high level, a D end of the first D flip-flop DF2 is connected to the output end of INV1 and one input end of the first nor gate NR0, a reset end RN of the first D flip-flop DF2 is connected to high level, the other input end of the first nor gate NR0 is connected to the output end of the fourth not gate INV3, an input end of the fourth not gate INV3 is connected to the Q end of the first D flip-flop DF2, the Q end of the first D flip-flop DF2 is represented as a detection leading pulse signal U _ CS, the input end of the INV0 is connected to Fref, an output end of the first not gate INV0 is connected to the input end of the first delay unit delay2 and one input end of the first and gate AD0, the other input end of the first and gate AD0 is connected to the output end of the first delay unit delay2, an output of the first nor gate NR0 is fed back to a PLL output of the PLL data phase detector corresponding to the first output end of the PLL, the output of the second nor gate NR1 is fed back to the other data terminal of the phase detector PFD of the PLL frequency synthesizer corresponding to the second output signal DN.
Preferably, the third and gate AD3 is connected to a high level and replaced by an externally input enable signal EN _ CS, and the reset terminal of the first D flip-flop DF2 is also connected to the externally input enable signal EN _ CS.
The frequency selector 112 is a two-input or gate, whose input terminals are the lagging detection pulse signal D _ CS and the leading detection pulse signal U _ CS, and output terminal is the cycle slip pulse signal Fs.
When the cycle slip detector generates and outputs the leading detection pulse signal U _ CS, the lagging detection pulse signal D _ CS is 0, so that U _ CS can be directly output to the cycle slip counting controller; when the cycle slip detector generates the lagging detection pulse signal D _ CS, the leading detection pulse signal U _ CS is 0, so that D _ CS can be directly output to the cycle slip counting controller, and the selection of the output frequency is realized.
As shown in fig. 3, the charge pump of the PLL frequency synthesizer includes, in addition to a default charge pump circuit, an additional X charge pump circuits, each charge pump circuit includes a first current source and a second current source, wherein one end of the first current source is connected in series with the second current source, the other end of the first current source is connected to a power VCC through a first charge-discharge switch, the other end of the second current source is grounded through a second charge-discharge switch, connection points between the first current source and the second current source of all the charge pump circuits are connected together to serve as an output signal CPout of the charge pump, current control signals of the default charge pump circuit are UP and DN, the additional X charge pump current control signals include a first switch control signal UP _ B [ X:1] and a second switch control signal DN _ B [ X:1], and the first charge-discharge switches and the second charge-discharge switches of all the charge pump circuits include a first switch control signal UP _ B _ X _ 1 X is the number of charge pump circuits and X is controlled by [ X:1] and a second switch control signal DN _ B [ X:1] respectively. As an example of the present invention, the default current in the charge pump (12) is set to 0.5 × Icp and one of the configurable currents is set to Icp, so that under the control of the first and second switch control signals UP _ B [7:1] and DN _ B [7:1], respectively, the additional charge pump output currents may have different values for Icp, 2 × Icp, 3 × Icp, …, 7 × Icp.
The cycle slip counting controller comprises a cycle slip number controller, i + 1D triggers and an adder. The cycle slip number controller outputs multi-bit wide data T [ i:0], each bit of data line in the multi-bit wide data T [ i:0] is T [ i ], i is 0-i, and the data line is connected with data ends D0, D1, … and Di of the ith D trigger; the output ends Q0, Q1, … and Qi of the i + 1D triggers form multi-bit wide data A [ i:0], the data are input to the adder, and the multi-bit wide data S [ i:0] and the multi-bit wide data A [ i:0] output by the adder are simultaneously fed back to the input of the cycle slip number controller to form a control loop. Wherein:
the cycle slip number controller receives a result Si: 0 output by the adder and a result ai: 0 output by the D trigger, performs logic operation on the advanced detection pulse signal U _ CS and the advanced detection pulse signal U _ CS, and sends the Si: 0 to the i + 1D triggers when the Si: 0 is smaller than X; otherwise, sending X to the i + 1D triggers;
the i + 1D triggers synchronously latch and output the output result T [ i:0] of the cycle number controller and send the multi-bit wide data A [ i:0] obtained by latching to the adder;
an adder receiving the multi-bit wide data A [ i:0]]When the lead detection pulse signal U _ CS is 1, the multi-bit wide data A [ i:0] is inputted every time one cycle slip pulse signal Fs pulse is received]Plus 1, when the lead detection pulse signal U _ CS is 0, every time a cycle slip pulse signal Fs pulse is received, the multi-bit wide data A [ i:0]Subtracting 1; the result is S [ i:0]Fed back to the input of the cycle number controller. The i +1 bit adder can be controlled by U _ CS under 1-2i+1Within range of realizationSuccessive additions or subtractions, the adder usually being able to add successively from 1 to 2i+1And then repeating the operation, or from 2i+1Repeating the subtraction to 1, obviously if the circuitry does not need to add or subtract 2i+1Second, time costs are increased and inflexibility is not achieved.
By combining the outputs of the adders Si: 0]And input A [ i:0]Simultaneously feeds back the input of the cycle slip number controller, and can realize the control of 1-X (X is less than or equal to 2) under the control of U _ CSi+1) Accumulation in the range or from 2i+1To 2i+1-a subtraction in the range of X, the size of X being set according to the actual requirements of the system circuit.
One embodiment of the cycle slip controller illustrated in FIG. 1 is described below. Let i equal to 3, two input multi-bit wide data S [ i:0] of cycle number controller]And multi-bit wide data A [ i:0]Is S3: 0]And A [3:0]The control terminal is U _ CS, and the output terminal is T [3:0]The logical operation expression of the cycle slip number controller is as follows (, and, + or,
non-denoted a 2):
this example controls the number of cycle slips to 7 or less, and when the number of detected cycle slips is greater than 7, the adder will not add up any more, and the analysis is also applicable to the adder subtracting.
Fig. 4 is a cycle slip reduction operating principle simulation, taking different reference frequencies Fref and feedback frequencies Fdiv as examples: fref and Fdiv are two input frequencies of the PFD, when the frequency is 0-40 us, the period of Fref and Fdiv is 100ns, at the moment, U _ C, D _ C is 0, and A [3:0] is 0000; when the frequency is 40 us-80 us, the period of Fref and Fdiv is 100ns and 102ns respectively (namely Fref > Fdiv), at this time, U _ C generates counting pulse, the adder in the circuit works to make A [3:0] from 0000 to 0111; when the frequency of Fref and Fdiv is 104ns and 102ns respectively (i.e. Fref < Fdiv) at 80 us-120 us, D _ C generates counting pulse, the subtracter in the circuit works to make A3: 0 from 1111 to 1000. That is, when the frequency Fref is continuously higher than Fdiv and every time one cycle is detected (cycle slip occurs), 7 switches for controlling the charge pump are sequentially turned on. When the frequency Fdiv is continuously higher than Fref and every time one more cycle is detected (cycle slip occurs), 7 switches for controlling the charge pump are turned off in sequence. As the frequencies of Fdiv and Fref are detected to be approaching gradually, the additional charge pump units are turned off one by one until all additional charge pump units have been disabled and the frequency has stabilized at the initial loop filter bandwidth.
It should be noted that the above mentioned embodiments are only preferred embodiments of the present invention, and it is obvious to those skilled in the art that several modifications and derivations can be made without departing from the technical principle of the present invention, and these modifications and derivations should be regarded as the protection scope of the present invention.
Parts of the specification which are not described in detail are within the common general knowledge of a person skilled in the art.
Claims (6)
1. A cycle slip suppression circuit for a PLL frequency synthesizer, comprising a cycle slip detector (111), a frequency selector (112), a cycle slip count controller (110), a decoder (113), wherein:
a cycle slip detector (111) which detects the phase difference between the reference signal Fref and the feedback signal Fdiv according to the input reference signal Fref and the feedback signal Fdiv of the PLL frequency synthesizer, the first output signal UP and the second output signal DN of the phase frequency detector PFD of the PLL frequency synthesizer, and generates an advanced detection pulse signal U _ CS to output to the frequency selector (112) and the cycle slip counting controller (110) when the phase difference of the reference signal Fref advanced from the feedback signal Fdiv exceeds the phase detection range of the PFD; when the phase difference of the reference signal Fref lagging the feedback signal Fdiv exceeds the phase discrimination range of the phase frequency discriminator PFD, a lagging detection pulse signal D _ CS is generated and output to a frequency selector (112), and one pulse in the leading detection pulse signal U _ CS and the lagging detection pulse signal D _ CS represents one cycle slip; the phase detection ranges of different types of PFDs are different, the phase detection range of the SR trigger type PFD is +/-pi, and the phase detection range of the D trigger type PFD is +/-2 pi;
a frequency selector (112) for setting the leading detection pulse signal U _ CS as the cycle slip pulse signal Fs when the reference signal Fref leads the feedback signal Fdiv; when the reference signal Fref lags behind the feedback signal Fdiv, taking the lagging detection pulse signal D _ CS as the cycle slip pulse signal Fs; outputting the cycle slip pulse signal Fs to a cycle slip counting controller (110);
a cycle slip count controller (110) which accumulates the number of the received cycle slip pulse signals Fs within a preset range every time one cycle slip pulse signal Fs is received when the lead detection pulse signal U _ CS is 1, and accumulates the number of the received cycle slip pulse signals Fs within the preset range every time one cycle slip pulse signal Fs is received when the lead detection pulse signal U _ CS is 0 to obtain a decoder control word, and outputs the decoder control word to the decoder;
and a decoder (113) for decoding the decoder control word to obtain a current control signal of the charge pump to control the charge pump current of the PLL frequency synthesizer to be turned on or off, thereby accelerating the locking of the PLL frequency synthesizer.
2. A cycle slip suppression circuit for a PLL frequency synthesizer according to claim 1, wherein: the cycle slip detector (111) comprises a first not gate INV0, a second not gate INV1, a third not gate INV2, a fourth not gate INV3, a fifth not gate INV4, a first D flip-flop DF2, a second D flip-flop DF3, a third D flip-flop DF4, a first AND gate AD0, a second AND gate AD2, a third AND gate AD3, a first delay unit delay2, a first NOR gate NR0, and a second NOR gate NR 1; a first output signal UP of a phase detector PFD of the PLL frequency synthesizer is connected with an input of a second not gate INV1, a second output signal DN of the PFD is connected with an input of a third not gate INV2, an output of the third not gate INV2 and a first output signal UP of the PFD are connected with an input end of a second NAND gate AD2, an output end of the second NAND gate AD2 is connected with a D end of a second D flip-flop DF3 and an input end of a second NOR gate NR1, the other input end of the second NOR gate NR1 is connected with an output end of a fifth not gate INV4, an input end of the fifth not gate INV4 is connected with a Q end of a second D flip-flop DF3 and a D end of a third D flip-flop DF4, an RN end of the second D flip-flop DF3 is connected with an output end of a third AND gate AD3, a CK end of the second D flip-flop DF3 is connected with a CK end of a first D flip-flop DF2, while an output end of the first D0 is connected with an output end of the third D flip-gate DF4, a D flip-flop is connected with a Q signal Fdiv, and a delay detection signal Fd _ Fd 7 is recorded as a delay signal Fdiv, an input end of a sixth not gate INV5 is connected, an output end of the sixth not gate INV5 is connected to one input end of the third and gate AD3, the other input end of the third and gate AD3 is connected to a high level, a D end of the first D flip-flop DF2 is connected to the output end of INV1 and one input end of the first nor gate NR0, a reset end RN of the first D flip-flop DF2 is connected to a high level, the other input end of the first nor gate NR0 is connected to the output end of the fourth not gate INV3, an input end of the fourth not gate INV3 is connected to a Q end of the first D flip-flop DF2, a Q end of the first D flip-flop DF2 is marked as a leading detection pulse signal U _ CS, an input end of the first not gate INV0 is connected to Fref, an output end of the first not gate INV0 is connected to an input end of the first delay unit delay2 and an input end of the first and gate AD0, the other input end of the first AD0 is connected to an output end of the first delay unit 2, and a feedback frequency detector PLL NR0, the output of the second nor gate NR1 is fed back to the other data terminal of the phase detector PFD of the PLL frequency synthesizer corresponding to the second output signal DN.
3. A cycle slip suppression circuit for a PLL frequency synthesizer according to claim 2, wherein: the third and gate AD3 is connected to a high level and replaced by an externally input enable signal EN _ CS, and the reset terminal of the first D flip-flop DF2 is also connected to the externally input enable signal EN _ CS.
4. A cycle slip suppression circuit for a PLL frequency synthesizer according to claim 1, wherein: the frequency selector (112) is an OR gate with two input ends, the input ends are a lag detection pulse signal D _ CS and a lead detection pulse signal U _ CS, and the output end is a cycle slip pulse signal Fs;
when the cycle slip detector generates and outputs the leading detection pulse signal U _ CS, the lagging detection pulse signal D _ CS is 0, so that U _ CS can be directly output to the cycle slip counting controller; when the cycle slip detector generates the lagging detection pulse signal D _ CS, the leading detection pulse signal U _ CS is 0, so that D _ CS can be directly output to the cycle slip counting controller, and the selection of the output frequency is realized.
5. A cycle slip suppression circuit for a PLL frequency synthesizer according to claim 1, wherein: the charge pump of the PLL frequency synthesizer is composed of an additional X-path charge pump circuit besides a default path of charge pump circuit, each path of charge pump circuit comprises a first current source and a second current source, wherein one end of the first current source is connected with the second current source in series, the other end of the first current source is connected with a power supply VCC through a first charge-discharge switch, the other end of the second current source is grounded through a second charge-discharge switch, and connection points between the first current source and the second current source of all the charge pump circuits are connected together to serve as an output signal CPout of the charge pump; the default current control signals of one path of charge pump circuit are UP and DN, the additional X paths of charge pump current control signals comprise a first switch control signal UP _ B [ X:1] and a second switch control signal DN _ B [ X:1], the first charge-discharge switches and the second charge-discharge switches of all the additional X paths of charge pump circuits are respectively controlled by the first switch control signal UP _ B [ X:1] and the second switch control signal DN _ B [ X:1], and X is the number of the additional charge pump circuits.
6. The cycle slip suppression circuit for a PLL frequency synthesizer of claim 5, wherein: the cycle slip counting controller comprises a cycle slip number controller, i + 1D triggers and an adder, wherein:
the cycle slip number controller receives a result Si: 0 output by the adder and a result AI: 0 output by the D trigger, performs logic operation on the advanced detection pulse signal U _ CS and the result SI: 0 output by the adder, and sends SI: 0 to i + 1D triggers when SI: 0 is smaller than X; otherwise, sending X to the i + 1D triggers;
the i + 1D triggers synchronously latch and output the output result T [ i:0] of the cycle number controller and send the multi-bit wide data A [ i:0] obtained by latching to the adder;
an adder for receiving the multi-bit wide data A [ i:0], adding 1 to the multi-bit wide data A [ i:0] every time a cycle slip pulse signal Fs pulse is received when the leading detection pulse signal U _ CS is 1, and subtracting 1 from the multi-bit wide data A [ i:0] every time a cycle slip pulse signal Fs pulse is received when the leading detection pulse signal U _ CS is 0; the result Si: 0 is fed back to the input of the cycle number controller.
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| CN109639269B (en) * | 2018-12-11 | 2023-08-01 | 海信视像科技股份有限公司 | Quick locking phase frequency detector and phase-locked loop |
| CN111190200B (en) * | 2019-12-09 | 2022-05-13 | 北京时代民芯科技有限公司 | Single-frequency cycle slip detection and restoration method in dynamic environment |
| CN112953529B (en) * | 2019-12-10 | 2022-08-19 | 上海交通大学 | Linear interval expanding method for rapid frequency locking and cycle slip elimination |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6624705B1 (en) * | 2002-04-04 | 2003-09-23 | National Semiconductor Corporation | Control circuit for phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock |
| US7183863B1 (en) * | 1998-10-20 | 2007-02-27 | Lucent Technologies Inc. | Self-initializing frequency detector |
| CN101588177A (en) * | 2009-06-22 | 2009-11-25 | 中国科学院微电子研究所 | Digital locking indictor, phase lock loop frequency synthesizer and wireless transceiver |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of performing locking fast |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN103746689A (en) * | 2013-12-19 | 2014-04-23 | 北京时代民芯科技有限公司 | Lock detector used for PLL frequency synthesizer |
| CN105306048A (en) * | 2015-11-11 | 2016-02-03 | 成都振芯科技股份有限公司 | Phase-locked loop circuit used for spurious suppression and spurious suppression method thereof |
| CN105515571A (en) * | 2015-12-02 | 2016-04-20 | 上海兆芯集成电路有限公司 | Delay lock loop |
| CN106961278A (en) * | 2016-01-08 | 2017-07-18 | 三星显示有限公司 | The display of phaselocked loop including the phaselocked loop and the method for operating the phaselocked loop |
-
2017
- 2017-12-19 CN CN201711373561.6A patent/CN108768393B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183863B1 (en) * | 1998-10-20 | 2007-02-27 | Lucent Technologies Inc. | Self-initializing frequency detector |
| US6624705B1 (en) * | 2002-04-04 | 2003-09-23 | National Semiconductor Corporation | Control circuit for phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock |
| CN101588177A (en) * | 2009-06-22 | 2009-11-25 | 中国科学院微电子研究所 | Digital locking indictor, phase lock loop frequency synthesizer and wireless transceiver |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of performing locking fast |
| CN103746689A (en) * | 2013-12-19 | 2014-04-23 | 北京时代民芯科技有限公司 | Lock detector used for PLL frequency synthesizer |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN105306048A (en) * | 2015-11-11 | 2016-02-03 | 成都振芯科技股份有限公司 | Phase-locked loop circuit used for spurious suppression and spurious suppression method thereof |
| CN105515571A (en) * | 2015-12-02 | 2016-04-20 | 上海兆芯集成电路有限公司 | Delay lock loop |
| CN106961278A (en) * | 2016-01-08 | 2017-07-18 | 三星显示有限公司 | The display of phaselocked loop including the phaselocked loop and the method for operating the phaselocked loop |
Non-Patent Citations (2)
| Title |
|---|
| "Real Time Cycle Slip Detection and Correction for APSK Modulation";Uri Beitler等;《IEEE TRANSACTIONS ON COMMUNICATIONS》;20140228;第62卷(第2期);736-746 * |
| "高灵敏度导航信号接收技术与信道编码设计研究";王建辉;《中国博士学位论文全文数据库 信息科技辑》;20170215;I136-82 * |
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