CN109639269B - Quick locking phase frequency detector and phase-locked loop - Google Patents
Quick locking phase frequency detector and phase-locked loop Download PDFInfo
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Abstract
The application provides a fast locking phase frequency detector and a phase-locked loop, which comprise a first trigger, a second trigger, a third trigger, a fourth trigger, a first OR gate and a second OR gate; the data input ends of the first trigger and the second trigger are respectively connected with a high level; clock ends of the first trigger and the second trigger are respectively connected with a reference clock and a feedback clock; the data input end of the third trigger is connected with the data output end of the first trigger, and the clock end of the third trigger is connected with the reference clock; the data input end of the fourth trigger is connected with the data output end of the second trigger, and the clock end of the fourth trigger is connected with the feedback clock; the first input end and the second input end of the first OR gate are respectively connected with the data output end of the first trigger and the data output end of the third trigger; the first input end and the second input end of the second OR gate are respectively connected with the data output end of the second trigger and the data output end of the fourth trigger. The locking speed of the phase-locked loop is increased, and the locking time is shortened.
Description
Technical Field
The application relates to the technical field of radio frequency communication equipment, in particular to a fast locking phase frequency detector and a phase-locked loop.
Background
A conventional phase-locked loop typically includes a phase frequency detector that compares the phases of two input signals, a charge pump, a loop filter, a voltage controlled oscillator, and a feedback divider. The performance of the phase-locked loop is closely related to the performance of the phase-frequency detector, and the phase-frequency detector is responsible for detecting the phase difference between the reference clock and the feedback clock in the use of the phase-locked loop. Specifically, when the reference clock leads the feedback clock, the output of the phase frequency detector outputs a high-level signal with corresponding pulse width according to the phase difference between the reference clock and the feedback clock to drive a charge pump of a later stage to open a charge switch to charge a loop filter, so that the phase difference between the reference clock and the feedback clock is reduced, and finally the phase-locked loop is locked to the target frequency; when the reference clock is behind the phase of the feedback clock, the high-level pulse width output by the phase frequency detector is in direct proportion to the phase difference between the reference clock and the feedback clock, the post charge pump is driven to open the discharge switch to discharge the loop filter, the phase of the feedback clock is driven to approach the phase of the reference clock, and finally the loop is locked to the target frequency.
Fig. 1 is a schematic circuit diagram of a typical phase frequency detector. As shown in fig. 1, the phase frequency detector comprises two flip-flops, the clock ends of the two flip-flops are respectively connected with a reference clock and a feedback clock, and the data input ends of the two flip-flops are respectively connected with a fixed high level 1. If the reference clock and the feedback clock input by the clock ends of the two triggers are not aligned, the charge switch and the discharge switch of the charge pump are controlled according to the output pulse of the output ends of the two triggers respectively, namely the phase frequency discriminator can open the charge pump switch to charge/discharge the filter capacitor so as to change the control voltage until the other clock edge comes, the charge/discharge of the filter only occurs in a period of the reference period, and the control voltage is kept unchanged in the rest period.
The high level pulse width of the phase frequency detector output in fig. 1 is proportional to the phase difference between the reference clock and the feedback clock. When the difference between the frequency of the phase-locked loop and the target set frequency is large, a relatively long time is required to pull the frequency of the phase-locked loop closer to the target set frequency.
Disclosure of Invention
The application provides a quick locking phase frequency detector and a phase-locked loop, which shorten the locking time of the phase-locked loop when the frequency difference between the frequency of the phase-locked loop and the target set frequency is larger, and quicken the locking speed of the phase-locked loop.
In a first aspect, the present application provides a fast lock phase frequency detector, including a first trigger, a second trigger, a third trigger, a fourth trigger, a first or gate, and a second or gate; wherein,,
the data input end of the first trigger and the data input end of the second trigger are respectively connected with a high level 1; the clock end of the first trigger is connected with a reference clock, and the clock end of the second trigger is connected with a feedback clock;
the data input end of the third trigger is connected with the data output end of the first trigger, and the clock end of the third trigger is connected with a reference clock;
the data input end of the fourth trigger is connected with the data output end of the second trigger, and the clock end of the fourth trigger is connected with a feedback clock;
the first input end of the first OR gate is connected with the data output end of the first trigger, and the second input end of the first OR gate is connected with the data output end of the third trigger;
the first input end of the second OR gate is connected with the data output end of the second trigger, and the second input end of the second OR gate is connected with the data output end of the fourth trigger.
In a second aspect, the present application provides a fast lock phase frequency detector, including a first trigger and a second trigger, and further including a third trigger, a fourth trigger, a first or gate, and a second or gate; wherein,,
the first flip-flop has a data input configured to receive a high level and a clock input configured to receive a reference signal, and is configured to generate a first output signal based on the reference signal;
the second flip-flop having a data input configured to receive a high level and a clock input configured to receive a feedback signal, and the second flip-flop being configured to generate a second output signal based on the feedback signal;
the third flip-flop having a data input configured to receive the first output signal and a clock input configured to receive the reference signal, and the third flip-flop being configured to generate a third output signal based on the reference signal and the first output signal;
the fourth flip-flop having a data input configured to receive the second output signal and a clock input configured to receive the feedback signal, and the fourth flip-flop being configured to generate a fourth output signal based on the feedback signal and the second output signal;
the first or gate is configured to perform a logical or operation on the first output signal and the third output signal;
the second or gate is configured to perform a logical or operation on the second output signal and the fourth output signal.
In a third aspect, the present application provides a phase locked loop, where the phase locked loop includes a phase frequency detector, and the phase frequency detector is the fast lock phase frequency detector.
The application provides a quick locking phase frequency detector and phase-locked loop, first trigger, second trigger, third trigger, fourth trigger, first OR gate and second OR gate. The first trigger and the second trigger realize one-time sampling, and the third trigger, the fourth trigger, the first or gate and the second or gate combine one-time sampling to perform secondary sampling. The charge pump is controlled to charge or discharge in the whole clock period through the secondary sampling logic, so that the frequency of the phase-locked loop can be rapidly driven to approach the target set frequency, and the locking speed of the phase-locked loop is increased. And the circuit structure that this application provided locks fast phase frequency detector, design realization is simple, easily realizes, has avoided complicated quick locking circuit to the interference behind the loop locking, leads to locking frequency unstable or brings great phase noise.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic circuit diagram of a typical phase frequency detector in the prior art;
fig. 2 is a schematic circuit structure diagram of a fast lock phase frequency detector according to an embodiment of the present application;
fig. 3 is a state switching diagram of the phase frequency detector shown in fig. 1;
fig. 4 is a state switching diagram of the fast lock phase frequency detector according to the embodiment of the present application;
fig. 5 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 2 is a schematic circuit structure diagram of a fast lock phase frequency detector according to an embodiment of the present application. As shown in fig. 2, the fast lock phase frequency detector provided in the embodiment of the present application includes a first trigger 1, a second trigger 2, a third trigger 3, a fourth trigger 4, a first or gate 5, and a second or gate 6.
The data input end of the first trigger 1 and the data input end of the second trigger 2 are respectively connected with a high level 1; the clock end of the first trigger 1 is connected with a reference clock, and the clock end of the second trigger 2 is connected with a feedback clock;
the data input end of the third trigger 3 is connected with the data output end of the first trigger 1, and the clock end of the third trigger 3 is connected with a reference clock;
the data input end of the fourth trigger 4 is connected with the data output end of the second trigger 2, and the clock end of the fourth trigger 4 is connected with a feedback clock;
a first input end of the first or gate 5 is connected with a data output end of the first trigger 1, and a second input end of the first or gate 5 is connected with a data output end of the third trigger 1;
the first input end of the second or gate 6 is connected to the data output end of the second flip-flop 2, and the second input end of the second or gate 6 is connected to the data output end of the fourth flip-flop 4.
In the embodiment of the present application, the first flip-flop 1, the second flip-flop 2, the third flip-flop 3, and the fourth flip-flop 4 are D-type flip-flops. The data input end of the first trigger 1 and the data input end of the second trigger 2 are respectively connected with a high level 1; the clock end of the first trigger 1 is connected with a reference clock and is used for receiving a reference clock signal; the clock end of the second trigger 2 is connected with a feedback clock and is used for receiving a feedback clock signal; the data output terminal of the first flip-flop 1 outputs up_linear and the data output terminal of the second flip-flop 2 outputs dn_linear. For example, when the clock end of the first flip-flop 1 receives the rising edge of the reference clock, the up_linear output by the data output end of the first flip-flop 1 is a high level pulse; when the clock end of the second flip-flop 2 receives the rising edge of the feedback clock, dn_linear outputted from the data output end of the second flip-flop 2 is a high level pulse.
The clock end of the third trigger 3 is connected with a reference clock, and the clock end of the fourth trigger 4 is connected with a feedback clock; the data input end of the third trigger 3 is used for receiving the data output end of the first trigger 1 and outputting up_linear; the data input end of the fourth trigger 4 is connected with the data output end of the second trigger 2 and is used for receiving dn_linear output by the second trigger 2; the up_boost output by the data output terminal of the third flip-flop 3, and the dn_boost output by the data output terminal of the fourth flip-flop 4. The up_linear output by the first trigger 1 and the up_boost output by the third trigger 3 are subjected to logical OR operation through the first OR gate 5, and up is output; and the second OR gate 6 carries out logical OR operation on the dn_linear output by the second trigger 2 and the dn_boost output by the fourth trigger 4, and outputs dn. Thus, up and dn are the output signals of the fast phase frequency detector.
Under certain approximation conditions, we can consider the phase frequency detector and charge pump phase locked loop as a continuous linear system, and the open loop transfer function can be expressed as:
in the above formula, H (S) open represents an open loop transfer function, icp represents a current of the charge pump, F (S) represents a transfer function of the loop filter, kvco is a gain of the voltage controlled oscillator, and S is a constant. From the above formula, the phase-locked loop can be approximated as a linear operation mode in the whole locking process, the bandwidth/gain is kept constant, and the locking time of the phase-locked loop is mainly dependent on the loop bandwidth and the frequency difference between the current frequency and the target set frequency of the phase-locked loop.
Since the locking time of the phase-locked loop is related to the loop bandwidth and the frequency range to be locked, the loop bandwidth is determined in advance in the early stage of the design of the phase-locked loop, and a proper value is selected according to the continuity of the sampling system, the phase noise performance and the like, so that the locked frequency range is closely related to the locking time of the phase-locked loop. The narrower the frequency range of the lock, the shorter the lock time of the phase locked loop and vice versa.
The output signals of the phase frequency detector shown in fig. 1 are recorded as up and dn, and the output states of the phase frequency detector are defined according to the control states of the charge pump:
up=0, dn=0, when the charge pump CP is in a high resistance state (both charge and discharge switches are off);
up=1, dn=0: the feedback clock is delayed from the reference clock, and the charge pump charging switch is turned on;
up=0, dn=1: the feedback clock leads the reference clock and the charge pump discharge switch is turned on.
As shown in fig. 3, the transition between its output states is:
up=0, dn=0: in the state, when the edge of the feedback clock div arrives, the state up=0 and dn=1 is entered; the edge of the reference clock ref comes, and then the state up=1 and dn=0 is entered;
up=0, dn=1: in the state, the edge of the feedback clock div arrives, and the state is kept unchanged; the edge of the reference clock ref comes, then the state up=0 and dn=0 is returned;
up=1, dn=0: in this state, the feedback clock div edge comes, then the state up=0, dn=0 is returned, the reference clock ref edge comes, and the state remains unchanged.
Thus, the phase frequency detector shown in fig. 1 turns on the charge pump switch to charge or discharge the filter capacitance to change the control voltage until another clock edge comes, i.e., the filter charge or discharge occurs only for a period of the reference period. And because the loop parameters are fixed, the loop gain and the bandwidth are constant, and when the frequency of the phase-locked loop and the target set frequency are large, a long time is required to pull the frequency of the phase-locked loop to the vicinity of the target set frequency.
As shown in fig. 2, the outputs up_linear and dn_linear of the conventional phase-frequency detector are sampled twice, and the sampled outputs up_boost and dn_boost are logically or-operated with the outputs up_linear and dn_linear of the conventional phase-frequency detector to serve as the output signals up and dn of the fast phase-frequency detector.
When the frequency difference between the reference clock ref and the feedback clock div is relatively large, that is, the frequency difference between the reference clock ref and the feedback clock div is greater than 10%, the up_linear and the dn_linear are taken by the secondary sampling logic, the up_boost and the dn_boost of the secondary sampling logic are high, and since the up and the dn (up=up_linear+up_boost, dn=dn_linear+dn_boost) of the fast frequency phase detector are forced to be 1 by the high level of the output of the secondary sampling logic, the up_linear and the dn_linear of the traditional frequency phase detector are shielded at this time, and the charge and discharge of the later charge pump are continued until the up_linear and the dn_linear are sampled at the following clock edge by the secondary sampling logic, and the fast frequency phase detector returns to the linear mode. From the above description, after the up_linear and dn_linear are adopted as high levels by the subsampling logic, it is judged that the frequency difference between the reference clock ref and the feedback clock div is relatively large, the fast phase frequency detector enters a nonlinear working mode, the gain of the fast phase frequency detector is increased, the frequency difference between the reference clock ref and the feedback clock div is quickly pulled up, and the purpose of fast locking is achieved.
When the frequency difference between the reference signal ref and the feedback signal div is relatively small, the outputs up_boost and dn_boost of the subsampling logic are always 0, so that the subsampling logic can be omitted, and the fast phase frequency detector enters a linear working mode. If the reference signal ref leads the feedback signal div, after the ref signal arrives, the output of up_linear is 1, the output up of the fast phase frequency detector is also 1, and the charge pump of the later stage is driven to charge the loop filter so as to drive the feedback signal div to catch up with the reference signal ref.
Therefore, the fast phase frequency detector provided by the embodiment of the application is completely judged and switched by the circuit per se with respect to the switching of the linear mode and the nonlinear mode, extra control expenditure is not needed, and the phase-locked loop loss of lock caused by manual intervention is avoided.
Fig. 4 is a state switching diagram of the fast lock phase frequency detector according to the embodiment of the present application. As shown in fig. 4, after the fast lock phase frequency detector provided in the embodiment of the present application adds the subsampling logic, the state of the fast lock phase frequency detector is increased from 3 states in the conventional phase frequency detector shown in fig. 1 to the 7-medium state (stage 0-stage 6) in fig. 4.
stage0 is defined as a high resistance state, where the charge pump circuit charge and discharge switches are turned off, and the output of the charge pump is in the high resistance state. After the edge of the reference clock ref arrives first, the state is switched from stage0 to stage1, and if the edge of the feedback clock div arrives at stage1, the state is returned to stage0, that is, the phase frequency detector is locked fast to operate in the linear mode. If the edge of the feedback clock div does not arrive at stage1, the subsampling logic starts to work, drives the fast locking phase frequency detector to enter a nonlinear mode, improves the gain of the fast locking phase frequency detector, and shortens the locking time. When the reference clock ref arrives, the state of the fast phase frequency detector is converted from stage1 to stage2, and the up/dn signal is high level in the whole clock period in stage2, so that the charge pump circuit of the later stage is driven to charge or discharge. In order to avoid the unstable loop caused by the excessive gain of the fast lock phase frequency detector, stage2 will switch to stage3 after the edge of the feedback clock div arrives, thereby providing for the fast lock phase frequency detector to leave the nonlinear mode. At stage3, if the next clock edge arrives at reference clock ref, then transition to stage1; if the feedback clock div is the feedback clock div, returning to the high-resistance state stage0; according to the working process, the key point of the proposed fast locking phase frequency detector for accelerating the locking process is that nonlinear states stage2 and stage3 are added after a subsampling logic is introduced, the gain is improved, and the state is switched to stage0 or stage1 in time after the next clock edge comes, so that the instability of a phase-locked loop caused by overlarge gain is avoided.
Further, in this embodiment of the present application, the fast locking phase frequency detector further includes an and gate 7 and a delay unit 8, a first input end of the and gate 7 is connected to a data output end of the first trigger 1, a second input end of the and gate 7 is connected to a data output end of the second trigger 2, an output end of the and gate 7 is connected to an input end of the delay unit 8, and input ends of the delay unit 8 are respectively connected to reset ends of the first trigger 1 and the second trigger 2.
When the values of up_linear and dn_linear are 1 after the arrival of the feedback signal div, the reset signal of the sampling logic is effective after the delay of a certain time by the delay unit, the outputs up_linear and dn_linear of the sampling logic are all reset to 0, and the frequency and phase discrimination process of the current period is finished. The delay unit is mainly used for solving the dead zone problem of the phase-locked loop, and because the up and dn signals drive the switch of the later stage charge pump for a certain time, the up and dn output signals of each period after the delay unit is introduced have the minimum pulse time, so that the charge and discharge switch of the charge pump can be opened.
In the fast lock phase frequency detector provided in the embodiment of the present application, the first trigger 1 and the second trigger 2 implement one sampling, and the third trigger 3, the fourth trigger 4, the first or gate 5 and the second or gate 6 combine one sampling to perform two sampling. The charge pump is controlled to charge or discharge in the whole clock period through the secondary sampling logic, so that the frequency of the phase-locked loop can be rapidly driven to approach the target set frequency, and the locking speed of the phase-locked loop is increased. And the circuit structure that this application provided locks fast phase frequency detector, design realization is simple, easily realizes, has avoided complicated quick locking circuit to the interference behind the loop locking, leads to locking frequency unstable or brings great phase noise.
In the fast lock phase frequency detector provided by the embodiment of the application, a first trigger is provided with a data input end configured for receiving a high level and a clock input end configured for receiving a reference signal, and the first trigger is configured for generating a first output signal based on the reference signal; a second flip-flop having a data input configured to receive a high level and a clock input configured to receive a feedback signal, and configured to generate a second output signal based on the feedback signal; a third flip-flop having a data input configured to receive the first output signal and a clock input configured to receive the reference signal, and configured to generate a third output signal based on the reference signal and the first output signal; a fourth flip-flop having a data input configured to receive the second output signal and a clock input configured to receive the feedback signal, and configured to generate a fourth output signal based on the feedback signal and the second output signal; the first or gate is configured to perform a logical or operation on the first output signal and the third output signal; the second or gate is configured to perform a logical or operation on the second output signal and the fourth output signal.
Further, the fast lock phase frequency detector provided in the embodiment of the present application further includes an and gate and a delay unit, where the and gate is configured to perform a logical sum operation of the first output signal and the second output signal; and the delay unit is configured to receive the output signal of the AND gate and generate a reset signal.
Based on the fast locking phase frequency detector provided by the embodiment of the application, the application also provides a phase-locked loop, as shown in fig. 5, wherein the phase-locked loop comprises the phase frequency detector, and the phase frequency detector is the fast locking phase frequency detector described in the above embodiment.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (3)
1. The fast locking phase frequency detector comprises a first trigger and a second trigger, and is characterized by further comprising a third trigger, a fourth trigger, a first OR gate, a second OR gate, an AND gate and a delay unit; wherein,,
the data input end of the first trigger and the data input end of the second trigger are respectively connected with a high level 1; the clock end of the first trigger is connected with a reference clock, and the clock end of the second trigger is connected with a feedback clock;
the data input end of the third trigger is connected with the data output end of the first trigger, and the clock end of the third trigger is connected with a reference clock;
the data input end of the fourth trigger is connected with the data output end of the second trigger, and the clock end of the fourth trigger is connected with a feedback clock;
the first input end of the first OR gate is connected with the data output end of the first trigger, and the second input end of the first OR gate is connected with the data output end of the third trigger;
the first input end of the second OR gate is connected with the data output end of the second trigger, and the second input end of the second OR gate is connected with the data output end of the fourth trigger;
the first input end of the AND gate is connected with the data output end of the first trigger, the second input end of the AND gate is connected with the data output end of the second trigger, the output end of the AND gate is connected with the input end of the delay unit, the input ends of the delay unit are respectively connected with the reset ends of the first trigger and the second trigger, so that when the feedback signal div arrives, the values of up_linear and dn_linear are 1, the reset signal of the sampling logic is effective after a certain time delay by the delay unit, the output up_linear and dn_linear of the sampling logic are all reset to 0, wherein the data output end of the first trigger outputs up_linear, and the data output end of the second trigger outputs dn_linear.
2. The fast locking phase frequency detector comprises a first trigger and a second trigger, and is characterized by further comprising a third trigger, a fourth trigger, a first OR gate, a second OR gate, an AND gate and a delay unit; wherein,,
the first flip-flop has a data input configured to receive a high level and a clock input configured to receive a reference signal, and is configured to generate a first output signal based on the reference signal;
the second flip-flop having a data input configured to receive a high level and a clock input configured to receive a feedback signal, and the second flip-flop being configured to generate a second output signal based on the feedback signal;
the third flip-flop having a data input configured to receive the first output signal and a clock input configured to receive the reference signal, and the third flip-flop being configured to generate a third output signal based on the reference signal and the first output signal;
the fourth flip-flop having a data input configured to receive the second output signal and a clock input configured to receive the feedback signal, and the fourth flip-flop being configured to generate a fourth output signal based on the feedback signal and the second output signal;
the first or gate is configured to perform a logical or operation on the first output signal and the third output signal;
the second or gate is configured to perform a logical or operation on the second output signal and the fourth output signal;
the AND gate is configured to perform logical sum operation of the first output signal and the second output signal;
the delay unit is configured to receive the output signal of the AND gate and generate a reset signal;
the first input end of the AND gate is connected with the data output end of the first trigger, the second input end of the AND gate is connected with the data output end of the second trigger, the output end of the AND gate is connected with the input end of the delay unit, the input ends of the delay unit are respectively connected with the reset ends of the first trigger and the second trigger, so that when the feedback signal div arrives, the values of up_linear and dn_linear are 1, the reset signal of the sampling logic is effective after a certain time delay by the delay unit, the output up_linear and dn_linear of the sampling logic are all reset to 0, wherein the data output end of the first trigger outputs up_linear, and the data output end of the second trigger outputs dn_linear.
3. A phase locked loop comprising a phase frequency detector, the phase frequency detector being the fast lock phase frequency detector of claim 1 or claim 2.
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| EP2752993B1 (en) * | 2013-01-04 | 2015-03-25 | Nxp B.V. | Phase frequency detector circuit |
| CN108768393B (en) * | 2017-12-19 | 2021-11-09 | 北京时代民芯科技有限公司 | Cycle slip suppression circuit for PLL frequency synthesizer |
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| CN101388666A (en) * | 2008-10-10 | 2009-03-18 | 哈尔滨工业大学 | Non-linear frequency and phase discriminator without phase discriminating blind zone |
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