CN210469272U - Phase-locked accelerating circuit based on level width extraction and phase-locked loop system - Google Patents

Abstract

The utility model discloses a phase-locked accelerating circuit and a phase-locked loop system based on level width extraction, the phase-locked accelerating circuit comprises a level extraction control circuit and a current injection switch module; the control output end of the level extraction control circuit is connected with the current injection control end of the current injection switch module, and meanwhile, the current stepping control end of the current injection switch module and the driving input end of the level extraction control circuit are both connected with the preset control signal output end of the phase frequency detector and used for controlling the current injection switch module to inject charges according to the level width change condition of the output signal of the preset control signal output end until the reference clock signal input by the phase frequency detector is synchronous with the phase of the feedback clock signal. The low-pass filter receives the charge injected by the current injection switch module under the control on-off action of the phase-locking acceleration circuit, so that the charge is quickly injected into the low-pass filter until the charge is close to stability, and meanwhile, the charge is injected step by step to avoid oscillation and shorten the phase-locking time.

Description

Phase-locked accelerating circuit based on level width extraction and phase-locked loop system

Technical Field

The utility model belongs to the technical field of the phase-locked loop, especially, relate to a phase-locked accelerating circuit and phase-locked loop system based on level width draws.

Background

A Phase Locked Loop (PLL) is an important functional system, such as providing clocks of one or more frequency requirements in a system-on-a-chip, generating local oscillator signals in a receiver, maintaining synchronization in a communication system, etc. For these systems, fast locking of the phase-locked loop is always a goal, but is constrained by stability, dynamic response, precision, noise and other factors, and the phase-locking speed is difficult to further increase.

In the phase-locked loop, a frequency discrimination phase discriminator, a charge pump, a low-pass filter, a voltage controlled oscillator and a frequency divider form a feedback loop, a feedback clock signal Ffb of a high-frequency output signal of the voltage controlled oscillator after frequency division and a reference clock signal Fref generated by a crystal oscillator are input into the frequency discrimination phase discriminator, the frequency discrimination phase discriminator compares the phase difference of two input signals to generate an output voltage, the output voltage controls the charge pump to generate a charging or discharging current, the charging or discharging current charges or discharges the low-pass filter to cause the control voltage Vc output by the low-pass filter to increase or decrease, Vc is used as an input signal of the voltage controlled oscillator to adjust the frequency of the output signal of the voltage controlled oscillator, then the output signal of the voltage controlled oscillator is subjected to frequency division by the frequency divider to obtain a feedback clock signal Ffb and is transmitted to the frequency discrimination phase discriminator, and when the phase difference between the reference clock signal Fref and the feedback clock signal Ffb is consistent, the phase locked loop is locked. Thus, by means of the phase locked loop circuit, an output signal Fout may be generated which is frequency and phase locked to a fixed frequency and phase. The reference clock signal Fref and the feedback clock signal Ffb are compared by the phase frequency detector, and the control voltage of the voltage-controlled oscillator is adjusted to change the output frequency until the phase lock is stable, wherein the frequency of the reference clock signal and the output frequency of the voltage-controlled oscillator are equal or in a multiple N relation when the phase lock is stable. However, in this process, the delay time of the loop feedback is long, and the phase-locked time of the phase-locked loop is long.

SUMMERY OF THE UTILITY MODEL

In order to overcome above-mentioned technical defect, the utility model discloses a phase-locked accelerating circuit based on level width draws, this phase-locked accelerating circuit utilizes the reference clock signal of the reflection input of phase frequency detector output and the control signal of feedback clock signal phase relation, the drive level draws the condition that control circuit marching type ground control current injection switch module pours into the electric charge into to low pass filter, until the reference clock signal of phase frequency detector input and feedback clock signal's phase synchronization, when avoiding the control voltage of input voltage controlled oscillator to overshoot, also offset the time delay of feedback loop, reduce phase-locked time.

The utility model provides a following technical scheme: a phase-locked accelerating circuit based on level width extraction is provided, and the phase-locked loop applicable to the phase-locked accelerating circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, wherein the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the frequency divider are sequentially connected to form a feedback loop; the level extraction control circuit is provided with a driving input end, an enabling control end and a control output end; the current injection switch module is provided with a current stepping input control end and a current injection control end; the enabling control end of the level extraction control circuit is connected with an external enabling signal source and is used for controlling the phase-locked loop to open phase locking work; the control output end of the level extraction control circuit is connected with the current injection control end of the current injection switch module, and meanwhile, the current stepping input control end of the current injection switch module and the driving input end of the level extraction control circuit are both connected with a preset control signal output end of the phase frequency detector, and the control circuit is used for controlling the current injection switch module to inject charges into the low-pass filter according to the level width change condition of the output signal of the preset control signal output end until the phase of a reference clock signal input by the phase frequency detector is synchronous with the phase of a feedback clock signal; the signal output by the preset control signal output end is an inverse signal of a control signal output by the phase frequency detector and used for controlling the charge pump to inject current; the signal input end of the low-pass filter is connected with the signal output end of the charge pump, the capacitance input end of the low-pass filter is connected with the signal output end of the current injection switch module, and the low-pass filter is used for receiving charges provided by the signal output end of the charge pump and charges injected by the signal output end of the current injection switch module, generating control voltage by receiving the accumulated charges, and outputting the control voltage to the voltage-controlled oscillator, wherein the capacitance input end of the low-pass filter is as follows: in the resistor-capacitor series branch inside the low-pass filter, the connection node of the resistor and the capacitor connected in series is connected.

The technical scheme is based on a pure hardware circuit, the level extraction control circuit obtains low level width information of a control signal by means of delay processing according to the jumping condition of the control signal reflecting the phase relation of a reference clock signal and a feedback clock signal, and controls the current conduction state of a current injection switch module based on the change condition of the low level width information along with the time, so that the charge is quickly injected into a low-pass filter until a phase-locked loop is close to stability, the oscillation is avoided by injecting the charge step by step, and the phase-locked time is shortened.

Further, the current injection switch module includes: the power supply comprises a power supply source, a first zero NMOS tube, a second zero NMOS tube and a first zero PMOS tube; the source electrode of the first zero NMOS tube is connected with the drain electrode of the second zero NMOS tube, the grid electrode of the first zero NMOS tube is connected with the drain electrode of the first zero NMOS tube, and the drain electrode of the first zero NMOS tube is connected with a power supply, so that the first zero NMOS tube is used as a current-limiting MOS tube; the drain electrode of the second zero NMOS tube is connected with the source electrode of the first zero NMOS tube, the source electrode of the second zero NMOS tube is connected with the source electrode of the first zero PMOS tube, the grid electrode of the second zero NMOS tube is connected with the preset control signal output end and serves as a current stepping input control end of the current injection switch module, and the current stepping input control end is used for changing the conduction condition of the second zero NMOS tube according to the jumping state of an output signal of the preset control signal output end so as to realize stepping current injection of the current injection switch module; the source electrode of the first zero PMOS tube is connected with the source electrode of the second zero NMOS tube, and the grid electrode of the first zero PMOS tube is connected with the control output end of the level extraction control circuit and serves as the current injection control end of the current injection switch module; and the drain electrode of the first zero PMOS tube is used as the signal output end of the current injection switch module and is connected with the capacitor input end of the low-pass filter. The technical scheme simultaneously utilizes the output signal of the preset control signal output end to be matched with the control signal output by the drive level extraction control circuit, and controls the current injected into the low-pass filter to be injected in a stepping mode when the current is close to the locking state, so that the voltage overshoot of the capacitor input end of the low-pass filter is reduced. The stability of the applicable phase-locked loop system is not affected.

Furthermore, the level extraction control circuit comprises a pulse width extraction array, a delay level generation array and a control signal generation module; the driving input end is connected with a clock input end of the delay level generating array, and the enabling control end is connected with a data input end of the delay level generating array; the delay level generation array internally comprises n +3 cascaded D triggers, and n +3 data output ends are correspondingly arranged respectively, wherein the D trigger connected with the enabling control end is a first-stage D trigger, and the stage number of the cascaded pulse width extraction unit is the same as the smaller stage number of two connected adjacent cascaded D triggers; the pulse width extraction array comprises n +2 cascaded pulse width extraction units, each pulse width extraction unit is provided with 2 pulse input ends, 1 charge discharge control end, 1 driving end and 1 pulse width information output end, adjacent cascaded pulse width extraction units have a common pulse input end, and the driving ends of the n +2 cascaded pulse width extraction units are connected with a clock input end arranged in the delay level generation array; the data output ends of two adjacent cascaded D triggers in the delay level generating array are correspondingly connected to two pulse input ends of pulse width extracting units with matched series of the pulse width extracting array; in the delay level generating array, the inverted output end of the D trigger connected with the enabling control end is connected with the charge discharge control end of each pulse width extraction unit; the positive and negative input ends of each comparator are respectively connected with the pulse width information output ends of adjacent cascaded pulse width extraction units, and only one input end of each of the two adjacent comparators is connected with the pulse width information output end of the same pulse width extraction unit, wherein the input ends of the two adjacent comparators connected with the pulse width information output end of the same pulse width extraction unit have different attributes, and the input ends of the two non-adjacent comparators are not connected with the pulse width information output end of the same pulse width extraction unit. The technical scheme is that an enable control signal EN output by an enable control end is sent to a delay level generation array for delay processing to obtain n +3 delay levels, the conduction condition of a pulse width extraction unit of a corresponding stage in a pulse width extraction array is controlled by delay output signals of every two adjacent stages, low level width extraction in each period output by a drive input end is converted into voltage information to be stored in a capacitor of the pulse width extraction unit, a comparator in a control signal generation module compares a voltage value representing the pulse width information output by the pulse width extraction unit to determine the condition that a current injection switch module injects charges into a low-pass filter, so that the technical effect of step-by-step current injection is achieved, the charge change speed of the capacitor input end of the low-pass filter is improved, and the probability of voltage overcharge at the capacitor input end is reduced, the time for phase locking is shortened; and proper stage expansion and circuit parameter adjustment are carried out according to the logic relation of the circuit so as to obtain a more accurate control effect.

Further, in the delay level generating array, the connection structure of the n +3 cascaded D flip-flops is: the data input end of the first-stage D trigger is connected with the enabling control end; in two adjacent cascaded D triggers, the data input end of the D trigger of the next stage is connected with the data output end of the D trigger of the previous stage; the clock end of each stage of D trigger is connected with the driving input end, and the reset end of each stage of D trigger is connected with the enabling control end. According to the technical scheme, under the common driving action of an enabling signal of a phase-locked loop and a signal of a preset control signal output end, the generation of a delay level is realized through a cascaded D trigger.

Furthermore, the pulse width extraction array comprises a power supply and n +2 cascaded pulse width extraction units, wherein each pulse width extraction unit comprises a pulse width test NMOS (N-channel metal oxide semiconductor) tube, a pulse width test PMOS tube, a switch PMOS tube, a reset control NMOS tube and a capacitor; in the current-stage pulse width extraction unit, the grid electrode of a pulse width test NMOS tube is connected with the data output end of a first-stage D trigger in the delay level generation array, and the grid electrode of a pulse width test PMOS tube is connected with the data output end of a second-stage D trigger in the delay level generation array, wherein the stage number of the first-stage pulse width extraction unit is equal to that of the current-stage pulse width extraction unit, the second-stage D trigger and the first-stage D trigger are in an adjacent cascade connection relation, so that the data output ends of two adjacent cascade connected D triggers in the delay level generation array are correspondingly connected to two pulse input ends of a pulse width extraction unit with the matched stage number of the pulse width extraction array, and the grid electrode of the pulse width test NMOS tube and the grid electrode of the pulse width test PMOS tube are respectively used as the 2 pulse input ends; in each level of pulse width extraction unit, the source electrode of a pulse width test PMOS tube is connected with a power supply, the drain electrode of the pulse width test PMOS tube is connected with the drain electrode of a pulse width test NMOS tube, the source electrode of the pulse width test NMOS tube is connected with the source electrode of a switch PMOS tube, the grid electrode of the switch PMOS tube is used as the drive end of the pulse width extraction unit, the grid electrode of a reset control NMOS tube is used as the charge discharge control end, the drain electrode of the reset control NMOS tube is simultaneously connected with the drain electrode of the switch PMOS tube and the upper polar plate of a capacitor, the connection node of the drain electrode of the reset control NMOS tube and the upper polar plate of the capacitor is used as the pulse width information output end, and the lower; the gates of the switch PMOS tubes of all the cascaded pulse width extraction units are connected to the clock input end, and the gates of the reset control NMOS tubes of all the cascaded pulse width extraction units are connected to the inverted output end of the first-stage D trigger.

Compared with the prior art, the technical scheme includes that delay signals output by all adjacent cascaded D triggers of the array are generated according to the delay level, corresponding low level width information on the extraction interval of each level of pulse width extraction unit is determined and stored in a capacitor of the corresponding level of pulse width extraction unit, so that the charging and discharging time of the pulse width information output end of the pulse width extraction unit is adjusted by changing the capacitance ratio of the adjacent two levels of pulse width extraction units, the time that the level extraction control circuit controls the on-off current of the current injection switch module is further realized, the increase of phase locking time caused by the delay fed back by a loop of a phase-locked loop can be counteracted, the control voltage output by the low-pass filter tends to be stable, and the locking time of the phase-locked loop is shortened.

In combination with the above technical solution, in the n +2 cascaded pulse width extraction units, a ratio between capacitances of two adjacent cascaded pulse width extraction units is a preset value, and the preset value is smaller than 1. This preferred solution is advantageous to control the current injection switching module to cut off the injection of charge to the capacitive terminal of the low-pass filter within one period of the signal UP.

Furthermore, the control signal generation module comprises n comparators, or logic circuits and a switch D trigger; the n comparators start from the pulse width extraction unit of the second stage according to the cascade sequence in the pulse width extraction array, the positive and negative input ends of each comparator are respectively connected with the pulse width information output ends of the adjacent cascade pulse width extraction units, the negative input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with the smaller stage number, and the positive input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with the larger stage number; the signal output ends of the n comparators are respectively connected to n input ends of an OR logic circuit, the output end of the OR logic circuit is connected to a clock end of a switch D trigger, a data input end and a reset end of the switch D trigger are both connected with the enabling control end, and a data output end of the switch D trigger is used as a control output end of the level extraction control circuit; wherein, the OR logic circuit comprises a plurality of OR gates or corresponding combinational logic circuits. The input ends of the n comparators in the technical scheme respectively receive voltage signals of pulse width information output by the pulse width extraction array, and the final comparison result of the level extraction control circuit is determined through comparison, however, the output voltage of the pulse width information output end is possibly changed due to leakage of capacitance charges of the pulse width extraction array after long-time operation, and the data output end of the switch D trigger can be ensured to maintain the output level state unchanged through the switch D trigger connected with the OR gate under the condition that the pulse width information output end outputs an edge jump signal, so that the reliability of the phase-locked acceleration circuit is improved.

A phase-locked loop system comprising: the phase frequency detector generates a pulse control signal; the charge pump is used for generating charging current and discharging current according to the control signal output by the phase frequency detector; the low-pass filter is used for converting the current control signal output by the charge pump into control voltage and filtering high-frequency noise; the voltage-controlled oscillator is used for controlling the frequency of an output signal of the voltage-controlled oscillator according to the control voltage output by the low-pass filter, increasing the oscillation frequency of the output signal when the control voltage is increased, decreasing the oscillation frequency of the output signal when the control voltage is decreased, and keeping the oscillation frequency of the output signal at a constant value when the control voltage is stable; the frequency divider is used for dividing the frequency of the output signal of the voltage-controlled oscillator to generate a feedback clock signal of the phase frequency detector; the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the frequency divider are sequentially connected to form a feedback loop; further comprising: the level extraction control circuit of the phase-locked acceleration circuit controls the current injection switch module of the phase-locked acceleration circuit to inject charges into the low-pass filter according to the duty ratio change condition of the inverse signal of the control signal output by the phase frequency detector until the phase of the reference clock signal input by the phase frequency detector is synchronous with the phase of the feedback clock signal, so that the phase-locked acceleration circuit shortens the phase-locked time of the feedback loop. According to the technical scheme, n +3 delay levels are obtained by delaying an external enabling control signal, corresponding pulse width information is extracted from a control signal which reflects the phase difference between a reference clock signal and a feedback clock signal and is output by a phase frequency detector and is used as a voltage signal for injection switch control in the current injection switch module, the pulse width information is used as a basis for level extraction, and the reliability of a conduction result of the current injection switch module is ensured by a switch D trigger. Therefore, the phase locking time of the phase-locked loop system is shortened, the stability of the control voltage output by the low-pass filter is ensured to be unchanged, the system characteristics, the transfer function and the noise performance are not changed, and the method can be widely applied to other phase-locked loop systems without changing device parameters and loop parameters.

Drawings

Fig. 1 is a schematic diagram of a frame of a phase-locked loop system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a level extraction control circuit applied to the phase-locked loop system shown in fig. 1.

Fig. 3 is a schematic structural diagram of a pulse width extraction array applied to the level extraction control circuit shown in fig. 2 according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a delay level generating array applied to the level extraction control circuit shown in fig. 2 according to an embodiment of the present invention.

Fig. 5 is a waveform diagram of output signals of the stages D flip-flops of the delay level generating array of fig. 4 varying with the input control signal UP.

Fig. 6 is a schematic structural diagram of a control signal generating module applied to the level extraction control circuit shown in fig. 2 according to an embodiment of the present invention.

Fig. 7 is a waveform diagram of input signals of the input terminals of the respective comparators of the control signal generation block of fig. 6, and the or logic result ctrl of the output signals of all the comparators follows the input control signal UP.

Fig. 8 is a waveform diagram of the capacitor input terminal VC _ DN of the low pass filter and the voltage VC _ out of the signal output terminal of the low pass filter before and after phase locking in the conventional phase locked loop system.

Fig. 9 is a waveform diagram of the capacitor input terminal VC _ DN of the low-pass filter and the voltage VC _ out of the signal output terminal of the low-pass filter before and after phase locking in the phase-locked loop system according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. Note that, the port name label at the circuit port below corresponds to the signal voltage input and output by the port.

The embodiment of the utility model provides a phase-locked accelerating circuit based on level width extraction, as shown in figure 1, the phase-locked loop suitable for the phase-locked accelerating circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, wherein the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the frequency divider are connected in sequence to form a feedback loop, the phase-locked accelerating circuit is additionally provided with a level extraction control circuit and a current injection switch module on the basis of the traditional phase-locked loop, the phase-locked accelerating circuit utilizes a control signal which reflects the phase relation between an input reference clock signal and a feedback clock signal and is output by the phase frequency detector to drive the level extraction control circuit to control the condition that the current injection switch module injects charges into the low-pass filter and realize the function of opening the current injection low-pass filter step by step until the reference clock signal fref input by the phase frequency detector is synchronous with, the phase synchronization change (i.e. phase synchronization) of the reference clock signal fref and the feedback clock signal fbk is realized, the control voltage overshoot of the input voltage-controlled oscillator is avoided, meanwhile, the delay of the feedback loop is also counteracted, and the phase locking time is reduced.

As shown in fig. 1, the level extraction control circuit is provided with a driving input terminal UP, an enable control terminal EN, and a control output terminal ctr _ kep; the current injection switch module is provided with a current stepping control end UP and a current injection control end ctr _ kep, namely, a control output end ctr _ kep of the level extraction control circuit is connected with the current injection control end ctr _ kep of the current injection switch module; the enable control terminal EN of the level extraction control circuit is connected to an external enable signal source EN for controlling the feedback loop to start phase locking operation, and starts to automatically adjust the phase relationship between the reference clock signal fref and the feedback clock signal fbk. Meanwhile, the current step input control end UP of the current injection switch module and the driving input end UP of the level extraction control circuit are both connected to a preset control signal output end UP of the phase frequency detector. In the phase frequency detector, control signals UP, DN, UPB and DNB are generated by comparing an input reference clock signal fref with a feedback clock signal fbk, the signal UPB and the signal DN are used for controlling a current switch MOS tube in a charge pump, the signal UP and the signal DNB are used for controlling cancellation charge sharing, the signal UPB and the signal UP are a pair of opposite level signals, the signal DNB and the signal DN are also a pair of opposite level signals, specifically, the signal DN is kept as a constant signal after the rising phase of a control voltage output by a low-pass filter, and therefore, the signal DNB and the signal DN are not suitable for step-by-step current regulation. In the prior art, a current switching device of a charge pump is controlled by using a signal UPB, and if the signal is used for controlling current injection into a switching module, the output current of the charge pump is affected. Therefore, in this embodiment, the UP signal output by a preset control signal output end of the phase frequency detector is used to control the current injection switch module, that is, the inverted signal of the control signal output by the phase frequency detector and used to control the charge pump to perform current injection is used to control the on/off of the current injection switch module, and the charge pump is not affected.

As shown in fig. 1, a signal input terminal VC _ in of the low pass filter is connected to a signal output terminal of the charge pump, a capacitance input terminal VC _ DN of the low pass filter is connected to a signal output terminal of the current injection switch module, and is configured to receive the charge provided by the signal output terminal of the charge pump and the charge injected by the signal output terminal of the current injection switch module, generate a control voltage by receiving the accumulated charge, and output the control voltage to the voltage controlled oscillator through a signal output terminal VC _ out of the low pass filter, where the capacitance input terminal VC _ DN of the low pass filter is: in the resistor-capacitor series branch inside the low-pass filter, the connection node of the resistor R and the capacitor C10 connected in series with the resistor R is connected. The low-pass filter shown in the embodiment of fig. 1 is a second-order low-pass filter, which includes a first filter capacitor C10, a second filter capacitor C20, and a resistor R3, the signal output end (i.e. VC _ DN in fig. 1) of the current injection control module is connected to one end of the first filter capacitor C10 and one end of the resistor R, the other end of the first filter capacitor C10 is grounded, the other end of the resistor R is connected to one end of the second filter capacitor C20, the other end of the second filter capacitor C20 is grounded, a connection node of the first filter capacitor C10 and the resistor R is a capacitor input terminal VC _ DN of the low-pass filter, a connection node of the resistor R and the second filter capacitor C20 is used as a signal input terminal VC _ in of the low-pass filter, and a connection node of the resistor R and the second filter capacitor C20 is also used as a signal output terminal VC _ out of the low-pass filter. Besides the embodiment shown in fig. 1, the multi-order low-pass filter such as the three-order low-pass filter circuit and the like is applicable to the phase-locked accelerating circuit (not shown in the figure), and no loop parameter is required to be changed, and a connection node of the filter resistor and the filter capacitor can be used as an input end or an output end of the low-pass filter and can be used for receiving the charge injected by the current injection switch module and the charge injected by the charge pump in the charging and discharging process. Meanwhile, other performances can be optimized according to the rapid locking capacity provided by the phase-locked accelerating circuit. The low pass filter functions to convert the pulse control signal (in the form of charge and discharge through a charge pump) output by the phase frequency detector, which is related to phase error, into a stable control signal and to filter out noise.

It should be noted that, in the phase-locked loop, the locking process of the phase-locked loop is divided into a frequency adjustment stage and a phase adjustment stage, the phase-locked loop starts to work, and the enable control signal changes from a low level to a high level, in this embodiment, it can be considered that the enable control end EN of the level extraction control circuit changes from a low level to a high level, the phase-locked loop starts to work and enters the frequency adjustment stage, because of the enable control of the enable signal EN, the voltage-controlled oscillator starts to generate an output clock frequency signal and feeds the output clock frequency signal back to the phase frequency detector through the frequency divider, in this stage, the UP signal is at a long-range high level first, and when the phase frequency detector receives the feedback signal, the UP signal with an irregularly-changing duty ratio is output according to the phase relationship between the reference clock signal fref and the; when the signal UP is at a long-section high level, the control output end ctr _ kep of the level extraction control circuit is at a low level, and the current injection switch module is turned on, so that charges are injected into the filter capacitor inside the low-pass filter, the process of adjusting the frequency is accelerated, the voltage output by the low-pass filter to the voltage-controlled oscillator is increased until the voltage is close to and slightly lower than the final stable voltage, and therefore the frequency of the feedback clock signal fbk is slightly lower than the frequency of the reference clock signal fref, and the signal UP is promoted to skip the irregular change stage and enter a phase adjustment stage. After entering a phase adjustment stage, a signal UP is adjusted to be a rectangular wave signal with a changing duty ratio law by the phase frequency detector, and the changing law is as follows: it can be seen from fig. 5 and fig. 7 that the low-level width of the signal UP is decreased and then increased (since the voltage output from the low-pass filter to the voltage-controlled oscillator is slightly lower than the final stable voltage when the phase-locked loop of the present embodiment enters the phase adjustment phase, only this situation is considered), until the low-level width of the signal UP is almost equal to the period width of the signal UP, and the pulse width of the signal UP is very small.

Specifically, the variation trend of the signal UP reflects the phase relationship between the feedback signal and the reference signal input by the phase frequency detector. When the low level width of the UP signal increases, indicating that the frequency of the feedback clock signal fbk is less than the frequency of the reference clock signal fref, at this stage, the reference clock signal fref leads the feedback clock signal fbk, and the leading level width of the reference clock signal fref relative to the feedback clock signal fbk increases, the voltage VC output by the low-pass filter for controlling the voltage-controlled oscillator is lower than the final stable voltage, and the current is injected into the corresponding capacitor of the low-pass filter by the charge pump to raise the voltage of the signal output terminal VC _ out of the low-pass filter, and the frequency of the feedback clock signal fbk is raised accordingly, so that the increasing speed of the low level width of the UP signal gradually decreases until the frequency of the feedback clock signal fbk is equal to the frequency of the reference clock signal fref, the low level width of the UP signal no longer increases, due to the feedback delay characteristic of the pll, the voltage at the signal output end VC _ out of the low-pass filter is already slightly higher than the final stable voltage, and at this time, since the phases of the feedback clock signal fbk and the reference clock signal fref are not aligned, a phase synchronization process still needs to be performed, and then the voltage at the signal output end VC _ out of the low-pass filter continues to be raised, the frequency of the feedback clock signal fbk is greater than the frequency of the reference clock signal fref, the low-level width of the control signal UP starts to decrease, and at this time, the voltage at the signal output end VC _ out of the low-pass filter exceeds the final stable voltage value, and then a decaying oscillation process is performed until phase locking.

In the phase locking process, the frequency adjustment stage is entered first, and due to the delay effect of the feedback loop, the signal UP goes through a long high level, the current injection switch module is conducted to quickly inject charges into the capacitor input end VC _ DN, the voltage of the signal output end VC _ out is quickly increased, and the voltage of the signal output end VC _ out is close to the final stable voltage, then, along with the coming of the feedback signal, the signal UP is changed into a jump signal with the low level and the width changing regularly, the phase adjustment stage is switched to the phase adjustment stage from the frequency adjustment stage, the stage of step-by-step adjustment of the current injection switch module is started, the level extraction control circuit is used for outputting the duty ratio change condition of the signal UP according to the control signal output end, the signal output by the control output ctr _ kep is hopped at an appropriate time to turn off the charge injection to the capacitive input VC _ DN of the low-pass filter.

Specifically, the level extraction control circuit determines a plurality of extraction intervals by delaying an enable control end EN signal of the level extraction control circuit, and extracts low-level pulse width information of the signal UP at different time stages before the phase lock is stabilized, that is, compares low-level pulse widths of the signal UP output by the control output end at different time stages. When the voltage of the signal output end VC _ out of the low-pass filter is close to stability, the output of the control output end ctr _ kep jumps, phase locking acceleration is completed, the speed of phase synchronization of the feedback clock signal fbk and the reference clock signal fref is increased, and the phase-locked loop can enter a stable damped oscillation locking process, so that the phase-locked time can be greatly reduced, the phase-locked loop can be quickly locked, and the phase-locked time is reduced. And the level extraction control circuit selects the moment when the increase trend of the pulse width of the signal UP starts to change according to the change rule of the low level width of the pulse signal UP, and the frequency of the feedback clock signal fbk is close to the frequency of the reference clock signal fref at the moment, so that the control output end ctr _ kep of the level extraction control circuit outputs high level, thereby turning off the work of the phase-locked accelerating circuit, and at the moment, the phase-locked accelerating circuit is turned off to avoid the charge overshoot of the low-pass filter. Compared with the prior art, the voltage of the signal output end VC _ out of the low-pass filter is quickly increased by quickly injecting charges on the basis of a pure hardware circuit; the level extraction control circuit controls the current conduction state of the current injection switch module according to the jump condition of a control signal UP reflecting the phase relation between a reference clock signal and a feedback clock signal, charges are injected into the low-pass filter in a stepping control mode in cooperation with the duty ratio change of the signal UP, the phase locking time is shortened, and meanwhile, the phase locking accelerating circuit is switched off when the phase locking accelerating circuit approaches to the phase locking state, so that the influence on loop parameters is avoided.

As shown in fig. 1, the current injection switch module includes: the power supply VCC comprises a first zero NMOS transistor MN10, a second zero NMOS transistor MN20 and a first zero PMOS transistor MP 10; the source electrode of the first zero NMOS transistor MN10 is connected with the drain electrode of the second zero NMOS transistor MN20, the grid electrode of the first zero NMOS transistor MN10 is connected with the drain electrode of the first zero NMOS transistor MN10, and the drain electrode of the first zero NMOS transistor MN10 is connected with a power supply VCC, so that the first zero NMOS transistor MN10 is used as a current-limiting MOS transistor; the drain electrode of the second zero NMOS transistor MN20 is connected to the source electrode of the first zero NMOS transistor MN10, the source electrode of the second zero NMOS transistor MN20 is connected to the source electrode of the first zero PMOS transistor MP10, and the gate electrode of the second zero NMOS transistor MN20 is connected to the preset control signal output terminal UP, and is used as the current step input control terminal UP of the current injection switch module, and is configured to change the conduction condition of the second zero NMOS transistor MN20 according to the transition state of the preset control signal output terminal UP, so as to realize the step-wise injection current of the current injection switch module; the source electrode of the first zero PMOS transistor MP10 is connected to the source electrode of the second zero NMOS transistor MN20, and the gate electrode of the first zero PMOS transistor MP10 is connected to the control output end ctr _ kep of the level extraction control circuit, and serves as the current injection control end ctr _ kep of the current injection switch module; the drain electrode of the first zero PMOS pipe MP10 is used as the signal output end of the current injection switch module and is connected with the capacitor input end VC _ DN of the low-pass filter; the second zero NMOS transistor MN20 is turned on when the signal UP is high, and the second zero NMOS transistor MN20 is turned off when the signal UP is low; meanwhile, the first zero PMOS transistor MP10 is turned off when the signal ctr _ kep is high, and the first zero PMOS transistor MP10 is turned on when the signal ctr _ kep is low; when the second zero NMOS transistor MN20 and the first zero PMOS transistor MP10 are simultaneously switched on, the current injection switch module controls a power supply VCC to inject current into a capacitor input end VC _ DN of the low-pass filter, and accelerates the change of voltage VC _ DN, so that the change of control voltage output by the voltage-controlled oscillator is accelerated by the low-pass filter, otherwise, the phase-locked acceleration circuit is switched off. The current injection switch module simultaneously utilizes the output signal of the preset control signal output end to match with the control signal output by the drive level extraction control circuit, charges are quickly injected at the beginning, and the current injected into the low-pass filter is controlled to be injected in a stepping mode when the phase is close to phase locking, so that the voltage overshoot of the capacitor input end of the low-pass filter is reduced. The stability of the applicable phase-locked loop system is not affected.

As shown in fig. 2, 3, 4 and 6, the level extraction control circuit includes a pulse width extraction array, a delay level generation array and a control signal generation module; the drive input end UP is connected with a clock input end UP set by a delay level generating array, and the enable control end EN is connected with a data input end set by the delay level generating array; the delay level generation array comprises n +3 cascaded D triggers which are correspondingly provided with n +3 data output ends Q1, Q2, Q3 and … Qn +3, wherein the D trigger connected with the enable control end EN is a first-stage D trigger, the stage number of the D trigger cascaded with the first-stage D trigger is sequentially increased, correspondingly, the stage number of the cascaded pulse width extraction unit is the same as the smaller stage number of two connected adjacent cascaded D triggers, and when the pulse width extraction unit of a certain stage is respectively connected with the data output end Q1 of the first-stage D trigger and the data output end Q2 of the second-stage D trigger, the pulse width extraction unit belongs to the first-stage pulse width extraction unit of the pulse width extraction array. The pulse width extraction array comprises n cascaded pulse width extraction units, and each pulse width extraction unit is provided with 2 pulse input ends, 1 charge discharge control end, 1 driving end and 1 pulse width information output end; the adjacent cascaded pulse width extraction units have a common pulse input end and are connected with the D trigger of the same stage, and the stage number of the D trigger of the stage is the same as that of the pulse width extraction unit of the next stage in the adjacent cascaded pulse width extraction units. The driving ends of the n +2 cascaded pulse width extraction units are all connected to a clock input end UP arranged in the delay level generation array. The data output ends of two adjacent cascaded D flip-flops in the delay level generating array are correspondingly connected to the two pulse input ends of pulse width extracting units with matched series of the pulse width extracting array, for example, the data output end Q2 of a second-stage D flip-flop and the data output end Q2 of a third-stage D flip-flopThe data output Q3 of the comparator is connected to two pulse inputs of the pulse width extraction unit of the second stage. In the delay level generating array, the inverted output end Q1B of the D flip-flop connected with the enabling control end is connected with the charge leakage control end of each pulse width extraction unit. N comparators are arranged in the control signal generation module, positive and negative phase input ends of each comparator are respectively connected with pulse width information output ends of adjacent cascaded pulse width extraction units, and the pulse width extraction module comprises a pulse width information output end V, wherein the positive phase input end of one comparator is connected with the pulse width information output end of the pulse width extraction unit of the (n + 2) th level_n+2The inverting input end of the comparator is connected with the (n + 1) th stage>1) Pulse width information output terminal V of the pulse width extraction unit_n+1(ii) a Two adjacent comparators only have one input end connected with the pulse width information output end of the same pulse width extraction unit, the inverting input end of the first comparator is connected with the pulse width information output end V2 of the pulse width extraction unit of the second stage, the non-inverting input end of the first comparator is connected with the pulse width information output end V3 of the pulse width extraction unit of the third stage, the inverting input end of the second comparator is connected with the pulse width information output end V3 of the pulse width extraction unit of the third stage, the non-inverting input end of the second comparator is connected with the pulse width information output end V4 of the pulse width extraction unit of the fourth stage, the inverting input end of the third comparator is connected with the pulse width information output end V4 of the pulse width extraction unit of the fourth stage, and the non-inverting input end of the third comparator is connected with the pulse width information output end V5 of the pulse width extraction unit of the fifth stage, so that the input ends of the, the input ends of the two non-adjacent comparators are not connected with the pulse width information output end of the same pulse width extraction unit. In this embodiment, an enable control signal EN output by the enable control terminal is first sent to a delay level generation array for delay processing, so as to obtain n +3 delay levels; then, the conduction condition of the pulse width extraction unit of the corresponding stage in the pulse width extraction array is controlled by the delay output signals of every two adjacent stages, the low level width extraction in each period of the output signal UP of the driving input end is converted into voltage information, the voltage information is stored in a capacitor of the pulse width extraction unit, and then the pulse is compared by a comparator in the control signal generation moduleThe voltage value which is output by the wide extraction unit and represents pulse width information is used for determining the condition that the current injection switch module injects charges into the low-pass filter, so that the technical effect of step-by-step current injection is achieved, the charge change speed of the capacitor input end of the low-pass filter is improved, the voltage overcharge frequency of the capacitor input end VC _ DN is reduced, and the phase locking time is shortened; and proper stage expansion and circuit parameter adjustment are carried out according to the logic relation of the circuit so as to obtain a more accurate control effect.

As an embodiment, in the delay level generating array, n is preferably 5, and the delay level generating array is formed by cascading eight D flip-flops, as shown in fig. 4, the connection structure is: the data input end D of the first-stage D trigger is connected with the enabling control end EN; in two adjacent cascaded D flip-flops, a data input terminal D of a D flip-flop of a next stage is connected to a data output terminal Q of a D flip-flop of a previous stage, 8 data output terminals Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8 are respectively and correspondingly arranged, a clock terminal of each D flip-flop is connected to the driving input terminal UP, and a reset terminal CLR of each D flip-flop is connected to the enable control terminal EN. When the signal EN changes from low to high, which marks the pll starting a new phase-locked loop operation, as shown in fig. 5, the UP signal generates a first rising edge at time t0, and the output Q1 of the first stage D flip-flop receives the signal EN, so that the output Q1 changes to high. Due to the delay of the first stage D flip-flop, the second stage D flip-flop is at a low level when the first rising edge of the signal UP comes, the output terminal Q2 of the second stage D flip-flop is still at a low level until time t1, the signal UP is kept at a high level state for a long time period between t0 and t1, the output terminals Q3, Q4, Q5, Q6, Q7, and Q8 of the subsequent stage D flip-flops higher than the first stage D flip-flop are kept at a low level, and when the signal UP changes to a low level within a time period from t0 to t1, the output signals of the cascaded D flip-flops do not change, but the output signals can be used for turning on the first zero PMOS transistor MP10 of the current injection switch module, and charges are injected into the capacitor input terminal VC _ DN of the low pass filter MN through the first zero NMOS transistor MP10 and the second zero NMOS transistor MN20, so as to accelerate the frequency modulation. At time t1, when the second rising edge of the UP signal arrives, the output Q1 of the first stage D flip-flop is still high and does not change, and the output Q2 of the second stage D flip-flop receives the high level of the output Q1 of the first stage D flip-flop. Also due to the delay effect, the input Q2 of the third stage D flip-flop is at a low level when the second rising edge of the UP signal arrives, so the output of the third stage D flip-flop is at a low level until the third rising edge of the UP signal arrives at time t2, where the UP signal appears to change irregularly during the time period from t0 to t2, and is in the frequency adjustment phase. In the same principle, every time the next rising edge of the signal UP comes, the output of the next stage D flip-flop changes to high level, so as to realize the generation of delay level until the time t7, wherein the present embodiment sets phase locking at the time t 7; then, the signal UP appears as low-level and high-level pulses, in which the low-level width of the signal UP is almost equal to one period of the signal UP. Therefore, the time t2 to t7 is in the phase adjustment phase, the low level width of the UP signal decreases and then increases, and after the time t7, the low level width of the UP signal does not increase any more, and the phase lock enters the stable state.

The pulse width extraction array comprises a power supply VCC and n +2 cascaded pulse width extraction units, wherein n is preferably 5, as shown in fig. 3, the first-stage pulse width extraction unit comprises a first pulse width test NMOS transistor MN1, a first pulse width test PMOS transistor MP1, a first switch PMOS transistor MP11, a first reset control NMOS transistor MN11 and a first capacitor C1, a gate of the first pulse width test NMOS transistor MN1 is connected to a data output Q1 of a D flip-flop of a first stage in the delay level generation array, a gate of the first pulse width test PMOS transistor MP1 is connected to a data output Q2 of a D flip-flop of a second stage in the delay level generation array, the D flip-flops of the second stage and the D flip-flops of the first stage are in an adjacent cascaded connection relationship, so as to satisfy that data outputs of two adjacent cascaded D flip-flops in the delay level generation array are correspondingly connected to two pulse input terminals of pulse width extraction units of a matched stage number in the delay level extraction array, the grid electrode of the first pulse width test NMOS transistor MN1 and the grid electrode of the first pulse width test PMOS transistor MP1 are respectively used as the 2 pulse input ends; the source of the first pulse width test PMOS transistor MP1 is connected to a power supply VCC, the drain of the first pulse width test PMOS transistor MP1 is connected to the drain of the first pulse width test NMOS transistor MN1, the source of the first pulse width test NMOS transistor MN1 is connected to the source of the first switch PMOS transistor MP11, the gate of the first switch PMOS transistor MP11 is used as the driving end UP of the pulse width extraction unit, the gate of the first reset control NMOS transistor MN11 is used as the charge bleed control end Q1B, the drain of the first reset control NMOS transistor MN11 is simultaneously connected to the drain of the first switch PMOS transistor MP11 and the upper plate of the first capacitor C1, the connection node V1 between the drain of the first reset control NMOS transistor MN11 and the upper plate of the first capacitor C1 is used as the pulse width information output terminal, and the lower plate of the first capacitor C1 and the source of the first reset control NMOS transistor MN11 are both grounded.

As shown in fig. 3, the second-stage pulse width extraction unit includes a second pulse width test NMOS transistor MN2, a second pulse width test PMOS transistor MP2, a second switch PMOS transistor MP22, a second reset control NMOS transistor MN22 and a second capacitor C2, a gate of the second pulse width test NMOS transistor MN2 is connected to the data output terminal Q2 of the second-stage D flip-flop in the delay level generation array, a gate of the second pulse width test PMOS transistor MP2 is connected to the data output terminal Q3 of the third-stage D flip-flop in the delay level generation array, a source of the second pulse width test PMOS transistor MP2 is connected to the power supply VCC, a drain of the second pulse width test PMOS transistor MN2 is connected to a drain of the second pulse width test PMOS transistor MP2, a source of the second pulse width test NMOS transistor MN2 is connected to a source of the second switch PMOS transistor MP22, a gate of the second switch PMOS transistor MP22 is used as the driving terminal UP of the pulse width extraction unit, and a gate of the second reset control NMOS transistor MN22 is used as the charge discharge terminal Q B, the drain of the second reset control NMOS transistor MN22 is connected to the drain of the second switching PMOS transistor MP22 and the upper plate of the second capacitor C2, the connection node V2 between the drain of the second reset control NMOS transistor MN22 and the upper plate of the second capacitor C2 serves as the pulse width information output terminal, and the lower plate of the second capacitor C2 and the source of the second reset control NMOS transistor MN22 are both grounded.

Similarly, as shown in fig. 3, the third-stage pulse width extraction unit includes a third pulse width test NMOS transistor MN3, a third pulse width test PMOS transistor MP3, a third switching PMOS transistor MP33, a third reset control NMOS transistor MN33 and a third capacitor C3, a gate of the third pulse width test NMOS transistor MN3 is connected to the data output terminal Q3 of the third-stage D flip-flop in the delay level generation array, a gate of the third pulse width test PMOS transistor MP3 is connected to the data output terminal Q4 of the fourth-stage D flip-flop in the delay level generation array, a source of the third pulse width test PMOS transistor MP3 is connected to the power supply VCC, a drain of the third pulse width test PMOS transistor MP3 is connected to the drain of the third pulse width test NMOS transistor MN3, a source of the third pulse width test NMOS transistor MN3 is connected to the source of the third switching PMOS transistor MP33, a gate of the third switching PMOS transistor MP33 is used as the driving terminal UP of the pulse width extraction unit, and a gate of the third reset control NMOS transistor MN33 is used as the charge discharge control terminal Q1B, the drain of the third reset control NMOS transistor MN33 is connected to the drain of the third switching PMOS transistor MP33 and the upper plate of the third capacitor C3 at the same time, the connection node V3 between the drain of the third reset control NMOS transistor MN33 and the upper plate of the third capacitor C3 serves as the output terminal of the pulse width information, and the lower plate of the third capacitor C3 and the source of the third reset control NMOS transistor MN33 are both grounded. The gates of the switching PMOS transistors of all the cascaded pulse width extraction units are connected to the clock input end, and the gates of the reset control NMOS transistors of all the cascaded pulse width extraction units are connected to a node, which is the inverted output end Q1B of the first stage D flip-flop.

As shown in fig. 3, the fourth-stage pulse width extraction unit includes a fourth pulse width test NMOS transistor MN4, a fourth pulse width test PMOS transistor MP4, a fourth switching PMOS transistor MP44, a fourth reset control NMOS transistor MN44 and a fourth capacitor C4, a gate of the fourth pulse width test NMOS transistor MN4 is connected to the data output terminal Q4 of the D flip-flop of the fourth stage in the delay level generation array, a gate of the fourth pulse width test PMOS transistor MP4 is connected to the data output terminal Q5 of the D flip-flop of the fifth stage in the delay level generation array, a source of the fourth pulse width test PMOS transistor MP4 is connected to the power supply VCC, a drain of the fourth pulse width test PMOS transistor MP4 is connected to the drain of the fourth pulse width test NMOS transistor MN4, a source of the fourth pulse width test NMOS transistor 4 is connected to a source of the fourth switching PMOS transistor MP44, a gate of the fourth switching PMOS transistor MP44 is used as the UP 1B of the pulse width extraction unit, and a gate drive terminal of the NMOS 44 is used as the charge bleed-off terminal Q1, the drain of the fourth reset control NMOS transistor MN44 is connected to the drain of the fourth switch PMOS transistor MP44 and the upper plate of the fourth capacitor C4 at the same time, the connection node V4 between the drain of the fourth reset control NMOS transistor MN44 and the upper plate of the fourth capacitor C4 serves as the pulse width information output terminal, and the lower plate of the fourth capacitor C4 and the source of the fourth reset control NMOS transistor MN44 are both grounded.

As shown in fig. 3, the fifth stage pulse width extraction unit includes a fifth pulse width test NMOS transistor MN5, a fifth pulse width test PMOS transistor MP5, a fifth switch PMOS transistor MP55, a fifth reset control NMOS transistor MN55 and a fifth capacitor C5, a gate of the fifth pulse width test NMOS transistor MN5 is connected to the data output terminal Q5 of the D flip-flop of the fifth stage in the delay level generation array, a gate of the fifth pulse width test PMOS transistor MP5 is connected to the data output terminal Q6 of the D flip-flop of the sixth stage in the delay level generation array, a source of the fifth pulse width test PMOS transistor MP5 is connected to the power supply VCC, a drain of the fifth pulse width test PMOS transistor MP5 is connected to the drain of the fifth pulse width test NMOS transistor MN5, a source of the fifth pulse width test NMOS transistor MN5 is connected to the source of the fifth switch PMOS transistor MP55, a gate of the fifth pulse width test PMOS transistor MP55 is used as the driving terminal of the pulse width extraction unit MN55, and a drain of the NMOS 1B of the gate of the fifth reset control NMOS transistor MN B, the drain of the fifth reset control NMOS transistor MN55 is connected to the drain of the fifth switch PMOS transistor MP55 and the upper plate of the fifth capacitor C5, the connection node V5 between the drain of the fifth reset control NMOS transistor MN55 and the upper plate of the fifth capacitor C5 serves as the pulse width information output terminal, and the lower plate of the fifth capacitor C5 and the source of the fifth reset control NMOS transistor MN55 are both grounded.

As shown in fig. 3, the sixth stage pulse width extraction unit includes a sixth pulse width test NMOS tube MN6, a sixth pulse width test PMOS tube MP6, a sixth switching PMOS tube MP66, a sixth reset control NMOS tube MN66 and a sixth capacitor C6, the gate of the sixth pulse width test NMOS tube MN6 is connected to the data output terminal Q6 of the D flip-flop of the sixth stage in the delay level generation array, the gate of the sixth pulse width test PMOS tube MP6 is connected to the data output terminal Q7 of the D flip-flop of the seventh stage in the delay level generation array, the source of the sixth pulse width test PMOS tube MP6 is connected to the power supply VCC, the drain of the sixth pulse width test PMOS tube MP6 is connected to the drain UP of the sixth pulse width test NMOS tube MN6, the source of the sixth pulse width test NMOS tube MN6 is connected to the source of the sixth switching PMOS tube MP66, the gate of the sixth switching PMOS tube MP66 is used as the driving terminal of the pulse width extraction unit, and the gate of the sixth reset control NMOS tube MN 3985 is used as the drain terminal Q3638 of the control NMOS transistor Q3985, the drain of the sixth reset control NMOS transistor MN66 is connected to the drain of the sixth switching PMOS transistor MP66 and the upper plate of the sixth capacitor C6, the connection node V6 between the drain of the sixth reset control NMOS transistor MN66 and the upper plate of the sixth capacitor C6 serves as the pulse width information output terminal, and the lower plate of the sixth capacitor C6 and the source of the sixth reset control NMOS transistor MN66 are both grounded.

As shown in fig. 3, the seventh-stage pulse width extraction unit includes a seventh pulse width test NMOS transistor MN7, a seventh pulse width test PMOS transistor MP7, a seventh switch PMOS transistor MP77, a seventh reset control NMOS transistor MN77 and a seventh capacitor C7, a gate of the seventh pulse width test NMOS transistor MN7 is connected to the data output terminal Q7 of the seventh-stage D flip-flop in the delay level generation array, a gate of the seventh pulse width test PMOS transistor MP7 is connected to the data output terminal Q8 of the eighth-stage D flip-flop in the delay level generation array, a source of the seventh pulse width test PMOS transistor MP7 is connected to the power supply VCC, a drain of the seventh pulse width test PMOS transistor MP7 is connected to a drain of the seventh pulse width test NMOS transistor MN7, a source of the seventh pulse width test NMOS transistor MN7 is connected to a source of the seventh switch PMOS transistor MP77, a gate of the seventh switch PMOS transistor MP77 is used as the driving terminal of the pulse width extraction unit, and a drain of the seventh reset control NMOS transistor MN77 is used as the charge drain terminal Q1B, the drain of the seventh reset control NMOS transistor MN77 is connected to the drain of the seventh switching PMOS transistor MP77 and the upper plate of the seventh capacitor C7, the connection node V7 between the drain of the seventh reset control NMOS transistor MN77 and the upper plate of the seventh capacitor C7 serves as the pulse width information output terminal, and the lower plate of the seventh capacitor C7 and the source of the seventh reset control NMOS transistor MN77 are both grounded.

As can be seen from fig. 3, according to the gate control manner of the first pulse width test NMOS transistor MN1 and the first pulse width test PMOS transistor MP1, charge can be injected into the first capacitor C1 only when the data output terminal Q1 of the first stage D flip-flop is at a high level and the data output terminal Q2 of the second stage D flip-flop is at a low level, as can be seen from fig. 5, a time period from t0 to t1 satisfies the above state, and at the same time, the gate of the first switch PMOS transistor MP11 is controlled by an UP signal, and in a time interval when both the first pulse width test NMOS transistor MN1 and the first pulse width test PMOS transistor MP1 are turned on, only when the signal UP is at a low level, charge can be injected into the first capacitor C1, and the voltage carried by both ends of the first capacitor C1 is in direct proportion to the time of injecting the charge, so as to achieve the function of extracting the width information of the first low level of the signal; similarly, when the output terminal Q2 of the D flip-flop of the second stage outputs a high level and the data output terminal Q3 of the D flip-flop of the third stage is a low level, that is, the time period from t1 to t2 in fig. 5 is taken as the extraction interval of the second stage, when the UP signal keeps a low level in this interval, the charge can be injected into the second capacitor C2, the voltage carried at the two ends of the second capacitor C2 is proportional to the time of injecting the charge, so as to extract the width information of the second low level of the UP signal; similarly, when the output Qn of the nth stage D flip-flop outputs a high level, the data output Qn +1 of the (n + 1) th stage D flip-flop outputs a low level, and the UP signal is a low level, the pulse width extraction units of the subsequent stages extract corresponding low level width information in the corresponding extraction intervals, and convert the low level width information into voltage information, which is respectively outputted from the pulse width information output terminals V1, V2, V3, V4, V5, V6, and V7 of the pulse width extraction units of the respective stages. When the signal EN changes from low level to high level, the data output terminal Q1 of the first stage D flip-flop outputs low level, and the inverted output terminal Q1B outputs high level, so as to turn on the reset control NMOS transistor in the pulse width extraction unit of each stage, and further release the charge on the capacitor, thereby ensuring that the voltage extraction from V1 to V7 is not affected. When the data output terminal Q1 of the first stage D flip-flop outputs a low level and changes to a high level, the inverted output terminal Q1B outputs a high level, ending the charge discharging process until the next phase-locked loop restarts. In this embodiment, according to the delay signal output by each adjacent cascaded D flip-flop of the delay level generation array, the corresponding low level width information on the extraction interval of each level of pulse width extraction unit is determined and stored in the capacitor corresponding to the one-level pulse width extraction unit, and the voltage magnitude relation of each capacitor in the pulse width extraction unit is adjusted by changing the capacitance ratio of the adjacent two-level pulse width extraction units, so that the level extraction control circuit controls the time of switching on and off the current of the current injection switch module, and the increase of the phase-locked time caused by the delay fed back by the phase-locked loop can be counteracted, so that the control voltage output by the low-pass filter tends to be stable, and the locking time of the phase-locked loop is shortened.

It should be noted that, in the 7 cascaded pulse width extraction units, a ratio between capacitances of two adjacent cascaded pulse width extraction units is a preset value, and the preset value is smaller than 1. The capacitance relationship satisfies Cn × K ═ Cn +1 (n: number of stages), and K is determined according to the actual operating state of the specific pll, and is between about 0.8 and 1, where K is preferably 0.9 in this embodiment. This preferred embodiment is advantageous for controlling the current injection switching module to cut off the injection of charge to the capacitor side of the low-pass filter while compensating for an increase in the phase-lock time due to the feedback loop delay.

The control signal generation module comprises n comparators, an OR logic circuit and a switch D trigger; the n comparators start from the pulse width extraction unit of the second stage according to the cascade sequence in the pulse width extraction array, the positive and negative input ends of each comparator are respectively connected with the pulse width information output ends of the adjacent cascade pulse width extraction units, the negative input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with the smaller stage number, and the positive input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with the larger stage number; wherein, the OR logic circuit comprises a plurality of OR gates or corresponding combinational logic circuits. As shown in fig. 6, the control signal generating module includes 5 comparators, a five-input or gate, and a switch D flip-flop; the negative input end of the comparator cmp1 is connected with the pulse width information output end V2 of the pulse width extraction unit of the second stage, and the positive input end is connected with the pulse width information output end V3 of the pulse width extraction unit of the third stage; the negative input end of the comparator cmp2 is connected with the pulse width information output end V3 of the pulse width extraction unit at the third stage, and the positive input end is connected with the pulse width information output end V4 of the pulse width extraction unit at the fourth stage; the negative input end of the comparator cmp3 is connected with the pulse width information output end V4 of the pulse width extraction unit at the fourth stage, and the positive input end is connected with the pulse width information output end V5 of the pulse width extraction unit at the fifth stage; the negative input end of the comparator cmp4 is connected with the pulse width information output end V5 of the pulse width extraction unit of the fifth stage, and the positive input end is connected with the pulse width information output end V6 of the pulse width extraction unit of the sixth stage; the negative input end of the comparator cmp5 is connected with the pulse width information output end V6 of the pulse width extraction unit of the sixth stage, and the positive input end is connected with the pulse width information output end V7 of the pulse width extraction unit of the seventh stage; the output ends of the comparator cmp1, the comparator cmp2, the comparator cmp3, the comparator cmp4 and the comparator cmp5 are all connected to the input end of the five-input or gate, the output end ctr of the five-input or gate is connected to the clock end of the switch D flip-flop, the data input end D and the reset end CLR are both connected to the enable control end EN, and the data output end Q of the switch D flip-flop is used as the control output end ctr _ kep of the level extraction control circuit.

The control signal generation module is used for sequentially comparing the voltage value relations of V2, V3, V4, V5, V6 and V7 through the comparator and carrying out control signal cut-off output at a proper time. In this embodiment, the proportions of MOS transistors in the comparator cmp1, the comparator cmp2, the comparator cmp3, the comparator cmp4 and the comparator cmp5 are adjusted, as shown in fig. 7, so that before the first rising edge of the UP signal arrives, that is, before the time t0, the positive and negative inputs of the comparator are both zero, and therefore when the phase-locked loop starts to operate, the outputs of the positive and negative input terminals of the comparator are all 0, that is, V1, V2, V3, V4, V5, V6 and V7 are all 0, and the outputs of the comparator are all 0. At the time t1, the second rising edge of the signal UP comes, and since the low-level width extraction voltage V1 of the pulse width extraction unit of the first stage is in the transition region between the frequency adjustment phase and the phase adjustment phase, in the transition region, since the low-level width of the signal UP for reflecting the phase relationship between the feedback clock signal fbk and the reference clock signal fref is unstable, the comparator that does not send the pulse width information to the control signal generation module participates in the comparison.

It should be noted that when the output signals of the comparator cmp1, the comparator cmp2, the comparator cmp3, the comparator cmp4, and the comparator cmp5 are at a high level, the output ctr of the five-input or gate is at a high level, otherwise, the output ctr of the five-input or gate is at a low level. As shown in fig. 7, the voltage V2 rises at time t2, while the voltage V3 remains low, and since the negative input terminal of the comparator cmp1 is connected to V2 and the positive input terminal of the comparator cmp1 is connected to V3, the output signal of the comparator cmp1 is 0 at this time V3 is 0. With the arrival of the fourth rising edge of the signal UP, the voltage V3 rises at the time t3, the voltage V3 changes, at this time, the voltage V2 is still greater than the voltage V3, the output of the comparator cmp1 is still 0, which also means that the low-level width of the signal UP is in a trend of keeping decreasing in the time period from t1 to t 3; if the voltage V2 is less than the voltage V3, the comparator cmp1 output is high, which also means that the low-level width of the signal UP shows an increasing tendency as a whole in the period from t1 to t3 (not shown in fig. 7). During the time period from t2 to t3, the negative input of the comparator cmp2 is at voltage V3, and the voltage V4 applied to the positive input of the comparator cmp2 remains zero, so the comparator cmp2 output is zero. As the fifth rising edge of the signal UP comes, the voltage V4 rises at the time t4, and the comparator cmp2 compares the magnitudes of the voltage V3 and the voltage V4 in the method of the foregoing embodiment, thereby determining whether the low-level width of the signal UP in the time period t2 to t4 increases or decreases. Similarly, the comparator cmp3, the comparator cmp4, and the comparator cm5 each perform comparison output in accordance with the foregoing principle.

It should be noted that when the output of the comparator cmp2 goes high, it is necessary to ensure that the output of the control signal generation block goes high, and the comparator cmp3, the comparator cmp4, and the comparator cmp5 continue to perform comparison output based on the voltage signal obtained by delaying, but the output result of the control signal generation module is not influenced, but under different process conditions and the like, the performance of the comparator is different, it may cause the output of the comparator to oscillate, causing the output ctr of the five-input or-gate to oscillate, or, due to long-time operation, the voltage released by the pulse width information output end of the pulse width extraction unit may be changed due to the leakage of the charge in the capacitor of the pulse width extraction unit, causing the output of the comparator to change, causing the signal ctr at the output of the five-input or gate to change. Therefore, the output end of the five-input or gate needs to be connected to the clock end of the switch D flip-flop, the data input end D of the switch D flip-flop is connected to the EN signal, after the phase-locked loop starts to operate, when the first rising edge of the output end signal ctr of the five-input or gate comes, the output end of the switch D flip-flop changes from low level to high level, and in the following operation process, even if the clock end of the switch D flip-flop still comes, because the signal EN connected to the data input end D of the switch D flip-flop keeps high level, the signal ctr _ kep output by the data output end Q of the switch D flip-flop does not change, and still remains high level, thereby ensuring that the data output end of the switch D flip-flop keeps the level state of the data input end unchanged under the condition that the pulse width information output end outputs the edge jump signal, thereby improving the reliability of the phase-locked accelerating circuit.

In summary, the pulse width extraction array extracts low level width information of the signal UP in seven different time periods, converts the low level width information into voltage values V1 to V7 through internal capacitors, determines the conduction time of the current injection switch module and the time when the phase of the reference clock signal fref input by the phase frequency detector is synchronized with the phase of the feedback clock signal fbk (determined as a stable phase lock state) according to the low level width change information of the signal UP, and sends a reliable signal ctr _ kep through the control signal generation module to control the current injection switch module. As shown in fig. 7, before time t5, the signal ctr remains low, which indicates that the pulse width information output terminals of the adjacent cascaded pulse width extraction units compared by the comparators cmp1, cmp2 and cmp3 are all 0; in the adjacent cascaded pulse width extraction units, the voltage Vn +1 of the pulse width information output end of the pulse width extraction unit with the larger stage number is not larger than the pulse width information output end Vn of the pulse width extraction unit with the smaller stage number, so that the control signal ctr is not enough to be inverted to the high level, which indicates that the low level width change state of the signal UP is still in the reduction stage. After the voltage V6 is increased from the low level at time t6, the voltage V6 is greater than the voltage V5, the output of the comparator cmp4 is at the high level, the output end signal ctr of the five-input or gate outputs the high level, the low level width of the signal UP continuously increases until the reference clock signal fref is equal to the feedback clock signal fbk, that is, after time t7, the low level width of the signal UP is close to the length of one period of the signal UP in the time period, and thereafter, the reference clock signal fref and the feedback clock signal fbk are adjusted based on the feedback delay characteristic of the phase-locked loop until the phases of the two start to change synchronously. The low pass filter is used for controlling the control voltage of the voltage-controlled oscillator, which does not need to be raised, but tends to be stable, so that the current injection switch module is cut off by the signal ctr to inject charges into the capacitance end VC _ DN of the low pass filter, and it should be noted that the current injection switch module is not only controlled by the signal ctr, but also needs to consider the level condition of the signal UP, that is, in the stage that the signal ctr is at a low level, the first zero PMOS transistor MP10 of the current injection switch module is turned on, but also needs to consider whether the signal UP connected to the gate of the second NMOS zero transistor MN20 of the current injection switch module is at a high level. Although the first zero PMOS transistor MP10 is turned on, the signal UP input by the gate of the second zero NMOS transistor MN20 is at a low level, and the current injection switch module still cannot inject charges into the capacitor terminal VC _ DN of the low pass filter, so the current injection switch module is in a phase adjustment phase, and performs current injection in a step manner under the control of the signal UP. When the signal ctr _ kep output by the data output end of the switch D flip-flop is at a high level, the switching state of the second zero NMOS transistor MN20 does not affect the low pass filter. When the phase-locked loop is restarted, the output of the switch D trigger returns to the low level again through the reset setting of the switch D trigger until the control signal ctr becomes the high level again.

In this embodiment, the time for turning off the current injection switch module of the control signal ctr may be changed by changing a proportional relationship among the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7, that is, decreasing the proportional parameter K may control the current injection switch module to turn off in advance, and increasing the proportional parameter K may control the current injection switch module to turn off in delay, so that the time for changing the signal ctr _ kep output by the control signal generation module to a high level is finely adjusted by changing the value K, an increase in phase-locked time due to a delay of a phase-locked loop feedback may be cancelled, and an error between VC when the phase-locked acceleration circuit is turned off and VC when the phase-locked acceleration circuit is finally stabilized may be minimized, thereby minimizing the lock time. The capacitance relation satisfies Cn × K ═ Cn +1 (n: number of stages), and the value of K is determined according to the actual operating state of the specific pll, which is between about 0.8 and 1, and K in this embodiment is preferably 0.9. As shown in fig. 7, the capacitance ratio between the seventh capacitor C7 and the sixth capacitor C6 can be individually adjusted to ensure that the signal ctr _ kep output by the control signal generation module must complete the turn-off of the current injection switch module within the time period from t6 to t7, thereby ensuring the stability of the phase-locked acceleration circuit. In this embodiment, the time for turning off the current injection switch module by the level extraction control circuit is advanced by reducing the ratio K between the capacitors, and the time for turning off the current injection switch module by the level extraction control circuit is delayed by increasing the ratio between the capacitors, so as to offset the increase of the phase-locking time caused by the delay of the loop feedback of the phase-locked loop.

The simulation through the EDA tool can obtain that fig. 8 is a waveform diagram of the charging voltage VC _ DN of the filter capacitor of the low-pass filter in the conventional phase-locked loop system and the voltage VC _ out of the signal output end of the low-pass filter before and after phase locking, and fig. 9 is a waveform diagram of the capacitor input end VC _ DN of the low-pass filter and the voltage VC _ out of the signal output end of the low-pass filter before and after phase locking in the phase-locked loop system provided by the embodiment of the present invention. As shown in fig. 8 and fig. 9, from the start of the phase-locked loop system, that is, t is equal to 0, VC _ out and VC _ DN both increase from 0, and the increase and increase rate of VC _ out at each time node are both greater than that of VC _ DN, but VC _ out and VC _ DN both change in the same trend, and VC _ out increases and then decreases to be stable during oscillation. The settling time of VC _ out and VC _ DN in fig. 9 is approximately 7us, and the settling time of VC _ out and VC _ DN in fig. 8 is approximately 28us, and the phase-lock accelerating circuit accelerates the phase-lock process, and compared with the conventional pll structure, the phase-lock accelerating circuit provided by this embodiment shortens the phase-lock settling time of the pll system in which it is located by about 75%.

Based on aforementioned phase-locked accelerating circuit, the utility model discloses still provide a phase-locked loop system, this phase-locked loop system includes aforementioned phase-locked accelerating circuit, and the inside relevant phase-locked accelerating's of this phase-locked loop system technical features can refer to aforementioned embodiment, so, no longer give consideration to repeatedly.

As shown in fig. 1, the phase-locked loop system includes: the phase frequency detector is used for detecting the frequency difference and the phase difference of a reference clock signal fref input by an external configuration and an internal feedback clock signal fbk and generating a pulse control signal until the phases of the reference clock signal fref and the internal feedback clock signal fbk change synchronously. And the charge pump is used for generating charging current and discharging current according to the pulse control signal output by the phase frequency detector. And the low-pass filter is used for converting the current control signal output by the charge pump into control voltage and filtering high-frequency noise. And the voltage-controlled oscillator controls the frequency of the output oscillation signal according to the control voltage output by the low-pass filter, increases the oscillation frequency of the output signal when the control voltage is increased, decreases the oscillation frequency of the output signal when the control voltage is decreased, and maintains the oscillation frequency of the output signal fout at a constant value when the control voltage is stable. A frequency divider divides the output signal fout of the voltage controlled oscillator to generate a feedback clock signal fbk which is input to the phase frequency detector. In the phase-locked loop system, a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider are sequentially connected to form a feedback loop. The phase-locked loop system further comprises: the phase-locked accelerating circuit in the foregoing embodiment includes a level extraction control circuit and a current injection switch module, and the phase-locked accelerating circuit integrates a comparator, a sequential logic circuit and a combinational logic circuit, and compares low level widths of a control signal UP output from the phase frequency detector at different phase-locked adjustment stages, where an enable control signal EN of the phase-locked accelerating circuit generates a series of delay signals through a delay level generation array of the level extraction control circuit, and generates a level extraction interval through the pulse width extraction array, and low level width information of the pulse width extraction array reflecting the signal UP is extracted and input to the control signal generation module, and the current injection switch module is switched off to inject charges into a capacitor terminal VC _ DN of the low-pass filter at a phase-locked stable time.

The level extraction control circuit controls the current injection switch module of the phase-locked accelerating circuit to inject charges into the low-pass filter according to the duty ratio change condition of the inverse signal of the control signal output by the phase frequency detector until the phase of the reference clock signal input by the phase frequency detector is synchronous with the phase of the feedback clock signal, so that the phase-locked accelerating circuit shortens the phase-locked time of the feedback loop. In this embodiment, n +3 delay levels are obtained by delaying an external enable control signal, corresponding pulse width information is extracted from a control signal, which is output by a phase frequency detector and reflects a phase difference between a reference clock signal and a feedback clock signal, and is used as a voltage signal for injection switch control in the current injection switch module, where the pulse width information is used as a basis for level extraction, and a switch D flip-flop ensures reliability of a conduction result of the current injection switch module. Therefore, the phase locking time of the phase-locked loop system is shortened, the stability of the control voltage output by the low-pass filter is ensured to be unchanged, the system characteristics, the transfer function and the noise performance are not changed, and the device parameters and the loop parameters are not required to be changed when the phase-locked loop system is applied to other phase-locked loop systems.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, it should be understood by those skilled in the art that: the invention can be modified or equivalent substituted for some technical features; without departing from the spirit of the present invention, it should be understood that the scope of the claims is intended to cover all such modifications and variations.

Claims (7)

1. A phase-locked accelerating circuit based on level width extraction is disclosed, and the phase-locked loop applicable to the phase-locked accelerating circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, wherein the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the frequency divider are sequentially connected to form a feedback loop;

the level extraction control circuit is provided with a driving input end, an enabling control end and a control output end; the current injection switch module is provided with a current stepping control end and a current injection control end; the enable control end of the level extraction control circuit is connected with an external enable signal source; the control output end of the level extraction control circuit is connected with the current injection control end of the current injection switch module, and meanwhile, the current stepping control end of the current injection switch module and the driving input end of the level extraction control circuit are both connected with a preset control signal output end of the phase frequency detector, wherein a signal output by the preset control signal output end is an inverse signal of a control signal which is output by the phase frequency detector and is used for controlling a charge pump to perform current injection;

the signal input end of the low-pass filter is connected with the signal output end of the charge pump, the capacitance input end of the low-pass filter is connected with the signal output end of the current injection switch module, wherein the capacitance input end of the low-pass filter is as follows: in the resistor-capacitor series branch inside the low-pass filter, the connection node of the resistor and the capacitor connected in series is connected.

2. The phase-locked boost circuit of claim 1, wherein the current injection switch module comprises: the power supply comprises a power supply source, a first zero NMOS tube, a second zero NMOS tube and a first zero PMOS tube;

the source electrode of the first zero NMOS tube is connected with the drain electrode of the second zero NMOS tube, the grid electrode of the first zero NMOS tube is connected with the drain electrode of the first zero NMOS tube, and the drain electrode of the first zero NMOS tube is connected with a power supply, so that the first zero NMOS tube is used as a current-limiting MOS tube;

the drain electrode of the second zero NMOS tube is connected with the source electrode of the first zero NMOS tube, the source electrode of the second zero NMOS tube is connected with the source electrode of the first zero PMOS tube, the grid electrode of the second zero NMOS tube is connected with the preset control signal output end and serves as a current stepping input control end of the current injection switch module, and the current stepping input control end is used for changing the conduction condition of the second zero NMOS tube according to the jumping state of an output signal of the preset control signal output end so as to realize stepping current injection of the current injection switch module;

the source electrode of the first zero PMOS tube is connected with the source electrode of the second zero NMOS tube, and the grid electrode of the first zero PMOS tube is connected with the control output end of the level extraction control circuit and serves as the current injection control end of the current injection switch module; and the drain electrode of the first zero PMOS tube is used as the signal output end of the current injection switch module and is connected with the capacitor input end of the low-pass filter.

3. The phase-locked accelerating circuit as claimed in claim 1 or 2, wherein the level extraction control circuit comprises a delay level generating array, a pulse width extracting array and a control signal generating module;

the driving input end is connected with a clock input end of the delay level generating array, and the enabling control end is connected with a data input end of the delay level generating array;

the delay level generation array internally comprises n +3 cascaded D triggers, and n +3 data output ends are correspondingly arranged respectively, wherein the D trigger connected with the enabling control end is a first-stage D trigger, and the stage number of the cascaded pulse width extraction unit is the same as the relatively small stage number of two connected adjacent cascaded D triggers;

the pulse width extraction array comprises n +2 cascaded pulse width extraction units, each pulse width extraction unit is provided with 2 pulse input ends, 1 charge discharge control end, 1 driving end and 1 pulse width information output end, adjacent cascaded pulse width extraction units have a common pulse input end, and the driving ends of the n +2 cascaded pulse width extraction units are connected with a clock input end arranged in the delay level generation array;

the data output ends of two adjacent cascaded D triggers in the delay level generating array are correspondingly connected to two pulse input ends of pulse width extracting units with matched series of the pulse width extracting array;

in the delay level generating array, the inverted output end of the D trigger connected with the enabling control end is connected with the charge discharge control end of each pulse width extraction unit;

the positive and negative input ends of each comparator are respectively connected with the pulse width information output ends of adjacent cascaded pulse width extraction units, each two adjacent comparators only have one input end connected with the pulse width information output end of the same pulse width extraction unit, the input ends of the two adjacent comparators connected with the pulse width information output end of the same pulse width extraction unit have different attributes, the input ends of the two non-adjacent comparators are not connected with the pulse width information output end of the same pulse width extraction unit, and the number of stages to which the pulse width extraction unit connected with the positive input end of the comparator belongs is higher than the number of stages to which the pulse width extraction unit connected with the negative input end of the same comparator belongs.

4. The phase-locked turbo circuit as claimed in claim 3, wherein, in the delay level generating array, the connection structure of n +3 cascaded D flip-flops is:

the data input end of the first-stage D trigger is connected with the enabling control end;

in two adjacent cascaded D triggers, the data input end of the D trigger of the next stage is connected with the data output end of the D trigger of the previous stage;

the clock end of each stage of D trigger is connected with the driving input end, and the reset end of each stage of D trigger is connected with the enabling control end.

5. The phase-locked accelerating circuit as claimed in claim 3, wherein the pulse width extraction array comprises a power supply and n +2 cascaded pulse width extraction units, each of which comprises a pulse width test NMOS transistor, a pulse width test PMOS transistor, a switch PMOS transistor, a reset control NMOS transistor and a capacitor;

in the pulse width extraction unit of the nth stage, the gate of a pulse width test NMOS tube is connected to the data output end of the D flip-flop of the nth stage in the delay level generation array, and the gate of a pulse width test PMOS tube is connected to the data output end of the D flip-flop of the (n + 1) th stage in the delay level generation array, where the stages of the D flip-flop of the nth stage and the pulse width extraction unit of the nth stage are equal, and the D flip-flop of the (n + 1) th stage and the D flip-flop of the nth stage are in an adjacent cascade connection relationship, so as to satisfy the connection relationship that the data output ends of two adjacent cascade D flip-flops in the delay level generation array are correspondingly connected to two pulse input ends of the pulse width extraction unit of the pulse width extraction array with matching stages, where the gate of the pulse width test NMOS tube and the gate of the pulse width test PMOS tube are respectively used;

in each level of pulse width extraction unit, the source electrode of a pulse width test PMOS tube is connected with a power supply, the drain electrode of the pulse width test PMOS tube is connected with the drain electrode of a pulse width test NMOS tube, the source electrode of the pulse width test NMOS tube is connected with the source electrode of a switch PMOS tube, the grid electrode of the switch PMOS tube is used as the drive end of the pulse width extraction unit, the grid electrode of a reset control NMOS tube is used as the charge discharge control end, the drain electrode of the reset control NMOS tube is simultaneously connected with the drain electrode of the switch PMOS tube and the upper polar plate of a capacitor, the connection node of the drain electrode of the reset control NMOS tube and the upper polar plate of the capacitor is used as the pulse width information output end, and the lower;

the gates of the switch PMOS tubes of all the cascaded pulse width extraction units are connected to the clock input end, and the gates of the reset control NMOS tubes of all the cascaded pulse width extraction units are connected to the inverted output end of the first-stage D trigger.

6. The phase-locked accelerating circuit as claimed in claim 3, wherein the control signal generating module comprises n comparators, or logic circuits and a switch D flip-flop;

the n comparators start from the pulse width extraction unit of the second stage according to the cascade sequence in the pulse width extraction array, the positive and negative input ends of each comparator are respectively connected with the pulse width information output ends of the pulse width extraction units of the adjacent cascade, the negative input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with relatively small number of stages in the pulse width extraction units of the adjacent cascade, and the positive input end of each comparator is connected with the pulse width information output end of the pulse width extraction unit with relatively large number of stages in the pulse width extraction units of the adjacent cascade;

the signal output ends of the n comparators are respectively connected to n input ends of an OR logic circuit, the output end of the OR logic circuit is connected to a clock end of a switch D trigger, a data input end and a reset end of the switch D trigger are both connected with the enabling control end, and a data output end of the switch D trigger is used as a control output end of the level extraction control circuit;

wherein, the OR logic circuit comprises a plurality of OR gates or corresponding combinational logic circuits.

7. A phase-locked loop system comprising:

the phase frequency detector is used for detecting the frequency difference and the phase difference of an input clock signal and a feedback clock signal and generating a pulse control signal;

the charge pump is used for generating charging current and discharging current according to the control signal output by the phase frequency detector;

the low-pass filter is used for converting the current control signal output by the charge pump into control voltage and filtering high-frequency noise;

the voltage-controlled oscillator is used for controlling the frequency of an output signal of the voltage-controlled oscillator according to the control voltage output by the low-pass filter, increasing the oscillation frequency of the output signal when the control voltage is increased, decreasing the oscillation frequency of the output signal when the control voltage is decreased, and keeping the oscillation frequency of the output signal at a constant value when the control voltage is stable;

the frequency divider is used for dividing the frequency of the output signal of the voltage-controlled oscillator to generate a feedback clock signal of the phase frequency detector;

the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the frequency divider are sequentially connected to form a feedback loop;

it is characterized by also comprising: a phase locked speed up circuit as claimed in any one of claims 1 to 6.

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