TWI630799B - Phase detector and clock and data recovery device - Google Patents

Abstract

A clock and data recovery device includes a clock signal generator and a phase detector. The clock signal generator generates a clock signal according to the control signal, and the control signal is used to adjust a frequency of the clock signal. The phase detector generates the control signal based on the clock signal and the input data. When the phase detector determines that a transition occurs between an nth symbol and an (n+1)th symbol, 1≦n≦(N-1), n is a positive integer, and the definition of the transition state is high or low. a logic level conversion, the phase detector determines that an integration time of the nth symbol is greater than an integration time of the (n+1)th symbol, and the phase detector adjusts the control signal to reduce the clock signal. The frequency, the integration time of the nth symbol is from the nth sampling edge of the clock signal to the transition point between the two symbols, and the integration time of the (n+1)th symbol is from the second The transition point between the symbols is to the (n+1)th sampling edge of the clock signal.

Description

Phase detector and clock and data recovery device

The invention relates to a device, in particular to a phase discriminator and clock and data recovery device without additional edge sampling.

The existing clock and data recovery (Clock and Data Recovery, hereinafter referred to as: CDR) technology needs to obtain the information of the conversion edge of the input data stream, and the phase detector used by it needs to oversample the received data stream by 2 times (using 2 One clock edge samples the same symbol), that is, the clock sampling frequency = 2 × data transfer rate (data rate), resulting in a large power consumption. In addition, in high-speed design, the same-origin multi-phase clock signal is usually used for data sampling (when locked, the data sampling point is located in the middle of the symbol) and edge sampling (when locked, the edge sampling point is located in the middle of the data conversion edge Point), there will be a problem of phase mismatch, so how to reduce power consumption and solve the problem of phase mismatch is the future research direction.

Therefore, the object of the present invention is to provide a clock and data recovery device that solves the above problems.

Therefore, the clock and data recovery device of the present invention includes a clock signal generator and a phase detector.

The clock signal generator receives a control signal and generates a clock signal according to the control signal. The control signal is used to adjust a frequency of the clock signal.

The phase detector receives an input data having the first to Nth symbols, N ≧ 2, N is a positive integer, and is electrically connected to the clock signal generator to receive the clock signal, and according to the clock signal and the input The data generates the control signal.

When the phase detector judges that a transition occurs between an n-th symbol and a (n + 1) -th symbol, 1 ≦ n ≦ (N-1), n is a positive integer, and the definition of transition is high or low In the logic level conversion, the phase detector determines that an integration time of the nth symbol is greater than an integration time of the (n + 1) th symbol, then the phase detector adjusts the control signal to reduce the clock signal The frequency, the integration time of the nth symbol is the transition point from the nth sampling edge of the clock signal to the two symbols, and the integration time of the (n + 1) th symbol is from the The transition point between two symbols to the (n + 1) th sampling edge of the clock signal.

The phase discriminator includes a data sampling circuit, an integration comparison circuit, and a logic circuit.

The data sampling circuit receives an input data having the first to Nth symbols, N ≧ 2, N is a positive integer, and is electrically connected to the clock signal generator to receive the clock signal, and to the input data according to the clock signal Sampling is performed to generate the first to N-th symbols.

The integration comparison circuit receives the input data and the clock signal, and integrates the n-th symbol and the (n + 1) -th symbol of the input data, and compares the n-th symbol and the (n + 1) -th symbol ) The integration time of the symbol to generate a digital signal, the digital signal is used to indicate one of the nth symbol and the (n + 1) th symbol.

The logic circuit electrically connects the comparator and the data sampling circuit to receive the digital signal from the comparator and the n-th symbol and the (n + 1) -th symbol from the data sampling circuit, and determine the digital The signal matches the n-th symbol or the (n + 1) -th symbol to generate the control signal. When the digital signal matches the n-th symbol, it indicates that the n-th sampling edge is ahead of the n-th symbol. At the middle point, the control signal indicates a reduction in frequency. When the digital signal matches the (n + 1) th symbol, indicating that the nth sampling edge lags behind the midpoint of the nth symbol, the control signal indicates an increase in frequency.

The effect of the present invention is that there is no need for additional edge sampling of the input data, so that the power consumption required by the entire CDR circuit is significantly reduced.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same number.

1 and 2, an embodiment of the clock and data recovery device of the present invention includes a clock signal generator 1 and a phase detector 2.

The clock signal generator 1 receives a control signal (UP, DN), and generates a clock signal (with multiple sampling edges respectively ... CKn, CKn + 1 ..., 1 ≦ n ≦ (N-1), based on the control signal N ≧ 2, N and n are positive integers), the control signal is used to adjust a frequency (increase, decrease or maintain frequency) of the clock signal. The clock signal generator 1 includes a charge pump 10, a filter 11, and an oscillator 12.

The charge pump 10 receives the control signal, and generates a current (Icp) according to the control signal.

The filter 11 is electrically connected to the charge pump 10 to receive the current, and converts the current into a control voltage (V _CTRL ). When the current flows into the filter 11, the control voltage increases, and when the current flows out of the filter 11 , The control voltage decreases.

The oscillator 12 is used to generate the clock signal, electrically connected to the filter 11 to receive the control voltage, and adjust the frequency of the clock signal according to the control voltage, the frequency being proportional to the control voltage.

The phase detector 2 receives an input data (Data) having the first to Nth symbols, N ≧ 2, N is a positive integer, and is electrically connected to the clock signal generator 1 to receive the clock signal, and according to the clock The signal and the input data generate the control signal (UP, DN).

As shown in Figure 2, (UP = 0, DN = 1) indicates that the phase of the clock signal is ahead, (UP = 1, DN = 0) indicates that the phase of the clock signal is behind, and the sampling edges of the clock signal CKn, CKn + 1 are for Indicates the sequence of the corresponding sampled symbols (Dn, Dn + 1).

As shown in FIG. 3, the phase detector 2 includes a data sampling circuit 3, an integration comparison circuit 4, and a logic circuit 5.

The data sampling circuit 3 receives the input data, and is electrically connected to the clock signal generator to receive the clock signal, and samples the input data according to the clock signal to generate the first to N-th symbols.

The integration comparison circuit 4 receives the input data and the clock signal, and integrates the n-th symbol (Dn) and the (n + 1) -th symbol (Dn + 1) of the input data, and compares the n-th symbol The integration time of the symbol D _n and the (n + 1) th symbol D _{n + 1} to generate a digital signal for indicating the nth symbol D _n and the (n + 1) th One of the symbols D _{n + 1} .

As shown in FIG. 4, the integration comparison circuit 3 includes an integrator 6 and a comparator 7.

The integrator 6 receives the input data and is electrically connected to the clock signal generator 1 to receive the clock signal, and from the nth sampling edge CK _{n of} the clock signal to the (n + 1) th sampling edge CK _{n +} Between ₁ , the n-th symbol D _n of the input data and the (n + 1) _-th symbol D _{n + 1} are integrated to obtain an integration result.

The comparator 7 is electrically connected to the integrator 6 to receive the integration result, and compares the integration result with a threshold to output a digital signal. If the integration result is greater than the threshold, the digital signal is a first logic (1 ), If the integration result is less than the critical value, the digital signal is a second logic (0).

The logic circuit 5 is electrically connected to the comparator 6 and the data sampling circuit 6 to receive the digital signal from the comparator and the nth symbol and the (n + 1) th symbol from the data sampling circuit, and It is judged that the digital signal matches the nth symbol or the (n + 1) th symbol to generate the control signal. When the digital signal conforms to the n-th symbol, indicating that the n-th sampling edge leads the midpoint of the n-th symbol, the control signal indicates a reduction in frequency; when the digital signal corresponds to the (n + 1) -th symbol , Indicating that the nth sampling edge lags behind the midpoint of the nth symbol, then the control signal indicates an increase in frequency.

Refer to Table 1 for the relationship between the signals in Figure 1 and Figure 3.         <TABLE border = "1" borderColor = "# 000000" width = "85%"> <TBODY> <tr> <td> D <sub> n </ sub> </ td> <td> E <sub> n </ sub> </ td> <td> D <sub> n + 1 </ sub> </ td> <td> UP </ td> <td> DN </ td> <td> Icp </ td> <td> VCTRL </ td> <td> fo </ td> </ tr> <tr> <td> 0 </ td> <td> 0 </ td> <td> 0 </ td> <td> 0 </ td> <td> 0 </ td> <td> 0 </ td> <td> unchanged </ td> <td> unchanged </ td> </ tr> <tr> <td> 0 </ td> <td> 0 </ td> <td> 1 </ td> <td> 0 </ td> <td> 1 </ td> <td>-</ td> <td> down </ td> <td> down </ td> </ tr> <tr> <td> 0 </ td> <td> 1 </ td> <td> 1 </ td> <td> 1 </ td> < td> 0 </ td> <td> + </ td> <td> rise </ td> <td> rise </ td> </ tr> <tr> <td> 1 </ td> <td> 0 </ td> <td> 0 </ td> <td> 1 </ td> <td> 0 </ td> <td> + </ td> <td> rise </ td> <td> rise </ td> </ tr> <tr> <td> 1 </ td> <td> 1 </ td> <td> 0 </ td> <td> 0 </ td> <td> 1 </ td> < td>-</ td> <td> down </ td> <td> down </ td> </ tr> <tr> <td> 1 </ td> <td> 1 </ td> <td> 1 </ td> <td> 0 </ td> <td> 0 </ td> <td> 0 </ td> <td> unchanged </ td> <td> unchanged </ td> </ tr> </ TBODY> </ TABLE> Table 1       

The parameter Icp is the current output by the charge pump 10. When the current polarity is positive (+), it indicates that the charge pump 10 is injecting current into the filter 11. When the current polarity is negative (−), it indicates that the current is drawn from the filter 11. The parameter V _CTRL is the control voltage of the oscillator 12. The parameter fo is the frequency of the clock signal. E _n is a parameter integral digital signal comparison circuit 4 outputs.

5, the integration time of the n-th symbol D _n T _n from the n-th sampling edge of the clock signal CK to the transient _n points between the two symbols of the (n + 1) The integration time Tn _{+ 1} of the symbol is from the transition point between the two symbols to the (n + 1) th sampling edge CKn _{+ 1 of} the clock signal.

When the phase detector 2 determines that there is no transition between an n-th symbol D _n and a (n + 1) -th symbol D _{n + 1} , the control signal maintains the frequency of the clock signal, that is, the input When no high or low potential transition occurs in the data, the control signals UP and DN are always 0. It is also worth noting that before unlocking, both the output data and the recovered clock signal are incorrect.

When the phase detector 2 determines that a transition occurs between an n-th symbol D _n and an (n + 1) _-th symbol D _{n + 1 of the} input data, 1 ≦ n ≦ (N-1), n It is a positive integer, and the definition of the transition is the transformation of high and low logic levels. The phase detector 2 determines that an integration time T _{n of} the nth symbol D _n is greater than that of the (n + 1) _th symbol D _{n + 1} An integration time T _{n + 1} , that is, when the phase of the clock signal leads, the phase detector 2 adjusts the control signal to reduce the frequency of the clock signal. For example, assume that the n-th symbol D _n is a logic 1 (positive polarity), the first n + 1 symbols D _{n + 1} is a logic 0 (negative polarity), when the clock signal a phase lead, the integrator 6 to n symbols D _n integration time T _n Is greater than the integration time T _{n + 1} for the n + 1th symbol D _{n + 1} , so the polarity of the total integration result is positive, the digital signal En = 1 of the comparator 7 is different from the sampling of the nth symbol D _n The result is the same, namely En = Dn. The operation of the entire CDR when the phase of the clock signal (CKD) is advanced is shown in FIG. 6, the control signal DN = 1 of the phase detector 2, the charge pump 10 extracts the charge from the filter, the control voltage V _CTRL drops, and the oscillator 12 outputs The frequency of the clock signal drops, and the phase of the clock signal shifts backward.

When the phase detector 2 determines the n-th symbol of an integral time T _n is less than the first (n + 1) symbols of an integration time T _{n + 1,} the time is a clock signal delayed in phase, the phase detector 2 Adjust the control signal to increase the frequency of the clock signal. When the phase of the clock signal lags behind, the integration time T _n of the nth symbol D _n by the integrator 6 is less than that of the n + 1 symbol D _{n + 1} The integration time T _{n + 1} , so the polarity of the total integration result is negative, at this time, En = D _{n + 1} . The operation of the entire CDR when the clock signal phase lags is shown in FIG. 7. The operation of the entire CDR is the control signal UP = 1 of the phase detector 2, the charge pump 10 injects charge into the filter 11, and the control voltage V _CTRL rises to cause oscillation The frequency of the clock signal output from the device 12 rises, and the clock phase shifts forward.

When phase locked, the node data symbols located in the middle, i.e. the best sampling point, at this time, the n-th symbol D _n of a equal to the integration time T _n of the (n + 1) symbol D _n An integration time T _{n + 1 of +1} . When locked, because the value of En is randomly equal to Dn or Dn + 1.

In summary, because of the phase detector 2 in the CDR of the above embodiment, there is no need for additional edge sampling of the input data (only one sampling edge is used to sample one symbol), that is, the required sampling frequency of the clock signal is the same Due to the data transmission rate, which is only half of the clock sampling frequency required by the existing CDR technology, its effect is to significantly reduce the power consumption of the entire CDR circuit. In addition, if it is a clock signal of the same frequency but multiple different phases In terms of sampling technology, when applied in high-speed design, because of the reduced sampling rate, it is assumed that eight clock signals (1 GHz) with eight different phases are provided to the existing phase detector, which makes it 4Gbps The input data is double oversampling (8Gbps), using the phase detector of the present invention only requires four phases to achieve baud rate sampling (4Gbps), the phase is reduced by half, which helps solve the difficulty of multi-phase clock matching Therefore, the purpose of cost invention can indeed be achieved.

However, the above are only examples of the present invention, and should not be used to limit the scope of implementation of the present invention, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still considered as Within the scope of the invention patent.

1‧‧‧ Clock generator
10‧‧‧charge pump
11‧‧‧filter
12‧‧‧Oscillator
2‧‧‧Phase detector
3‧‧‧Data sampling circuit
4‧‧‧ Integral comparison circuit
5‧‧‧Logic circuit
6‧‧‧Integrator
7‧‧‧Comparator
CK‧‧‧clock signal
Data‧‧‧Enter data
En‧‧‧Digital signal
Dn‧‧‧ symbol
Dn + 1‧‧‧ symbol
CKn‧‧‧nth sampling edge
CKn + 1‧‧‧th (n + 1) th sampling edge
UP‧‧‧Control signal
DN‧‧‧Control signal
I _CP ‧‧‧ current
V _CTRL ‧‧‧ control voltage

Other features and functions of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a circuit diagram of an embodiment of the clock and data recovery device of the present invention; FIG. 2 is a moment of the embodiment Sequence diagram; FIG. 3 is a circuit diagram of the phase discriminator of this embodiment; FIG. 4 is a circuit diagram of the integration comparison circuit of this embodiment; FIG. 5 is an integration phase diagram of the integrator of this embodiment; FIG. 6 is this FIG. 7 is a timing diagram of the operation of the CDR when the phase of the embodiment is advanced; FIG. 7 is a timing diagram of the operation of the CDR when the phase of the embodiment is behind.

Claims (8)

A clock and data recovery device includes: a clock signal generator, receiving a control signal, and generating a clock signal according to the control signal, the control signal is used to adjust a frequency of the clock signal; a phase detector, receiving a Input data with the first to Nth symbols, N ≧ 2, N is a positive integer, and is electrically connected to the clock signal generator to receive the clock signal, and generates the control signal according to the clock signal and the input data ; When the phase detector judges that a transition occurs between an nth symbol and a (n + 1) th symbol, 1 ≦ n ≦ (N-1), n is a positive integer, and the definition of the transition is For the conversion of high and low logic levels, the phase detector determines that an integration time of the nth symbol is greater than an integration time of the (n + 1) th symbol, then the phase detector adjusts the control signal to reduce the clock signal The frequency of, the integration time of the nth symbol is the transition point from the nth sampling edge of the clock signal to the two symbols, and the integration time of the (n + 1) th symbol is from The transition point between the two symbols reaches the (n + 1) th sampling edge of the clock signal. The clock and data reply device according to claim 1, wherein the phase detector determines that an integration time of the nth symbol is less than an integration time of the (n + 1) th symbol, then the phase detector adjusts The control signal increases the frequency of the clock signal. The clock and data reply device according to claim 1, wherein when the phase detector determines that there is no transition between an n-th symbol and an (n + 1) -th symbol, the control signal maintains the clock The frequency of the signal. The clock and data reply device according to claim 1, wherein the phase detector includes: a data sampling circuit that receives the input data, and is electrically connected to the clock signal generator to receive the clock signal, based on the clock signal Sampling the input data to generate the first to Nth symbols; an integration comparison circuit that receives the input data and the clock signal, and the nth symbol and the (n + 1) The symbols are integrated, and the integration time of the nth symbol and the (n + 1) th symbol is compared to generate a digital signal, which is used to indicate the nth symbol and the ( n + 1) one of the symbols; a logic circuit electrically connecting the comparator and the data sampling circuit to receive the digital signal from the comparator and the n-th symbol from the data sampling circuit and the The (n + 1) th symbol, and it is judged that the digital signal matches the nth symbol or the (n + 1) th symbol to generate the control signal, when the digital signal matches the nth symbol, it means The nth sampling edge leads the midpoint of the nth symbol, then the control signal Frequency; when the digital signal conforms to the first (n + 1) symbol, indicating that the backward edge of the n-th sampling the n-th symbol intermediate point, the control signal indicates the frequency increases. The clock and data reply device according to claim 4, wherein the integration comparison circuit includes: an integrator that receives the input data, and is electrically connected to the clock signal generator to receive the clock signal, and from the clock signal From the nth sampling edge to the (n + 1) th sampling edge, integrate the nth symbol and the (n + 1) th symbol of the input data to obtain an integration result; a comparison Is connected to the integrator to receive the integration result and compare the integration result with a threshold to output a digital signal. If the integration result is greater than the threshold, the digital signal is a first logic (1), If the integration result is less than the critical value, the digital signal is a second logic (0). The clock and data recovery device according to claim 1, wherein the clock signal generator includes: a charge pump that receives the control signal and generates a current according to the control signal; and a filter that is electrically connected to the charge pump to receive The current, and the current is converted into a control voltage, when the current flows into the filter, the control voltage increases, when the current flows out of the filter, the control voltage decreases; an oscillator is used to generate the clock signal , The filter is electrically connected to receive the control voltage, and the frequency of the clock signal is adjusted according to the control voltage, the frequency being proportional to the control voltage. A phase discriminator is suitable for electrically connecting a clock signal generator, the clock signal generator generates a clock signal, the phase discriminator is used to generate a control signal to control a frequency of the clock signal, and the phase discriminator includes: A data sampling circuit receives an input data having the first to Nth symbols, N ≧ 2, N is a positive integer, and is electrically connected to the clock signal generator to receive the clock signal, based on the clock signal The input data is sampled to generate the first to Nth symbols; an integration comparison circuit receives the input data and the clock signal, and the nth symbol and the (n + 1) th of the input data The symbols are integrated, and the integration time of the nth symbol and the (n + 1) th symbol is compared to generate a digital signal, which is used to indicate the nth symbol and the (n + 1) One of the symbols; a logic circuit electrically connecting the comparator and the data sampling circuit to receive the digital signal from the comparator and the n-th symbol and the (( n + 1) symbol, and judge that the digital signal conforms to the nth A symbol or the (n + 1) th symbol to generate the control signal, when the digital signal matches the nth symbol, indicating that the nth sampling edge leads the midpoint of the nth symbol, then the The control signal instructs to decrease the frequency; when the digital signal matches the (n + 1) th symbol, indicating that the nth sampling edge lags behind the midpoint of the nth symbol, the control signal instructs to increase the frequency. The phase discriminator according to claim 7, wherein the integration comparison circuit includes: an integrator that receives the input data, and is electrically connected to the clock signal generator to receive the clock signal, and from the nth of the clock signal From the sampling edge to the (n + 1) th sampling edge, integrate the nth symbol and the (n + 1) th symbol of the input data to obtain an integration result; a comparator, The integrator is electrically connected to receive the integration result and compare the integration result with a critical value to output a digital signal. If the integration result is greater than the critical value, the digital signal is a first logic (1), if the If the integration result is less than the critical value, the digital signal is a second logic (0).