KR20080051662A - High-speed clock and data recovery circuit using quarter rate clock - Google Patents

Abstract

A high-speed clock and data recovery circuit using a quarter frequency clock of data speed, and a method thereof are provided to reduce the size of whole circuit while processing data at a high-speed by recovering a clock and data with the quarter frequency clock of data speed in a situation incapable of generating a high frequency clock. A PLL(Phase Locked Loop) circuit(100) generates a quarter frequency clock of reception data speed by receiving an external clock. A phase interpolation circuit(300) adjusts the phase of the clock output from the PLL circuit to sample the middle part of a received data signal according to a phase control signal received from a clock recovery circuit. A demultiplier circuit(500A,500B) demultiplies the received data signal into halves. The clock recovery circuit(700A,700B) generates the phase control signal for adjusting the phase of the clock by using the demultiplied data signal and the clock output from a phase interpolation circuit. A data determination circuit(900) outputs the middle part of the received data by using the clock adjusted by the clock recovery circuit and the phase interpolation circuit.

Description

High-speed clock and data recovery circuit using quarter rate clock

1 is a circuit diagram of a clock and data recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the phase locked loop circuit of FIG. 1.

3 is a circuit diagram illustrating an oscillator of FIG. 2.

4 is a diagram illustrating a phase interpolation circuit and a waveform of FIG. 1.

5 is a diagram illustrating the clock recovery circuit of FIG. 1.

6 is an operation timing diagram of the clock recovery circuit of FIG. 5.

FIG. 7 is a diagram illustrating a data determination circuit of FIG. 1.

8 is an operation timing diagram of the data determination circuit of FIG. 7.

9A is a diagram for explaining a data restoration process when no delay buffer circuit is used.

FIG. 9B is a diagram illustrating a data restoration process in the case of using a delay buffer circuit as in the present invention.

Explanation of symbols on the main parts of the drawings

100: phase locked loop circuit

300: phase interpolation circuit

500A, 500B: first division circuit, second division circuit

700A, 700B: first clock recovery circuit, second clock recovery circuit

800: delay buffer circuit

900: data determination circuit

The present invention relates to a high-speed clock and data recovery circuit and method using a 1/4 frequency clock of the data rate, and more specifically, to a 1/4 clock frequency of the data rate even in a situation that can not produce a high frequency clock A clock and data recovery circuit and method capable of recovering clock and data.

In general, a receiving end of a data communication or data transmission system recovers a clock from the received data and extracts and restores the data using the restored clock.

Conventionally, since the speed of the received data is not high and the input buffer has no significant distortion in transferring data to the next stage, a clock having the same frequency as the data rate is generated in a phase locked loop (PLL) and used for data determination. .

However, if the data rate is increased to several tens of Gbps, an Inter Symbol Interference (ISI) phenomenon occurs when the received data passes through the input buffer and is transferred to the next stage. This cannot be done properly.

In addition, it is difficult to generate the required clock frequency due to the threshold frequency at which the device can operate when the clock frequency increases according to the data rate. To this end, an on-chip inductor is conventionally used. There is a problem that the size is too large.

Accordingly, it is an object of the present invention to recover a clock and data using a 1/4 clock frequency of a data rate, thereby enabling a high-speed data processing and reducing the size of an entire circuit. To provide.

In order to achieve the above object, a clock and data recovery circuit according to the present invention comprises: a phase locked loop circuit for receiving an external clock to generate a 1/4 clock frequency of a received data rate; A phase interpolation circuit for adjusting a phase of a clock output from the phase locked loop circuit so as to sample the center of the received data according to a phase control signal input from a clock recovery circuit; A division circuit for dividing the received data by half; A clock recovery circuit configured to generate a phase control signal for adjusting a phase of the clock by using a data signal divided through the division circuit and a clock output from the phase interpolation circuit; And a data determination circuit for sampling and outputting the center of the received data using a clock whose phase is adjusted through the clock recovery circuit and the phase interpolation circuit.

On the other hand, to achieve the above object, the clock and data recovery method according to the present invention, (a) receiving an external clock to generate and output a clock signal having a frequency of 1/4 of the received data rate; (b) adjusting a phase of the output clock to sample the center of the received data according to an input phase control signal; (c) dividing the received data in half; (d) generating and outputting a phase control signal for adjusting the phase of the clock using the divided data signal and the phase adjusted clock; And (e) sampling and outputting the center of the received data using the phase adjusted clock.

Objects and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a clock and data recovery circuit according to an embodiment of the present invention.

Referring to FIG. 1, the clock and data recovery circuit 1 of the present invention includes a phase locked loop circuit PLL 100, a phase interpolator 300, a divider circuit 500A, 500B, and a clock. Recovery circuits (Clock Recovery, 700A, 700B), delay buffer circuit 800, and a data decision circuit (Data Decision, 900).

The phase locked loop circuit 100 is for generating a clock having a quarter frequency of the data rate for data recovery, which will be described in more detail with reference to FIGS. 2 and 3 as follows.

FIG. 2 is a block diagram illustrating the phase locked loop circuit 100 of FIG. 1, and FIG. 3 is a circuit diagram illustrating the oscillator 110 of FIG. 2.

As shown in FIG. 2, the phase locked loop circuit 100 includes an oscillator (VCO) 110, a first divider 120 having a CML (Current-Mode Logic) structure, and a D2S converter (Differential to Single-ended Converter). 130, a second divider 140, a phase frequency detector (PFD) 150, a charge pump, and a low pass filter (CP & LP) 160.

The oscillator 110 outputs the multi-phase clock signals CK0, CK45, CK90, and CK135 as shown in FIG. 3 according to a control voltage input from a charge pump and a low pass filter 160 to be described later.

The first divider 120 divides the clock signals CK0, CK45, CK90, and CK135 output from the oscillator 110 into quarters, and the clock signals divided into quarters are divided into the D2S converters ( 130 is converted into a single-ended signal and input to the second divider 140 to be divided into 1/16.

The phase frequency detector 150 compares the frequency of the external clock signal with the frequency of the clock signal divided by 1/16 through the second divider 140 and detects the phase difference.

The charge pump and the low pass filter 160 increase and decrease the charge according to the phase difference signal detected by the phase frequency detector 150, and then remove the high frequency component from the charge-decreased signal to generate a control voltage.

That is, the phase locked loop circuit 100 generates and outputs multi-phase clock signals CK0, CK45, CK90, and CK135 necessary for data recovery from an external clock.

Referring back to FIG. 1, the phase interpolation circuit 300 adjusts the phase of the clock signal so that the clock signal output from the phase locked loop circuit 100 can sample the center portion of the data. With reference to Figure 4 will be described in more detail as follows.

4 is a diagram illustrating a waveform and the phase interpolation circuit 300 of FIG. 1.

As shown in FIG. 4, the phase interpolation circuit 300 outputs a clock signal output from the phase locked loop circuit 100 according to phase control signals Vctrl input from clock recovery circuits 700A and 700B to be described later. First to fourth phase interpolation circuits 300a, 300b, 300c, and 300d which output the phase-adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 by adjusting the phases of (CK0, CK45, CK90, and CK135). do.

The first phase interpolation circuit 300a outputs the phase interpolated signal INTCLK0 of the clock signal CK0 and the clock signal CK90, and the second phase interpolation circuit 300b performs the phase interpolation of the clock signal CK45 and the clock signal CK135. Output the signal INTCLK45.

In addition, the third phase interpolation circuit 300c outputs an inverting signal of the clock signal CK0 (that is, a falling edge signal of the clock signal CK0) and a phase interpolated signal INTCLK90 of the clock signal CK90. 300d outputs an inverting signal of the clock signal CK45 (that is, the falling edge signal of the clock signal CK45) and a phase interpolated signal INTCLK135 of the clock signal CK135.

Here, the reason for using the clock signal (falling edge of the clock signal) inverted to the input of the phase interpolation circuit 300, the phase adjustment range (D2) of the interpolated clock is a duration of at least one data (duration) ) Must be equal to or greater than D1.

That is, in order to recover the correct data, the clock signal should sample the center portion of the data. For this purpose, in the phase interpolation circuit 300, the edge of the clock output from the phase locked loop circuit 100 is located at the center portion of the data. The phase of the clock is adjusted so that it is located.

Referring back to FIG. 1, the first division circuit 500A and the second division circuit 500B may reduce the speed of the reception data DATA so that the next division circuits may operate at the speed at which the subsequent circuits may operate properly. DATA) is divided in half, and at this time, the first division circuit 500A outputs the divided signal DATA / 2_1 based on the rising edge of the received data DATA and the second division The circuit 500B outputs the divided signal DATA / 2_2 based on the falling edge of the received data DATA.

The division of the received data DATA in this manner is due to the bandwidth of the clock recovery circuits 700A and 700B. If the received data DATA is directly input to the flip-flops of the clock recovery circuits 700A and 700B, Due to the high frequency of the received data DATA, the flip-flop reaches the limit at which the device can operate, and thus the flip-flop does not operate properly. For this purpose, the received data DATA is transferred through the division circuits 500A and 500B. It is busy.

In addition, the division circuits 500A and 500B perform the division based on the rising edge and the falling edge of the received data DATA, respectively, because the clock recovery circuits 700A and 700B described later perform more accurate clock recovery. This will be described in detail with reference to FIGS. 5 and 6.

Referring back to FIG. 1, the clock recovery circuits 700A and 700B are output from the data Data / 2_1 and Data / 2_2 divided by the division circuits 500A and 500B and the phase interpolation circuit 300. The phase control signal Vctrl for adjusting the phase of the clock is generated by using the phase-controlled clock signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135, which will be described in detail with reference to FIGS. 5 and 6 as follows. same.

5 is a diagram illustrating a clock recovery circuit of FIG. 1, and FIG. 6 is an operation timing diagram of the clock recovery circuit of FIG. 5.

As shown in FIG. 5, the clock recovery circuits 700A and 700B include flip-flops 710, 720, 730 and 740, XOR gates 750 and 760, a comparator 770 and a voltage-to-current converter VI. do.

The flip-flops 710, 720, 730, and 740 include clock signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit 300 and data divided by the divider circuits 500A and 500B. Data / 2_2) are respectively input. The reason why a plurality of clock signals and divided data are used during clock recovery will be described in detail as follows.

As shown in FIG. 6, when the INTCLK0 waveform of the phase-adjusted clock signal and the waveform of Data / 2_1 of the divided data are examined, the rising edge of the Data / 2_1 waveform is always located at the edge portion of the INTCLK0. Because of this, it is difficult to determine the phase difference.

In other words, if only one clock phase INTCLK0 is used for clock recovery as in the conventional clock recovery circuit, the rising edge of the data cannot always sample the edge of the clock.

That is, in the present invention, multiphase clock signals CK0, CK45, CK90, and CK135 are generated through the phase-locked loop circuit 100 to solve a problem that occurs when only one phase clock is used for clock recovery. And adjust the phase so that the edges of the clock signals CK0, CK45, CK90, and CK135 are located at the center of the data, so that the clock recovery is performed according to the phase-controlled signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135. will be.

On the other hand, the more edges of the data in the clock recovery, the more the number of times to check the phase of the data and the clock can be more accurate clock recovery. Dispensing results in fewer data edges and fewer checks.

That is, the present invention divides the data on the basis of both the rising edge and the falling edge of the received data DATA, and performs clock recovery using the divided data signal. As such, the number of rising edges of the data DATA and the number of rising edges of the divided data Data / 2_1 and Data / 2_2 are equal, so that the number of times of the clock recovery circuits 700A and 700B checks the data DATA. It becomes equal to the number of rising edges, resulting in more accurate clock recovery.

The XOR gates 750 and 760 and the selector 770 determine whether the divided data Data / 2_1 and Data / 2_2 are faster or slower than the clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135. If this is described in more detail as follows.

Referring to the case of (I) of FIG. 6, in the flip-flop 710, the rising edge of the divided data DATA / 2_1 samples INTCLK0 so that D0 becomes '1', and the flip-flop 720 divides the divided data. The rising edge of (DATA / 2_1) samples INTCLK90 so that D1 becomes '0'.

That is, when the divided data DATA / 2_1 and the edge of INTCLK0 are compared, the state of (I) means that the data is slower than the clock.

In the method of determining whether data is faster or slower than the clock in the state of (I), the values D0 and D90 may be input to the XOR gate 750. That is, Exclusive-OR is performed by inputting the outputs of the flip-flops 710 and 720 to the XOR gate 750.

That is, if the X0 value is '0' because the D0 value and the D90 value are the same, the data is faster than the clock. If the X1 value is '1' because the D0 value and the D90 value are different, the data is slower than the clock.

The problem arises in the case of (II). In the case of (II), the rising edge of the data DATA / 2_1 divided by the flip-flop 710 samples INTCLK0 so that D0 becomes '1' and the data DATA / 2_1 divided by the flip-flop 720. The rising edge of samples INTCLK90 and D1 becomes '0', and the X1 value becomes '1' in the same manner as in the state (I) above.

That is, in the state of (II), the data is faster than the clock as opposed to the state of (I), but the value of X1 becomes '1' as in the state of (I), and accordingly the data according to the value of X1. Cannot determine whether it is faster or slower than the clock.

To this end, in the clock recovery circuits 700A and 700B of the present invention, the X2 value generated through the flip-flops 730 and 740 and the XOR gate 760 is compared with the X1 value through the comparator 770 as follows. Based on the result of the comparison, the data is determined to be faster or slower than the clock.

First, the rising edges of the data DATA / 2_1 divided through the flip-flops 730 and 740 sample the INTCLK45 and INTCLK135, respectively, and input the sampling values D45 and D135 into the XOR gate 760 to input the X2 value. Output

Next, the comparator 770 compares the X1 value output from the XOR gate 750 with the X2 value output from the XOR gate 760, and outputs '1' if the X1 value and the X2 value are different from each other. If the X1 value and the X2 value are the same, '0' is output. Here, the comparator 770 has an XOR gate characteristic that receives an output of the XOR gate 750 and an output of the XOR gate 760 and outputs a difference between a phase of the received data and the clock phase.

For example, in FIG. 6, when looking at the output S of the selector 770, when X1 is '1' and X2 is '0', S is '1', X1 is '1' and X2 is '1'. It can be seen that S becomes '0'.

That is, if the S value is '0', the data is faster than the clock. If the S value is '1', the data is slower than the clock.

As such, the clock recovery circuit 700A samples the INTCLK0, INTCLK45, INTCLK90, and INTCLK135 using the divided data Data / 2_1 and Data / 2_2, respectively, and uses the signals to determine whether data is out of phase with the clock. Decide if

In the present embodiment, multi-phase clock signals CK0, CK45, CK90, and CK135 having 0 °, 45 °, 90 °, and 135 ° phases are generated in order to use a 1/4 frequency clock of the data rate. Although the rising and falling edges of the multi-phase clock signals CK0, CK45, CK90, and CK135 are used for clock recovery, for example, when a 10 GHz clock is used for 10 Gbps data, a bang-bang clock recovery circuit is used. One clock is sufficient, in which case the rising or falling edge of the data samples the edge of the clock to determine whether the clock is faster or slower than the data, depending on whether the sampling value is '0' or '1'.

For example, if one clock is used in the clock recovery circuit, if the rising edge of the data samples the left portion '0' of the rising edge of the clock, it can be determined that the data is faster than the clock, and thus the phase of the clock. Can be adjusted to the data edge.

Referring back to FIG. 1, the data determination circuit 900 uses a clock whose phase is adjusted to sample the center of the data through the clock recovery circuits 700A and 700B and the phase interpolation circuit 300. The delayed received data (Delayed DATA) is delayed through the delay buffer circuit 800 using only two clocks (INTCLK45, INTCLK135) among the phase-controlled clock signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135. The data is restored and output as output data OUTDATA, which will be described in more detail with reference to FIGS. 7 and 8 as follows.

FIG. 7 is a diagram illustrating the data determination circuit 900 of FIG. 1, and FIG. 8 is an operation timing diagram of the data determination circuit of FIG. 7.

As illustrated in FIG. 7, the data determination circuit 900 includes first to fourth flip-flops 910, 920, 930, and 940 that receive and output delayed data through the delay buffer circuit 800. The first flip-flop 910 and the third flip-flop 930 output the delayed data in response to the rising and falling edges of the clock INTCLK45 signal, and the second flip-flop 920 and the second flip-flop 930. The four flip-flops 940 output the delayed data in response to the rising and falling edges of the clock INTCLK135 signal.

Referring to FIG. 8, when the clock signals INTCLK45 and INTCLK135 and the delayed data signal are input to the data determination circuit 900, the delayed data of the delayed data on the rising and falling edges of the clock signal INTCLK45 is input. The center is sampled to output a sampling value of '11', and the center of the delayed data is sampled at the rising and falling edges of the clock signal INTCLK135 to output the sampling value of '01'.

In this case, the clock signals INTCLK45 and INTCLK135 are phase adjusted signals so that the center of the data can be sampled through the clock recovery circuits 700A and 700B and the phase interpolation circuit 300.

That is, among the phase-adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 so that the center of the data may be sampled through the phase interpolation circuit 300, INTCLK45 and INTCLK135 may be used to restore the data in the data determination circuit 900. The data output from the data determination circuit 900 is 1: 4 demultiplexed and output.

Referring back to FIG. 1, the delay buffer circuit 800 is for delaying the received data DATA by the delay times of the division circuits 500A and 500B, which will be described in more detail with reference to FIGS. 9A and 9B. Is as follows.

FIG. 9A is a diagram illustrating a data restoration process when the delay buffer circuit is not used, and FIG. 9B is a diagram illustrating a data restoration process when the delay buffer circuit is used as in the present invention.

As shown in FIG. 9A, when the delay buffer circuit is not used, the signal DATA / 2 divided through the divider circuits 500A and 500B is delayed and output by the delay time of the divider circuit element. In this case, the received data DATA which is not delayed is input to the data determination circuit 900, but the clock recovery circuits 700A and 700B recover the clock signal in accordance with the edge of the delayed signal DATA / 2. As a result, the edges of the restored clock signal and the received data DATA do not coincide, and thus, accurate data cannot be recovered.

On the other hand, as shown in FIG. 9B, even when the delay buffer circuit is used, even if the signal DATA / 2 divided through the division circuits 500A and 500B is delayed and output by the delay time of the division circuit element, That is, even when the clock recovery circuits 700A and 700B restore the clock signal to the edge of the delayed data, the delayed signal circuit Delayed_DATA is delayed by the delay buffer circuit 800 to determine the data decision circuit 900. In this case, the edges of the divided data (DATA / 2) and the delayed data (Delayed DATA) coincide with each other, thereby accurately recovering the data.

Meanwhile, in the present exemplary embodiment, the delayed data is delayed by a predetermined time, and the delayed buffer circuit 800 is input to the data determination circuit 900. It may be omitted for simplicity of configuration.

As described above, the present invention proposes a clock and data recovery circuit structure of a new method of recovering a clock by using a 1/4 clock frequency of a data rate, so that even when a high frequency clock cannot be produced, a quarter of the data rate can be obtained. The advantage is that the clock frequency can be used to process high speed data. In addition, the present invention, if only the oscillator capable of generating a high frequency clock frequency can be easily designed, there is an advantage that it is possible to simply implement the clock and data recovery circuit without using multiple flip-flops.

So far, the present invention has been described with reference to the preferred embodiments, and those skilled in the art to which the present invention belongs may be embodied in a modified form without departing from the essential characteristics of the present invention. You will understand. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

As described above, according to the present invention, by presenting a clock and data recovery circuit structure of a new method of recovering the clock by using the 1/4 clock frequency of the data rate, even in a situation where a high frequency clock can not be made It is effective to process high speed data using 1/4 clock frequency of.

In addition, according to the present invention, since a high speed clock and data recovery circuit can be implemented without using an inductor, the size of the entire circuit can be reduced.

Claims (20)

A phase locked loop circuit for receiving an external clock and generating a quarter clock frequency of the received data rate; A phase interpolation circuit for adjusting a phase of a clock output from the phase locked loop circuit so as to sample the center of the received data according to a phase control signal input from a clock recovery circuit; A division circuit for dividing the received data by half; A clock recovery circuit configured to generate a phase control signal for adjusting a phase of the clock by using a data signal divided through the division circuit and a clock output from the phase interpolation circuit; And And a data determination circuit for sampling and outputting the center of the received data using a clock whose phase is adjusted through the clock recovery circuit and the phase interpolation circuit. The circuit of claim 1, wherein the phase locked loop circuit comprises: An oscillator for receiving an external clock and generating clock signals CK0, CK45, CK90, and CK135 of multi-phase according to a control voltage; A first divider for dividing the clock signal output from the oscillator into quarters; A D2S converter for converting the signal output from the first divider into a single-ended signal; A second divider for dividing the signal output from the D2S converter by a quarter; A phase frequency detector for comparing a frequency of the external clock signal with a frequency of a clock signal divided through the second divider and detecting a phase difference thereof; And And a charge pump and a low pass filter for generating the control voltage by increasing and decreasing charge according to the phase difference signal detected by the phase frequency detector and removing high frequency components from the charge-decreased signal. . The method of claim 2, wherein the phase interpolation circuit, A first to output phase adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 by adjusting phases of the clock signals CK0, CK45, CK90, and CK135 output from the phase-locked loop circuit according to the phase control signal; And a fourth phase interpolation circuit. 4. The clock and data recovery circuit of claim 3 wherein the phase adjustment range of the phase interpolation circuit is greater than or equal to a period of at least one data. The method of claim 1, wherein the frequency division circuit, A first division circuit configured to output a divided signal DATA / 2_1 based on the rising edge of the received data; And And a second division circuit configured to output a divided signal DATA / 2_2 based on the falling edge of the received data. The method of claim 5, wherein the clock recovery circuit, A first clock recovery circuit configured to generate a phase control signal for adjusting a phase of the clock by using a data signal DATA / 2_1 divided through the first division circuit and a clock output from the phase interpolation circuit; And And a second clock recovery circuit configured to generate a phase control signal for adjusting the phase of the clock by using the data signal DATA / 2_2 divided by the second division circuit and the clock output from the phase interpolation circuit. Clock and data recovery circuitry. The method of claim 6, wherein the first clock recovery circuit and the second clock recovery circuit, And a phase control signal for adjusting a phase of the clock by determining whether the divided data signal is faster or slower than a clock output from the phase interpolation circuit. The method of claim 6, wherein the first clock recovery circuit and the second clock recovery circuit, A flip-flop that receives and outputs the divided data signal and a clock signal output from the phase interpolation circuit; An XOR gate configured to exclusively OR the output of the flip-flop; A selector for outputting a signal representing a difference between a phase of the divided data signal and a phase of a clock signal output from the phase interpolation circuit according to the output of the XOR gate; And And a voltage-to-current converter for converting the voltage signal output from the selector into a current signal. The method of claim 8, And the divided data signal is input to the flip-flop clock, and the clock signal output from the phase interpolation circuit is input to the flip-flop data. The method of claim 1, And a delay buffer circuit for delaying and outputting the received data signal by a predetermined time. The method of claim 10, And an edge of the data signal divided by the division circuit and an edge of the data signal delayed by the delay buffer circuit for a predetermined time. The method of claim 10, wherein the data determination circuit, And first to fourth flip-flops for receiving and outputting the delayed data through the delay buffer circuit. A clock signal whose phase is adjusted through the phase interpolation circuit is input to the clocks of the first to fourth flip-flops, and the delayed data signal is input to the data of the first to fourth flip-flops And data recovery circuitry. The method of claim 3, wherein the data determination circuit, A clock comprising sampling the center of the delayed data at the rising and falling edges of two clock signals INTCLK45 and INTCLK135 among the phase-adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 through the phase interpolation circuit; And data recovery circuitry. The method of claim 10 or 13, The first flip-flop and the third flip-flop are the delayed data in response to the rising and falling edges of the clock signal INTCLK45 among the signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. Output The second flip-flop and the fourth flip-flop are the delayed data in response to the rising and falling edges of the clock signal INTCLK135 among the signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. The clock and data recovery circuit, characterized in that for outputting. (a) receiving an external clock to generate and output a clock signal having a frequency of 1/4 of a received data rate; (b) adjusting a phase of the output clock to sample the center of the received data according to an input phase control signal; (c) dividing the received data in half; (d) generating and outputting a phase control signal for adjusting the phase of the clock using the divided data signal and the phase adjusted clock; And (e) sampling and outputting the center of the received data by using the phase-controlled clock. The method of claim 15, wherein step (a), A first step of receiving an external clock and generating clock signals CK0, CK45, CK90, and CK135 of a multi-phase according to a control voltage; Dividing the multi-phase clock signal into quarters; Converting the signal divided into quarters into a single-ended signal and dividing the converted signal into quarters again; A fourth step of comparing a frequency of the external clock signal with a frequency of a clock signal divided through the third step and detecting a phase difference thereof; And And a fifth step of generating a control voltage by increasing and decreasing charge in accordance with the detected phase difference signal and removing high frequency components from the charge-decreased signal. The method of claim 16, wherein step (b), And adjusting the phases of the multi-phase clock signals CK0, CK45, CK90, and CK135 according to the phase control signal to output the phase-adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135. Clock and data recovery method. The method of claim 15, wherein step (c) is Outputting a divided signal DATA / 2_1 based on the rising edge of the received data; And And outputting a divided signal DATA / 2_2 based on the falling edge of the received data. 19. The method of claim 17 or 18, wherein step (d) Generating a phase control signal for adjusting the phase of the clock by determining whether the divided data signals DATA / 2_1 and DATA / 2_2 are faster or slower than the phase-controlled signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135. The clock and data recovery method further comprises. The method of claim 16, wherein step (e) Outputting the received data signal by delaying the predetermined time; And And sampling a center of the delayed data at the rising and falling edges of two clock signals INTCLK45 and INTCLK135 among the phase-adjusted signals INTCLK0, INTCLK45, INTCLK90, and INTCLK135. And how to restore data.

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