KR100844313B1 - High-Speed Clock and Data Recovery Circuit using quarter rate clock - Google Patents

Abstract

The present invention relates to a high speed clock and data recovery circuit and method using a quarter frequency clock of a data rate. The present invention relates to a new method of clock and data recovering a clock using a quarter clock frequency of a received data rate. By presenting a recovery circuit structure, it is possible to process high-speed data using a 1/4 clock frequency of the data rate even in a situation where a high-frequency clock cannot be produced. In addition, the present invention can implement a high-speed clock and data recovery circuit without using an inductor, it is characterized in that the size of the entire circuit can be reduced.

Clock Recovery, Data Determination, Phase Interpolation, Division, Phase Locked Loop

Description

High-speed clock and data recovery circuit using quarter rate clock

1 is a circuit diagram of a clock and data recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the phase locked loop circuit of FIG. 1.

3 is a circuit diagram illustrating an oscillator of FIG. 2.

4 is a diagram illustrating a phase interpolation circuit and a waveform of FIG. 1.

5 is a diagram illustrating the clock recovery circuit of FIG. 1.

6 is an operation timing diagram of the clock recovery circuit of FIG. 5.

FIG. 7 is a diagram illustrating a data determination circuit of FIG. 1.

8 is an operation timing diagram of the data determination circuit of FIG. 7.

9A is a diagram for explaining a data restoration process when no delay buffer circuit is used.

FIG. 9B is a diagram illustrating a data restoration process in the case of using a delay buffer circuit as in the present invention.

Explanation of symbols on the main parts of the drawings

100: phase locked loop circuit

300: phase interpolation circuit

500A, 500B: first division circuit, second division circuit

700A, 700B: first clock recovery circuit, second clock recovery circuit

800: delay buffer circuit

900: data determination circuit

The present invention relates to a high-speed clock and data recovery circuit and method using a 1/4 frequency clock of the data rate, and more specifically, to a 1/4 clock frequency of the data rate even in a situation that can not produce a high frequency clock A clock and data recovery circuit and method capable of recovering clock and data.

In general, a receiving end of a data communication or data transmission system recovers a clock from the received data and extracts and restores the received data using the restored clock.
Conventionally, since the speed of the received data is not high and the input buffer has no significant distortion in transferring data to the next stage, a clock having the same frequency as the data rate is generated in a phase locked loop (PLL) and used for data determination. .

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However, if the data rate is increased to several tens of Gbps, an Inter Symbol Interference (ISI) phenomenon occurs when the received data passes through the input buffer and is transferred to the next stage. This cannot be done properly.

In addition, it is difficult to generate the required clock frequency due to the threshold frequency at which the device can operate when the clock frequency increases according to the data rate. To this end, an on-chip inductor is conventionally used. There is a problem that the size is too large.

Accordingly, it is an object of the present invention to recover a clock and data using a 1/4 clock frequency of a data rate, thereby enabling a high-speed data processing and reducing the size of an entire circuit. To provide.

In order to achieve the above object, the clock and data recovery circuit according to the present invention receives an external clock and generates multi-phase clocks CK0, CK45, CK90, and CK135 having a 1/4 frequency of a received data rate. A phase locked loop circuit for outputting the same; The first phase of which the phase is adjusted by adjusting the phase of the multi-phase clocks CK0, CK45, CK90, and CK135 output from the phase-locked loop circuit so as to sample the center of the received data according to a phase control signal Vctrl. A phase interpolation circuit for outputting the fourth to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135; A divider circuit for dividing the received data in half and outputting divided received data (Data2_1, Data2_2); A delay buffer circuit for delaying the received data by a predetermined time and outputting delayed received data so that the edges of the received data Data2_1 and Data2_2 divided by the division circuit are synchronized with the edge of the received data; The phase control signal Vctrl using the received data Data2_1 and Data2_2 divided through the division circuit and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. A clock recovery circuit which generates and outputs a signal; And sampling and outputting the center of delayed data delayed through the delay buffer circuit using the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. A decision circuit is provided.

In order to achieve the above object, the clock and data restoration method according to the present invention includes (a) a multi-phase clock (CK0, CK45, CK90) having an external clock input and having a 1/4 frequency of a received data rate. Generating and outputting CK135; (b) Adjust the phase of the multi-phase clocks CK0, CK45, CK90, and CK135 outputted through the step (a) to sample the center of the received data according to the phase control signal Vctrl. Outputting the adjusted first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135; (c) dividing the received data in half and outputting divided received data (Data2_1, Data2_2); (d) outputting delayed received data by delaying the received data for a predetermined time so that the edges of the received data Data2_1 and Data2_2 divided by the step (c) are synchronized with the edge of the received data. Doing; (e) generating and outputting the phase control signal Vctrl using the divided received data Data2_1 and Data2_2 and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted; ; And (f) sampling and outputting a center of the delayed received data using the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted. .

Objects and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a clock and data recovery circuit according to an embodiment of the present invention.

Referring to FIG. 1, the clock and data recovery circuit 1 of the present invention includes a phase locked loop circuit PLL 100, a phase interpolator 300, a divider circuit 500A, 500B, and a clock. Recovery circuits (Clock Recovery, 700A, 700B), delay buffer circuit 800, and a data decision circuit (Data Decision, 900).

The phase locked loop circuit 100 receives an external clock and generates a clock having a frequency of 1/4 of the received data rate for data recovery. The clock is further described with reference to FIGS. 2 and 3. The detailed description is as follows.

FIG. 2 is a block diagram illustrating the phase locked loop circuit 100 of FIG. 1, and FIG. 3 is a circuit diagram illustrating the oscillator 110 of FIG. 2.

As shown in FIG. 2, the phase locked loop circuit 100 includes an oscillator (VCO) 110, a first divider 120 having a CML (Current-Mode Logic) structure, and a D2S converter (Differential to Single-ended Converter). 130, a second divider 140, a phase frequency detector (PFD) 150, a charge pump, and a low pass filter (CP & LP) 160.

The oscillator 110 generates and outputs multi-phase clocks CK0, CK45, CK90, and CK135 as shown in FIG. 3 according to a control voltage input from a charge pump and a low pass filter 160 to be described later.

The first divider 120 divides the clocks CK0, CK45, CK90, and CK135 of the multi-phase outputted from the oscillator 110 in quarters, and the clock divided in quarters is the D2S converter. The signal is converted into a single-ended clock through 130 and input to the second divider 140 to be divided into 1/16.

The phase frequency detector 150 detects a difference between phase and frequency by comparing phase and frequency of the clock divided by 1/16 through the external clock and the second divider 140.

The charge pump and the low pass filter 160 increase or decrease the charge according to the difference between the phase and the frequency detected by the phase frequency detector 150, and then remove the high frequency component from the charge-decreased signal to generate a control voltage.

That is, the phase locked loop circuit 100 generates and outputs multi-phase clocks CK0, CK45, CK90, and CK135 necessary for recovering received data from an external clock.

Referring back to FIG. 1, the phase interpolation circuit 300 adjusts the phase of the clock so that the clock output from the phase locked loop circuit 100 can sample the center portion of the received data. A detailed description with reference to FIG. 4 is as follows.

4 is a diagram illustrating a waveform and the phase interpolation circuit 300 of FIG. 1.

As shown in FIG. 4, the phase interpolation circuit 300 outputs a clock output from the phase lock loop circuit 100 according to phase control signals Vctrl input from clock recovery circuits 700A and 700B to be described later. First to fourth phase interpolation circuits 300a, 300b, 300c, and 300d which adjust the phases of CK0, CK45, CK90, and CK135 to output the clocks whose phases are adjusted (INTCLK0, INTCLK45, INTCLK90, INTCLK135). .

The first phase interpolation circuit 300a outputs a phase interpolated clock INTCLK0 of clocks CK0 and CK90, and the second phase interpolation circuit 300b outputs a phase interpolated clock INTCLK45 of clocks CK45 and CK135. Outputs

In addition, the third phase interpolation circuit 300c outputs an inverting signal of the clock CK0 (that is, the falling edge signal of the clock CK0) and the phase interpolated clock INTCLK90 of the clock CK90, and the fourth phase interpolation circuit 300d. Outputs an inverting signal of clock CK45 (that is, a falling edge signal of clock CK45) and a phase interpolated clock INTCLK135 of clock CK135.

Here, the reason for using the inverted clock (falling edge of the clock) as the input of the phase interpolation circuit 300, the phase adjustment range (D2) of the interpolated clock is the duration (bit) of at least one received data This is because it must be equal to or greater than D1.

That is, in order to accurately restore the received data, the clock must sample the center portion of the received data. For this purpose, in the phase interpolation circuit 300, the edge of the clock output from the phase locked loop circuit 100 is the center of the received data. It is to adjust the phase of the clock so that it is located in the part.

Referring back to FIG. 1, the first division circuit 500A and the second division circuit 500B may reduce the speed of the reception data DATA so that the next division circuits may operate at the speed at which the subsequent circuits may operate properly. DATA) is divided in half, and at this time, the first division circuit 500A outputs received data DATA / 2_1 divided in half in synchronization with the rising edge of the received data DATA, The second division circuit 500B outputs received data DATA / 2_2 divided in half in synchronization with the falling edge of the reception data DATA.

The division of the received data DATA in this manner is due to the bandwidth of the clock recovery circuits 700A and 700B. If the received data DATA is directly input to the flip-flops of the clock recovery circuits 700A and 700B, Due to the high frequency of the received data DATA, the flip-flop reaches the limit at which the device can operate, and thus the flip-flop does not operate properly. For this purpose, the received data DATA is transferred through the division circuits 500A and 500B. It is busy.

In addition, the division circuits 500A and 500B perform the division based on the rising edge and the falling edge of the received data DATA, respectively, because the clock recovery circuits 700A and 700B described later perform more accurate clock recovery. This will be described in detail with reference to FIGS. 5 and 6.

Referring back to FIG. 1, the clock recovery circuits 700A and 700B output the received data Data / 2_1 and Data / 2_2 and the phase interpolation circuit 300 divided through the division circuits 500A and 500B. By using the phase-controlled clock (INTCLK0, INTCLK45, INTCLK90, INTCLK135) to generate a phase control signal (Vctrl) for adjusting the phase of the clock, this will be described in more detail with reference to FIGS. same.

5 is a diagram illustrating a clock recovery circuit of FIG. 1, and FIG. 6 is an operation timing diagram of the clock recovery circuit of FIG. 5.

As shown in FIG. 5, the clock recovery circuits 700A and 700B may include first to fourth D-flip flops 710, 720, 730 and 740, first and second XOR gates 750 and 760, a comparator 770, and a voltage. -A current converter (VI Converter) 780 is provided.

The first to fourth D-flip flops 710, 720, 730, and 740 are divided through the clocks INTCLK0, INTCLK45, INTCLK90, INTCLK135 whose phase is adjusted through the phase interpolation circuit 300, and the division circuits 500A and 500B. Receive data (Data / 2_1, Data / 2_2) are respectively input. The reason for using a plurality of clocks and divided received data during clock recovery is described in detail as follows.

As shown in FIG. 6, when the INTCLK0 waveform of the phase-controlled clock and the waveform of Data / 2_1 of the divided received data are examined, the rising edge of the Data / 2_1 waveform is always located at the edge portion of the INTCLK0. Because of this, it is difficult to determine the phase difference.

In other words, if only one clock phase INTCLK0 is used in clock recovery as in the conventional clock recovery circuit, the rising edge of the received data cannot always sample the edge of the clock.

That is, in the present invention, multiphase clocks CK0, CK45, CK90, and CK135 are generated through the phase-locked loop circuit 100 to solve a problem that occurs when only one phase clock is used for clock recovery. The phase is adjusted so that the edges of the clocks CK0, CK45, CK90, and CK135 are located at the center of the received data, so that the clock recovery is performed according to the clocks having the phase adjusted clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135. .

On the other hand, the more edges of the received data in clock recovery, the more the number of times of checking the phase of the received data and the clock can be more accurate clock recovery can be performed, as in the conventional clock recovery circuit based on only the rising edge when the clock recovery Dispensing the received data results in fewer edges of the received data, reducing the number of checks.

In other words, the present invention divides the data based on both the rising edge and the falling edge of the received data DATA, and performs clock recovery using the divided received data. As shown in FIG. 5, the number of rising edges of the reception data DATA and the number of rising edges of the divided reception data Data / 2_1 and Data / 2_2 are equal, so that the number of times of the clock recovery circuits 700A and 700B checks the received data. It becomes equal to the number of rising edges of DATA, so that the clock recovery can be performed more accurately.

Meanwhile, the XOR gates 750 and 760 and the selector 770 determine whether the divided received data Data / 2_1 and Data / 2_2 are faster or slower than the phase-controlled clocks INTCLK0, INTCLK45, INTCLK90 and INTCLK135. For the purpose of more detail, it will be described below.

Referring to the case of (I) of FIG. 6, in the first D-flip-flop 710, the rising edge of the divided received data DATA / 2_1 samples INTCLK0, so that D0 becomes '1' and the second D-flip-flop 710. In the flip-flop 720, the rising edge of the divided received data DATA / 2_1 samples the INTCLK90 so that D1 becomes '0'.

That is, when the divided received data DATA / 2_1 and the edge of INTCLK0 are compared, the state of (I) means that the received data is slower than the clock.

In the state of (I), a method of determining whether the received data is faster or slower than the clock is to input the D0 value and the D90 value to the XOR gate 750. That is, Exclusive-OR is performed by inputting the outputs of the first and second D flip-flops 710 and 720 to the XOR gate 750.

That is, if the D0 value and the D90 value are the same and the X1 value is '0', the received data is faster than the clock. If the D0 value and the D90 value are different, and the X1 value is '1', the received data is slower than the clock. .

The problem arises in the case of (II). In case of (II), the rising edge of the received data DATA / 2_1 divided by the first D-flip-flop 710 samples INTCLK0, so that D0 becomes '1', and the second D-flip-flop 720 The rising edge of the received data DATA / 2_1 divided by D1 samples INTCLK90, so that D1 becomes '0', and the X1 value becomes '1' as in the state (I).

That is, in the state of (II), the received data is faster than the clock as opposed to the state of (I), but the value of X1 becomes '1' in the same manner as in the state of (I). It is impossible to determine whether the received data is faster or slower than the clock.

To this end, in the clock recovery circuits 700A and 700B of the present invention, the X2 values generated through the third and fourth D-flip flops 730 and 740 and the XOR gate 760 are compared through the comparator 770 as follows. Compared with the X1 value, it is determined whether the received data is faster or slower than the clock according to the comparison result, which will be described in more detail as follows.

First, the rising edges of the received data DATA / 2_1 divided through the third and fourth D flip-flops 730 and 740 sample the INTCLK45 and INTCLK135, respectively, and the sampling values D45 and D135 are XOR gates 760. ) To print the X2 value.

Next, the comparator 770 compares the X1 value output from the XOR gate 750 with the X2 value output from the XOR gate 760, and outputs '1' if the X1 value and the X2 value are different from each other. If the X1 value and the X2 value are the same, '0' is output. Here, the comparator 770 has an XOR gate characteristic that receives an output of the XOR gate 750 and an output of the XOR gate 760 and outputs a difference between a phase of the received data and the clock phase.

For example, in FIG. 6, when looking at the output S of the selector 770, when X1 is '1' and X2 is '0', S is '1', X1 is '1' and X2 is '1'. It can be seen that S becomes '0'.

That is, if the S value is '0', the received data is faster than the clock. If the S value is '1', the received data is slower than the clock.

As such, the clock recovery circuit 700A samples the INTCLK0, INTCLK45, INTCLK90, and INTCLK135 using the divided received data Data / 2_1 and Data / 2_2, respectively, and uses the clocks to receive the received data in phase with the clock. Determine if it is fast or slow.

Meanwhile, in the present embodiment, multi-phase clocks CK0, CK45, CK90, and CK135 having phases of 0 °, 45 °, 90 °, and 135 ° are generated to use a 1/4 frequency clock of the received data rate. Although the rising and falling edges of the multi-phase clocks (CK0, CK45, CK90, and CK135) were used for clock recovery, for example, a clock recovery circuit of bang-bang structure is used when a 10 GHz clock is used for 10 Gbps data. It is sufficient to use a clock of. In this case, the rising edge or falling edge of the received data samples the edge portion of the clock to determine whether the clock is faster or slower than the received data, depending on whether the sampling value is '0' or '1'. .

For example, if one clock is used in the clock recovery circuit, if the rising edge of the received data samples the left portion '0' of the rising edge of the clock, it can be determined that the received data is faster than the clock, and thus the clock The phase of is adjusted to the edge of the received data.

Referring back to FIG. 1, the data determination circuit 900 uses a clock whose phase is adjusted to sample centers of received data through the clock recovery circuits 700A and 700B and the phase interpolation circuit 300. For receiving data, the received data delayed through the delay buffer circuit 800 using only two clocks INTCLK45 and INTCLK135 out of phase-controlled clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135. Is restored and output as output data OUTDATA, which will be described in more detail with reference to FIGS. 7 and 8 as follows.

FIG. 7 is a diagram illustrating the data determination circuit 900 of FIG. 1, and FIG. 8 is an operation timing diagram of the data determination circuit of FIG. 7.
As illustrated in FIG. 7, the data determination circuit 900 may include first through fourth D-flip flops for sampling and outputting the center of delayed received data through the delay buffer circuit 800. 910,920,930,940.
The first D-flip-flop 910 and the third D-flip-flop 930 output the delayed received data at the rising and falling edges of the clock INTCLK45, and the second D-flip-flop 920 And the fourth D-flip-flop 940 output the delayed received data at the rising and falling edges of the clock INTCLK135.

Referring to FIG. 8, when clocks INTCLK45 and INTCLK135 and delayed received data are input to the data determination circuit 900, the delayed received data at the rising and falling edges of the clock INTCLK45 is centered. Is sampled, and a sampling value of '11' is output, and the center of the delayed received data is sampled at the rising edge and the falling edge of the clock INTCLK135 to output the sampling value of '01'.

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In this case, the clocks INTCLK45 and INTCLK135 are clocks whose phases are adjusted to sample centers of the received data through the clock recovery circuits 700A and 700B and the phase interpolation circuit 300.

That is, among the phase-controlled clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135, in which the center of the received data is sampled through the phase interpolation circuit 300, INTCLK45 and INTCLK135 perform data restoration in the data determination circuit 900. The data output from the data determination circuit 900 is 1: 4 demultiplexed and output.

Referring back to FIG. 1, the delay buffer circuit 800 is configured to synchronize the edges of the received data Data2_1 and Data2_2 and the edges of the received data DATA through the division circuits 500A and 500B. This is for delaying the received data DATA by the delay time of the frequency dividing circuits 500A and 500B. This will be described in more detail with reference to FIGS. 9A and 9B.

FIG. 9A is a diagram illustrating a data restoration process when the delay buffer circuit is not used, and FIG. 9B is a diagram illustrating a data restoration process when the delay buffer circuit is used as in the present invention.

As shown in FIG. 9A, when the delay buffer circuit is not used, the reception data DATA / 2 divided through the division circuits 500A and 500B are delayed and output by the delay time of the division circuit element. In this case, the data determination circuit 900 receives the non-delayed reception data DATA, but the clock recovery circuits 700A and 700B restore the clock to match the edge of the delayed reception data DATA / 2. As a result, the edges of the restored clock and the received data DATA do not coincide, and thus accurate data cannot be recovered.

On the other hand, as shown in FIG. 9B, even when the delay buffer circuit is used, even if the received data DATA / 2 divided through the division circuits 500A and 500B are delayed and output by the delay time of the division circuit element. That is, even when the clock recovery circuits 700A and 700B restore the clock to the edge of the delayed received data, the received data Delayed_DATA delayed by the delay buffer circuit 800 for a predetermined time is not determined. Since it is input to 900, it can be seen that the edges of the divided received data DATA / 2 and the delayed received data are matched to accurately restore the received data.

Meanwhile, in the present embodiment, it has been described that received data delayed by a predetermined time through the delay buffer circuit 800 is input to the data determination circuit 900 in order to correctly restore the received data. However, the delay buffer circuit 800 is described. ) May be omitted for simplicity of configuration.

As described above, the present invention proposes a clock and data recovery circuit structure of a new method of recovering a clock by using a 1/4 clock frequency of a data rate, so that even when a high frequency clock cannot be produced, a quarter of the data rate can be obtained. The advantage is that the clock frequency can be used to process high speed data. In addition, the present invention, if only the oscillator capable of generating a high frequency clock frequency can be easily designed, there is an advantage that it is possible to simply implement the clock and data recovery circuit without using multiple flip-flops.

So far, the present invention has been described with reference to the preferred embodiments, and those skilled in the art to which the present invention belongs may be embodied in a modified form without departing from the essential characteristics of the present invention. You will understand. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

As described above, according to the present invention, by presenting a clock and data recovery circuit structure of a new method of recovering the clock by using the 1/4 clock frequency of the data rate, even in a situation where a high frequency clock can not be made It is effective to process high speed data using 1/4 clock frequency of.

In addition, according to the present invention, since a high speed clock and data recovery circuit can be implemented without using an inductor, the size of the entire circuit can be reduced.

Claims (20)

A phase locked loop circuit which receives an external clock and generates and outputs multi-phase clocks CK0, CK45, CK90, and CK135 having a quarter frequency of a received data rate; The first phase of which the phase is adjusted by adjusting the phase of the multi-phase clocks CK0, CK45, CK90, and CK135 output from the phase-locked loop circuit so as to sample the center of the received data according to a phase control signal Vctrl. A phase interpolation circuit for outputting the fourth to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135; A divider circuit for dividing the received data in half and outputting divided received data (Data2_1, Data2_2); A delay buffer circuit for delaying the received data by a predetermined time and outputting delayed received data so that the edges of the received data Data2_1 and Data2_2 divided by the division circuit are synchronized with the edge of the received data; The phase control signal Vctrl using the received data Data2_1 and Data2_2 divided through the division circuit and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. A clock recovery circuit which generates and outputs a signal; And Determining data output by sampling the center of delayed received data through the delay buffer circuit using the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. And a circuit comprising a circuit. The circuit of claim 1, wherein the phase locked loop circuit comprises: An oscillator for generating and outputting multi-phase clocks CK0, CK45, CK90, and CK135 according to the control voltage; A first divider for dividing the clock output from the oscillator by a quarter; A D2S converter (Differential to Single-ended Converter) for converting a clock divided in the first divider into a single-ended clock; A second divider for dividing the clock output from the D2S converter by a quarter; A phase frequency detector for comparing a phase and a frequency of the clock divided by the external clock and the second divider to detect a difference between phase and frequency; And Clock and data comprising a charge pump and a low pass filter for generating the control voltage by increasing or decreasing the charge in accordance with the difference between the phase and the frequency detected by the phase frequency detector to remove the high frequency components from the charge-decreased signal Restoration circuit. The method of claim 1, wherein the phase interpolation circuit, The first to fourth phases of which the phases are adjusted by adjusting the phases of the multi-phase clocks CK0, CK45, CK90, and CK135 output from the phase-locked loop circuit according to the phase control signal Vctrl output from the clock recovery circuit. And first to fourth phase interpolation circuits for outputting clocks (INTCLK0, INTCLK45, INTCLK90, INTCLK135). 4. The clock and data recovery circuit of claim 3, wherein the phase adjustment range of the phase interpolation circuit is equal to or greater than the bit duration of one received data. The method of claim 1, wherein the frequency division circuit, A first division circuit for dividing the received data by half in synchronization with the rising edge of the received data and outputting the divided received data DATA / 2_1; And And a second division circuit for dividing the received data in half in synchronization with the falling edge of the received data and outputting the divided received data (DATA / 2_2). The method of claim 5, wherein the clock recovery circuit, The phase control signal (B) using the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit and the received data DATA / 2_1 distributed through the first division circuit. A first clock recovery circuit generating and outputting Vctrl); And The phase control signal (B) using the received data DATA / 2_2 divided through the second division circuit and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. And a second clock recovery circuit for generating and outputting Vctrl). The method of claim 6, The first clock recovery circuit is, The phase is determined by determining whether the received data Data2_1 divided through the first division circuit is faster or slower than the first through fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. Generates and outputs a control signal (Vctrl). The second clock recovery circuit, The phase is determined by determining whether the received data Data2_2 divided through the second divider circuit is faster or slower than the first through fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. A clock and data recovery circuit, characterized in that for generating and outputting a control signal (Vctrl). The method of claim 6, wherein the first clock recovery circuit and the second clock recovery circuit, First to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 each of which receives received data Data2_1 and Data2_2 divided through the first and second divider circuits as clocks, and whose phases are adjusted through the phase interpolation circuit. First to fourth D-flip flops each receiving data as data; First and second XOR gates for exclusively ORing the outputs of the first to fourth D flip-flops; The phases of the divided received data Data2_1 and Data2_2 according to the output of the first and second XOR gates, and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. A selector for selecting and outputting a voltage signal representing a phase difference; And And a voltage-to-current converter for converting the voltage signal output from the selector into a current signal, respectively. delete delete delete The method of claim 1, The data determination circuit includes first to fourth D-flip flops, And delayed received data through the delay buffer circuit as data of the first to fourth D-flip-flops. delete The method of claim 12, The first D-flip-flop and the third D-flip-flop are raised from the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 of which phases are adjusted through the phase interpolation circuit. And sampling and outputting a center of the delayed received data at the falling edge. The second D flip-flop and the fourth D flip-flop are raised by the fourth clock INTCLK135 among the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through the phase interpolation circuit. And sampling and outputting a center of the delayed received data at a falling edge. (a) receiving an external clock and generating and outputting multi-phase clocks CK0, CK45, CK90, and CK135 having a quarter frequency of a received data rate; (b) Adjust the phase of the multi-phase clocks CK0, CK45, CK90, and CK135 outputted through the step (a) to sample the center of the received data according to the phase control signal Vctrl. Outputting the adjusted first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135; (c) dividing the received data in half and outputting divided received data (Data2_1, Data2_2); (d) outputting delayed received data by delaying the received data for a predetermined time so that the edges of the received data Data2_1 and Data2_2 divided by the step (c) are synchronized with the edge of the received data. Doing; (e) generating and outputting the phase control signal Vctrl using the divided received data Data2_1 and Data2_2 and the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted; ; And and (f) sampling and outputting a center of the delayed received data using the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted. And how to restore data. The method of claim 15, wherein step (a), A first step of generating and outputting the multi-phase clocks CK0, CK45, CK90, and CK135 according to the control voltage; Dividing the multi-phase clock by 1/4; Converting the clock divided by quarter into a single-ended clock and then splitting the converted clock back into quarters; A fourth step of detecting a difference between a phase and a frequency by comparing a phase and a frequency of the clock divided through the third step with the external clock; And And a fifth step of generating the control voltage by increasing or decreasing charge in accordance with the detected phase and frequency and removing high frequency components from the charge-decreased signal. delete The method of claim 15, wherein step (c) is Dividing the received data in half in synchronization with the rising edge of the received data and outputting the divided received data (DATA / 2_1); And And dividing the received data in half in synchronization with the falling edge of the received data and outputting the divided received data (DATA / 2_2). The method of claim 15, wherein step (e) The phase control signal Vctrl is generated by determining whether the divided received data DATA / 2_1 and DATA / 2_2 are faster or slower than the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted. Clock and data recovery method comprising the step of outputting. The method of claim 15, wherein step (f), The delayed received data at the rising and falling edges of the second and fourth clocks INTCLK45 and INTCLK135 of the first to fourth clocks INTCLK0, INTCLK45, INTCLK90, and INTCLK135 whose phases are adjusted through step (b). And sampling the center of Delayed DATA.

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