KR20030086107A - Phase detector for high-speed clock recovery circuit - Google Patents

Abstract

PURPOSE: A phase detector for high-speed clock circuit is provided to process the continuous input data within a short time by using the phase detector including two exclusive OR gates. CONSTITUTION: A high-speed clock circuit includes a phase detector, a charge pump, and a voltage controlled oscillator to recover clocks and data from serial data. The phase detector for high-speed clock circuit includes the first exclusive OR gate(101) and the second exclusive OR gate(102). The first exclusive OR gate(101) receives a phase clock signal of 0 degree and a phase clock signal of 90 degrees from the voltage controlled oscillator and outputs a data priority signal to the charge pump. The second exclusive OR gate(102) is used for receiving the phase clock signal of 0 degree and an input data signal and outputting a data delay signal to the charge pump.

Description

Phase Detector for High Speed Clock Recovery Circuit {PHASE DETECTOR FOR HIGH-SPEED CLOCK RECOVERY CIRCUIT}

The present invention relates to a phase detector included in a clock recovery circuit used in a data communication system.

The optical data rate used in the Internet backbone requires high speed operation of 2.5Gb / s-10Gb / s, and the high speed data communication system has a circuit for recovering clock and data from serial data. CDR circuit ') is necessary. The clock recovery circuit is largely composed of a phase / frequency detector, a clock signal generator, a data regenerator, and the like.

In the field of gigabit (Gb / s) optical communication data transmission and reception, the data transmission rate is determined according to a predetermined standard (OC-48, OC-192, etc.), so phase detection is more important than wide frequency detection of data. Therefore, the performance of the phase detector circuit plays an important role in the performance of the clock recoverer.

In the case of a high-speed CMOS (complementary metal oxide semiconductor) CDR circuit, a phase / frequency detection circuit using a complex state machine and a voltage controlled oscillator (VCO) are connected to restore a clock. Currently, various types of phase frequency detectors (PFDs) are used. Specifically, a PFD or a dynamic PFD using a general state machine is used to construct a fast CMOS clock recovery circuit. Mainly used for.

Since the circuits are mainly applied to a clock recovery circuit operating in a wide frequency domain, the circuits include a plurality of flip-flop structures and logic gates. In addition, when a continuous '1' or '0' is input, there is a problem that a separate voltage hold circuit is required because the voltage for adjusting the voltage control oscillator is not preserved.

In addition, a CMOS CDR circuit has been proposed using an oversampling method that uses only a digital circuit and simultaneously detects phase and frequency of input data using fast multi-phase clocks. However, when using this oversampling method, there is a problem that a relatively large chip area is required in the restoration circuit and a large amount of power is consumed.

In addition, since high speed data communication for optical communication does not require a wide range of frequency acquisition functions, there is a need for a phase detector that responds to high speed operation and has a simple structure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a high performance and high speed phase detector that can be implemented in a small chip area and can be applied to a high speed clock and data recovery circuit of several Gb / s. It is done. In addition, even when continuous '1' or '0' data is input, it is not necessary to have a separate voltage hold circuit and operates at high speed and operates by restoring a clock that is 1/2 of the data rate. It is an object of the present invention to provide a phase detector that is easy and has a power saving effect.

1 is a clock recovery circuit diagram including a phase detector according to the present invention;

2 is a detailed configuration diagram of a phase detector according to the present invention;

3 is a view showing a data preceding signal and a delay signal generation form during phase detection;

4 is a view showing a data leading signal and a delay signal generation mode when the clock speed is faster than the data rate;

5 is a view showing a data leading signal and a delay signal generation mode when the clock speed is slower than the data rate;

6 is a view showing a data leading signal and a delay signal generation form when the input data is consecutive '0';

7 is a view showing a data leading signal and a delay signal generation form when the input data is a continuous '1';

8 is a diagram illustrating a recovery clock and a data signal of random input data;

In order to achieve the above object, the present invention outputs a data preceding signal by inputting a 0 degree phase clock signal (0 CLK) and a 90 degree phase clock signal (90 CLK) output from the voltage control oscillator 300 of the clock recovery circuit. And a second exclusive logic logic gate (101) for inputting a zero degree phase clock signal (0 CLK) and an input data signal and outputting a data delay signal. A phase detector for a high speed clock recovery circuit is provided.

Unlike a phase / frequency detector (PFD) based on a flip-flop and a state machine or a phase detector (PD) in the form of an analog circuit, the phase detector 100 for a fast clock recovery circuit according to the present invention is a VCO (300). Of the clocks from < RTI ID = 0.0 > 1) < / RTI > and two exclusive-OR logic gates 101 and 102 that take input data as input, and the 0 degree phase and 90 degree phase clock signals (0 CLK and 90 CLK). It is composed. The output signal of the phase detector 100 according to the present invention is generated by performing an exclusive logical sum operation on the input data and two clock signals supplied from the VCO 300, and using the phase detector 100, the VCO 300. By designing a clock that is one half the data rate, it alleviates the challenges of high-speed VCO design and reduces power consumption. Accordingly, in the final data restoration, a double edge operation flip-flop is required to extract data using the rising edge and the falling edge of the clock generated by the VCO 300.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a clock recovery circuit including a phase detector 100 according to the present invention, and FIG. 2 is a detailed configuration diagram of the phase detector 100 according to the present invention. The phase detector 100 is composed of two two input exclusive logic logic gates 101 and 102, and an input signal of the phase detector 100 is zero degrees among four different phase reconstruction clocks generated by the VCO 300. Phase clock signal (0 CLK), 90 degree phase clock signal (90 CLK), and data input from the outside.

The input 0 CLK signal and the 90 CLK signal enter the input signal of one exclusive logical logic logic gate 101 and generate and output a preceding phase difference signal, that is, a data preceding signal based on the phase relationship between the data and the clock. On the other hand, the input 0 CLK signal and the input data signal is input to another exclusive logic logic gate 102 to generate a delay phase difference signal, that is, a data delay signal based on the phase relationship between the data and the clock. The preceding phase difference signal and the delayed phase difference signal are eventually connected to the voltage generation circuit of the VCO 300 and used to generate a new recovery clock. That is, the data preceding and delayed signals output from the above are connected to the charge pump circuit 200 to supply or consume charges according to the signal to change the voltage of the VCO 300 to adjust the phase and frequency of the generated clock.

For example, when a data delay voltage pulse occurs, charge is supplied from a power supply to increase the VCO 300 control voltage to increase the frequency of VCO 300 to catch up with the phase. On the contrary, when a data leading voltage pulse occurs, the charge is discharged to the ground to lower the control voltage of the VCO 300 to lower the frequency of the VCO 300 so that the phase is delayed to correctly phase the data and the clock.

When the phase detector 100 according to the present invention is used, the VCO 300 of the clock recovery circuit outputs a clock that is 1/2 of the data rate. By sampling and restoring data on the rising and falling edges of the generated clock, high-speed data recovery is possible even with a clock that is half the data rate.

FIG. 3 shows the data preceding signal and delay signal generation patterns during phase detection, when the phase between the data and the clock is aligned (phase locked state), when the data phase precedes (data phase leading), and the data phase is delayed. The signal generated by the phase detector 100 is displayed for the three cases (clock phase leading). Each case will be described below.

First, when the rising and falling edges of the 0 CLK signal are in the center of the data, the system operates in phase locked or phase locked. At this time, the data leading signal and the data delay signal, which are output signals of the phase detector 100, generate a signal having the same width at the same time, and thus control the connected VCO 300 because the amount of charge charged and discharged in the charge pump circuit 200 is the same. There is no change in voltage. Therefore, the phase locked state is maintained. In the conventional phase detection circuit of another structure, since the signals for charge charge / discharge are lost when the phase is locked, a separate voltage hold circuit is required to maintain the VCO control voltage constant. However, in the case of the present invention, since the data leading signal and the delay signal for determining the charge pump during phase locking are continuously made the same width, there is no voltage change even if they continue to charge / discharge the actual charge. 300) The control voltage hold circuit is not necessary.

Next, when the input data is in phase faster than 90 CLK, the high state of the data delay signal is shorter than that of the data leading signal, so that the extra value of the data leading signal at the two signal differences causes the charge pump ( It acts as a charge reduction signal of 200). The charge reduction leads to a drop in the VCO 300 control voltage, which results in a reduction in the clock period of the VCO 300 so that the clock phase can keep pace with the phase value of the input data.

Finally, when the input data is in phase slower than 90 CLK, the high state of the data delay signal is longer than that of the data preceding signal, so that the extra value of the data delay serves as the charge increase signal of the charge pump. The increase in charge leads to an increase in the control voltage of the VCO 300 which leads to an increase in the clock period of the VCO 300, so that the clock phase can keep pace with the phase of the input data.

The same applies if the frequency is different between the input data and the clock. As shown in Fig. 4, when the frequency of the input data is slower than that of the corresponding clock speed, the high state of the data delay signal is longer than that of the data preceding signal, so that the extra value of the data delay signal is the charge pump. Act as an increase signal of the charge (200). The increase in charge at the VCO 300 control voltage node leads to an increase in voltage, which results in an increase in the clock period of the VCO 300 resulting in a decrease in clock speed. Thus, the clock phase value can keep pace with the phase value of the input data. In the opposite case, i.e., when the frequency of the input data is faster than that of the corresponding clock speed, as shown in Fig. 5, the remaining portion of the data leading signal acts as a charge reduction, which leads to a reduction in the clock period and restores it. The clock speeds up.

6 and 7 illustrate the generation form of the data leading signal and the delay signal when the input data is continuous '0' and the continuous '1', respectively. 6 and 7, when the input data stays in the '1' or '0' state for a long time, the high state values of the data leading signal and the data delay signal are alternately repeatedly displayed. However, since the average charge value does not change, the circuit remains in a stable locked state.

8 illustrates an experimental result of data restoration and clock restoration in response to actual random input data, and each graph represents data input, recovered data, and recovered clock.

The phase detector according to the present invention adjusts the clock in response to a narrow range of data frequency changes, but frequency locking may occur in the harmonics of the data. Therefore, it is desirable to apply to a system operating on data rate fluctuations in which the data frequency fluctuation is 2 times or less and 0.5 times or more.

As described above, when the phase detectors of the two exclusive logic structures according to the present invention are used, even when input data of '1' or '0' that is continuous in a small chip area does not require a separate voltage hold circuit, it operates at high speed. The clock recovery circuit can be designed. In addition, when the phase detector according to the present invention is used, the VCO of the clock recovery circuit recovers a clock of 1/2 the data rate, thereby reducing power consumption.

Claims (4)

In a phase detector for a high speed clock recovery circuit used in a high speed clock recovery circuit for recovering clock and data from serial data, including a phase detector, a charge pump and a voltage controlled oscillator (VCO), A first exclusive logical sum logic gate configured to output a data leading signal to the charge pump by inputting a zero degree phase clock signal and a ninety degree phase clock signal output from the VCO; And a second exclusive logic sum logic gate for inputting the zero degree phase clock signal and the input data signal and outputting a data delay signal to the charge pump. The method of claim 1, And said phase detector is used to recover a clock at which said VCO is one-half of the data rate. A phase detector for a high speed clock recovery circuit used in a high speed clock recovery circuit for recovering clock and data from serial data, including a phase detector, a charge pump and a VCO, and a zero degree phase clock signal output from the VCO of the clock recovery circuit; A first exclusive logic logic gate for outputting a data leading signal to the charge pump with a 90 degree phase clock signal as an input, and a data delay signal for outputting a data delay signal to the charge pump with the 0 degree phase clock signal and an input data signal as inputs; And include a second exclusive logic logic gate to When the input data signal is in phase with the 90-degree phase clock signal, the data leading signal and the data delay signal are generated with the same width and output. When the input data signal is in phase faster than the 90-degree phase clock signal, a high state of the data delay signal is generated and output so as to be shorter than a high state of the data preceding signal. And outputting such that the high state of the data delay signal is longer than the high state of the data preceding signal when the input data signal is in phase slower than the 90 degree phase clock signal. The method of claim 3, wherein The phase detector, when the input data signal is a continuous '0' or '1', the high-speed clock recovery characterized in that the high state value of the data preceding signal and the data delay signal is generated to alternately repeat Phase detection method for circuits.