CN116865747A

CN116865747A - Frequency locking control method, frequency locking circuit and chip of phase-locked loop

Info

Publication number: CN116865747A
Application number: CN202310886377.0A
Authority: CN
Inventors: 赵东艳; 杨小坤; 李德建; 冯曦; 杨立新; 谭浪
Original assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2023-07-18
Filing date: 2023-07-18
Publication date: 2023-10-10

Abstract

The application discloses a frequency locking control method, a frequency locking circuit and a chip of a phase-locked loop. Because the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal, the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

Description

Frequency locking control method, frequency locking circuit and chip of phase-locked loop

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a frequency locking control method, a frequency locking circuit, and a chip for a phase locked loop.

Background

The components of common telecommunications, computer and other digital electronic applications have very stringent timing requirements in order for the electronic device to perform very accurate operations. A phase locked loop (phase locked loop, PLL) that produces a stable frequency and synchronizes the output signal with a reference signal is a very widely used circuit in electronic control systems. The phase locked loop may include a frequency locked loop having a coarse locking function and an undersampled phase locked loop that performs a fine locking based on the frequency locked by the frequency locked loop.

In the related art, during the locking process of the undersampled phase-locked loop, the frequency locked loop and the undersampled phase-locked loop may be switched back and forth, resulting in the phenomenon of output frequency oscillation.

Disclosure of Invention

The present application aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present application is to provide a frequency lock control method, a frequency lock circuit, and a chip of a phase locked loop, in which the frequency lock control circuit controls the frequency lock loop to be in an off state based on a first dead zone width when detecting that the frequency lock loop is in a locked state. The first dead zone width is larger than the phase difference between the reference clock signal received by the phase-locked loop and the frequency-division clock signal output by the frequency divider after the frequency-locked loop is in a locked state, so that the frequency-locked loop can be kept in an off state all the time in the process of frequency locking of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

In one aspect, a frequency lock control circuit of a phase-locked loop is provided, the phase-locked loop including: a frequency locked loop and an undersampled phase locked loop, the frequency locked control circuit comprising: a state detection circuit and a state control circuit;

the state detection circuit is used for detecting the state of the frequency locking loop, and outputting a first control signal to the state control circuit when detecting that the frequency locking loop is in a locking state;

the state control circuit is used for responding to a first control signal, outputting a first indication signal to the undersampled phase-locked loop and the frequency locking loop respectively, wherein the first indication signal is used for indicating that the frequency locking loop is in an open state based on the first dead zone width and indicating the undersampled phase-locked loop to perform frequency locking;

the first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, wherein the reference clock signal is a clock signal received by a phase-locked loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output after the phase-locked loop is in a locked state.

Optionally, the state detection circuit is further configured to output a second control signal to the state control circuit when detecting that the frequency locked loop is in the unlocked state;

The state control circuit is also used for responding to a second control signal and outputting a second indication signal to the undersampled phase-locked loop and the frequency locking loop respectively, wherein the second indication signal is used for indicating that the undersampled phase-locked loop is in a disconnected state and indicating that the frequency locking loop performs frequency locking based on a second dead zone width, and the second dead zone width is smaller than a preset phase.

Optionally, the state detection circuit is configured to:

when the first clock signal and the second clock signal output by the dead zone phase discriminator of the frequency locking loop are the same and the third clock signal and the fourth clock signal output by the dead zone phase discriminator are the same, determining that the frequency locking loop is in a locking state;

determining that the frequency locked loop is in an unlocked state when the first clock signal and the second clock signal are different and the third clock signal and the fourth clock signal are different;

the first clock signal and the second clock signal are generated by the dead zone phase discriminator according to the reference clock signal and the frequency division clock signal, the third clock signal is generated by the dead zone phase discriminator according to the first clock signal and the dead zone width, the fourth clock signal is generated by the dead zone phase discriminator according to the second clock signal and the dead zone width, and the dead zone width comprises the first dead zone width or the second dead zone width.

Optionally, the state detection circuit includes: the first detection sub-circuit, the first control sub-circuit and the second detection sub-circuit;

the output end of the first detection sub-circuit is connected with the first input end of the first control sub-circuit, the input end of the first detection sub-circuit is used for being connected with the output end of the dead zone phase discriminator, when the first clock signal and the second clock signal output by the dead zone phase discriminator are different, the first pulse signal is output to the first control sub-circuit, and when the first clock signal and the second clock signal are the same, the second pulse signal is output to the first control sub-circuit;

the second detection sub-circuit is connected with the first control sub-circuit and is used for being connected with the dead zone phase discriminator, outputting a third pulse signal to the first control sub-circuit when a third clock signal and a fourth clock signal output by the dead zone phase discriminator are different, and outputting a fourth pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal are the same;

the first control sub-circuit is also connected with the state control circuit, and the first control sub-circuit is used for outputting a first control signal to the state control circuit when receiving the second pulse signal and the fourth pulse signal and outputting a second control signal to the state control circuit when receiving the first pulse signal and the third pulse signal.

Optionally, the state control circuit is configured to:

when the time length of receiving the first control signal reaches the first time length, responding to the first control signal, and respectively outputting first indication signals to the undersampled phase-locked loop and the frequency locking loop;

and outputting a locking signal when the time period of outputting the first indication signal to the undersampled phase-locked loop reaches the second time period.

Optionally, the state control circuit is further configured to connect to an output end of a frequency divider of the frequency locked loop, and determine that a duration of receiving the first control signal reaches a first duration when the number of pulses of the received frequency-divided clock signal reaches the first number after receiving the first control signal;

after the first indication signal is output to the undersampled phase-locked loop, when the number of pulses of the received frequency division clock signal reaches a second number, determining that the duration of outputting the first indication signal to the undersampled phase-locked loop reaches a second duration.

Optionally, the state control circuit includes: the output end of the first counter is connected with the frequency locking loop and the undersampled phase locking loop, and the input end of the first counter is connected with the output end of the state detection circuit; a first counter for:

Responding to a first control signal output by the state detection circuit, counting the number of pulses of the divided clock signal, and outputting a first indication signal to the frequency locking loop and the undersampled phase locking loop when the number of pulses reaches a first number;

and resetting in response to a second control signal output by the state detection circuit, and outputting a second indication signal to the frequency locking loop and the undersampled phase-locked loop respectively.

Optionally, the state control circuit further includes: a second control sub-circuit and a second counter;

the output end of the first counter is connected with the input end of the second control sub-circuit, and the first counter is also used for responding to the second control signal to output a second indication signal to the second control sub-circuit, and outputting the first indication signal to the second control sub-circuit when the number of pulses reaches a first number;

the output end of the second control sub-circuit is connected with the input end of the second counter, and the second control sub-circuit is used for responding to the second indication signal, outputting a reset signal to the second counter and outputting an enabling signal to the second counter responding to the first indication signal;

the clock end of the second counter is used for being connected with the output end of the frequency divider, resetting is conducted in response to the reset signal, the number of pulses of the divided clock signal is counted in response to the enabling signal, and a locking signal is output when the number of pulses reaches the second number.

In another aspect, a phase locked loop is provided, the phase locked loop comprising: a frequency locked loop and an undersampled phase locked loop;

the frequency locking loop is used for receiving a first indication signal output by the state control circuit and is in an off state based on a first dead zone width in response to the first indication signal;

the undersampled phase-locked loop is used for receiving a first indication signal output by the state control circuit and responding to the first indication signal to perform frequency locking;

Optionally, the frequency locking loop is further configured to receive a second indication signal output by the state control circuit, and perform frequency locking based on a second dead zone width in response to the second indication signal, where the second dead zone width is smaller than the preset phase;

the undersampled phase locked loop is further configured to receive a second indication signal and to be in an off state in response to the second indication signal.

Optionally, the frequency locked loop further comprises: a dead zone phase detector;

The input end of the dead zone phase discriminator is connected with the output end of the frequency divider, the output end of the dead zone phase discriminator is used for being connected with the input end of the state detection circuit, a first clock signal and a second clock signal are generated according to the reference clock signal and the frequency division clock signal, and the first clock signal and the second clock signal are output to the state detection circuit;

the method includes generating a third clock signal from the first clock signal and a dead zone width, generating a fourth clock signal from the second clock signal and the dead zone width, and outputting the third clock signal and the fourth clock signal to the state detection circuit, the dead zone width including the first dead zone width or the second dead zone width.

Optionally, the frequency locked loop includes: a frequency divider;

and the frequency divider is used for dividing the frequency of the signal output by the phase-locked loop and outputting a frequency division clock signal obtained by frequency division to the state control circuit.

In still another aspect, a frequency lock control method of a phase locked loop is provided, and is applied to a frequency lock control circuit, the method includes:

determining a state of a frequency locking loop in the phase-locked loop;

outputting a first indication signal to an undersampled phase-locked loop and a frequency locked loop in the phase-locked loop when the frequency locked loop is in a locked state;

The first indication signal is used for indicating that the frequency locking loop is in an off state based on a first dead zone width, and indicating that the undersampled phase locking loop performs frequency locking, the first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, and the reference clock signal is a clock signal received by the phase locking loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output after the phase-locked loop is in a locked state.

Optionally, the method further comprises:

when the frequency locking loop is in an unlocked state, outputting second indication signals to the undersampled phase-locked loop and the frequency locking loop respectively, wherein the second indication signals are used for indicating that the undersampled phase-locked loop is in a disconnected state and indicating that the frequency locking loop performs frequency locking based on a second dead zone width, and the second dead zone width is smaller than a preset phase.

Optionally, determining a state of a frequency locked loop in the phase locked loop includes:

when the first clock signal and the second clock signal output by the dead zone phase discriminator in the frequency locking loop are the same and the third clock signal and the fourth clock signal output by the dead zone phase discriminator are the same, determining that the frequency locking loop is in a locking state;

Optionally, when detecting that the frequency locked loop is in the locked state, outputting a first indication signal to the undersampled phase locked loop and the frequency locked loop, including:

and outputting a first indication signal to the undersampled phase-locked loop and the frequency locked loop when the time length of the frequency locked loop in the locked state reaches a first time length.

Optionally, the method further comprises:

after the frequency locking loop is in a locking state, when the number of pulses of the received frequency division clock signal reaches a first number, determining that the duration of the frequency locking loop in the locking state reaches a first duration;

And outputting a locking signal when the time period for outputting the first indication signal to the undersampled phase-locked loop reaches the second time period.

Optionally, the method further comprises:

In yet another aspect, a frequency lock control method of a phase-locked loop is provided, applied to the phase-locked loop, where the phase-locked loop includes a frequency locked loop and an undersampled phase-locked loop; the method comprises the following steps:

the frequency locking loop receives a first indication signal output by the frequency locking control circuit and is in an off state based on a first dead zone width in response to the first indication signal;

the undersampled phase-locked loop receives a first indication signal and performs frequency locking in response to the first indication signal;

Optionally, the method further comprises:

the frequency locking loop receives a second indication signal output by the frequency locking control circuit and responds to the second indication signal to perform frequency locking based on a second dead zone width, wherein the second dead zone width is smaller than a preset phase;

the undersampled phase locked loop receives the second indication signal and is in an off state in response to the second indication signal.

Optionally, the frequency locked loop further comprises: a dead zone phase detector; the method further comprises the steps of:

the dead zone phase detector generates a first clock signal and a second clock signal from the reference clock signal and the divided clock signal, generates a third clock signal from the first clock signal and the dead zone width, generates a fourth clock signal from the second clock signal and the dead zone width, and outputs the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to the frequency lock control circuit, the dead zone width including the first dead zone width or the second dead zone width.

Optionally, the frequency locked loop includes: a frequency divider; the method further comprises the steps of:

the frequency divider divides the frequency of the signal output by the phase-locked loop and outputs a frequency-divided clock signal obtained by the frequency division to the frequency locking control circuit.

In yet another aspect, a frequency locking circuit is provided, the frequency locking circuit comprising: frequency lock control circuit and phase-locked loop, frequency lock control circuit includes: a state detection circuit and a state control circuit, the phase locked loop comprising: a frequency locked loop and an undersampled phase locked loop;

the state control circuit is used for responding to the first control signal and outputting a first indication signal to the undersampled phase-locked loop and the frequency locked loop respectively;

the frequency locking loop is used for responding to a first indication signal and is in an off state based on a first dead zone width, the first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, and the reference clock signal is a clock signal received by the phase-locked loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output after the phase-locked loop is in a locked state;

the undersampled phase locked loop is configured to frequency lock in response to the first indication signal.

The state control circuit is also used for responding to a second control signal and outputting a second indication signal to the undersampled phase-locked loop and the frequency-locked loop respectively;

the frequency locking loop is used for responding to the second indication signal and carrying out frequency locking based on a second dead zone width, and the second dead zone width is smaller than the preset phase;

the undersampled phase locked loop is configured to be in an off state in response to the second indication signal.

Optionally, the frequency locked loop further comprises: and the dead zone phase discriminator is respectively connected with the frequency divider and the state detection circuit and is used for:

generating a first clock signal and a second clock signal according to the reference clock signal and the frequency division clock signal, and outputting the first clock signal and the second clock signal to the state detection circuit;

generating a third clock signal according to the first clock signal and the dead zone width, generating a fourth clock signal according to the second clock signal and the dead zone width, and outputting the third clock signal and the fourth clock signal to the state detection circuit, wherein the dead zone width comprises the first dead zone width or the second dead zone width;

a state detection circuit for determining that the frequency locked loop is in a locked state when the first clock signal and the second clock signal are the same and the third clock signal and the fourth clock signal are the same; when the first clock signal and the second clock signal are different and the third clock signal and the fourth clock signal are different, it is determined that the frequency locked loop is in an unlocked state.

the input end of the first detection sub-circuit is used for being connected with the output end of the dead zone phase discriminator, the output end of the first detection sub-circuit is also connected with the first input end of the first control sub-circuit, and the first detection sub-circuit is used for outputting a first pulse signal to the first control sub-circuit when the first clock signal and the second clock signal are different, and outputting a second pulse signal to the first control sub-circuit when the first clock signal and the second clock signal are the same;

the second detection sub-circuit is used for being connected with the dead zone phase detector, the second detection sub-circuit is also connected with the first control sub-circuit, and is used for outputting a third pulse signal to the first control sub-circuit when a third clock signal and a fourth clock signal output by the dead zone phase detector are different, and outputting a fourth pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal are the same;

Optionally, the state control circuit is configured to:

Optionally, the state control circuit is also connected with the output end of the frequency divider; the state control circuit is also used for:

after the first control signal is received, when the number of pulses of the received frequency division clock signal reaches a first number, determining that the time length for receiving the first control signal reaches a first time length;

Resetting is carried out in response to a second control signal output by the state detection circuit, and a second indication signal is output to the frequency locking loop and the undersampled phase-locked loop respectively;

and in response to the first control signal output by the state detection circuit, counting the number of pulses of the divided clock signal, and outputting a first indication signal to the frequency locked loop and the undersampled phase locked loop when the number of pulses reaches a first number.

the clock end of the second counter is connected with the output end of the frequency divider, and the second counter is used for resetting in response to the reset signal, counting the pulse number of the frequency division clock signal in response to the enabling signal, and outputting a locking signal when the pulse number reaches the second number.

In yet another aspect, a chip is provided that includes the frequency locking circuit of the above aspect.

Optionally, the chip further comprises: a reference clock source and an integrated circuit;

the reference clock source is used for outputting a reference clock signal to a phase-locked loop in the frequency locking circuit;

the phase-locked loop is used for outputting a locking signal and a clock signal to the integrated circuit;

the integrated circuit is configured to operate based on a clock signal in response to the lock signal.

In yet another aspect, an electronic device is provided, including a chip as described in the above aspect.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

FIG. 1 is a schematic diagram of a chip according to an embodiment of the present application;

fig. 2 is a schematic diagram of a frequency locking circuit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application;

FIG. 4 is a waveform diagram of a reference clock signal, a frequency of the reference clock signal, a frequency of a divided clock signal, a first pulse signal, and a second pulse signal according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a frequency locking control circuit according to an embodiment of the present application;

Fig. 6 is a flowchart of a method for controlling frequency locking of a phase-locked loop according to an embodiment of the present application;

fig. 7 is a flowchart of another method for controlling frequency lock of a phase locked loop according to an embodiment of the present application;

fig. 8 is a flowchart of a frequency lock control method of a phase locked loop according to another embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

The phase-locked loop is an important clock source of an integrated circuit as a negative feedback control system for tuning a voltage-controlled oscillator to generate a target frequency using a control voltage generated by phase synchronization. The chip can normally start, operate, communicate and time the function such as time keeping clock. Also, the performance and stability of the clock determine the performance and stability of the chip.

In the fields of high-precision data acquisition, high-speed high-precision data communication, high-precision clock timing and the like, higher requirements are put on the precision and reliability of the clock. In some specific application scenarios, such as bluetooth connection scenarios, a phase-locked loop of conventional structure only includes a frequency-locked loop, but the phase-locked loop has not been able to meet the chip requirements for clock phase noise (phase noise), clock jitter (jitter), and stability.

In order to reduce phase noise of the phase-locked loop, the phase-locked loop provided by the embodiment of the application has natural advantages, and the phase-locked loop comprises a frequency locking loop and an undersampled phase-locked loop, and the phase-locked loop can also be called as undersampled phase-locked loop (SSPLL). Compared with the phase-locked loop with the traditional structure, the phase-locked loop can eliminate noise generated by a frequency divider (divider), and greatly inhibit noise generated by a phase frequency detector (phase frequency detector, PFD) and a Charge Pump (CP), so that clock jitter and phase noise of signals output by the phase-locked loop provided by the embodiment of the application are obviously better than those of the phase-locked loop with the traditional structure.

However, during the process of locking the undersampled phase-locked loop, the frequency locked loop and the undersampled phase-locked loop may switch back and forth, resulting in a phenomenon of output frequency oscillation. In the actual starting and locking process of the circuit, the frequency locking loop and the undersampled phase-locked loop face the problem of simultaneous working and timely and reasonable switching of working states, the two loops working simultaneously can lead the circuit to be incapable of locking the undersampled phase-locked loop in the starting process, and the failure to reasonably switch the working states can lead the two loops of the frequency locking loop and the undersampled phase-locked loop to be switched in error or back and forth, so that the phenomenon of oscillation of output frequency occurs. The above problems are solved by requiring an additional frequency locking control circuit to ensure that the normal locking can be realized by reasonably configuring the working states of the frequency locking loop and the undersampled phase locking loop after the circuit is started or out of lock.

The components of common telecommunications, computer and other digital electronic applications have very stringent timing requirements in order for the electronic device to perform very accurate operations. Therefore, a pll that can generate a stable frequency and synchronize an output clock signal with a reference clock signal is a very widely used circuit in electronic devices. The embodiment of the application provides electronic equipment which can be a personal computer, a tablet personal computer or wearable equipment and the like. The electronic device may comprise at least one chip, and referring to fig. 1, each chip 1000 may comprise a frequency locking circuit 100, and the frequency locking circuit 100 may comprise a frequency locking control circuit 10, and a phase locked loop 20 connected to the frequency locking control circuit 10.

Referring to fig. 1, the chip 1000 may further include a reference clock source 200 and an integrated circuit 300, the reference clock source 200 for outputting a reference clock signal Ref to a phase-locked loop 20 in the frequency locked circuit 100, the phase-locked loop 20 for outputting a locking signal locking and a clock signal to the integrated circuit 300, the integrated circuit 300 for operating based on the clock signal output by the phase-locked loop 20 in response to the locking signal.

Fig. 2 is a schematic diagram of a frequency locking circuit according to an embodiment of the present application, and as shown in fig. 2, a frequency locking control circuit 10 in the frequency locking circuit may include a state detection circuit 11 and a state control circuit 12, and a phase-locked loop 20 may include a frequency locking loop 21 and an undersampled phase-locked loop 22. The frequency locked loop 21 is used for coarse locking of the frequency and the undersampled phase locked loop 22 is used for fine locking on the basis of the frequency locked by the frequency locked loop 21.

It will be understood that the frequency-locked loop 21 performs coarse frequency locking, which refers to a process that the frequency-locked loop 21 continuously adjusts the clock signal output by the phase-locked loop 20 according to the reference clock signal Ref input by the reference clock source 200 until the output clock signal approaches the reference clock signal Ref. After the clock signal output by the phase-locked loop 20 approaches the reference clock signal Ref, the undersampled phase-locked loop 22 further adjusts the clock signal output by the phase-locked loop 20 based on the reference clock signal Ref on the basis of the clock signal output by the phase-locked loop 20 until the clock signal output by the phase-locked loop 20 substantially coincides with the reference clock signal Ref.

Referring to fig. 2, the state detection circuit 11 is connected to the state control circuit 12 and the frequency lock loop 21, respectively. The state detection circuit 11 detects the state of the frequency locked loop 21, and outputs a first control signal to the state control circuit 12 when detecting that the frequency locked loop 21 is in the locked state.

The state control circuit 12 is also connected to a frequency locked loop 21 and an undersampled phase locked loop 22, respectively. The state control circuit 12 is configured to output a first indication signal vc0 to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively, in response to the first control signal.

The frequency lock loop 21 is configured to receive the first indication signal vc0 output from the state control circuit 12, and to be in an off state based on the first dead zone width in response to the first indication signal vc0. The undersampled phase-locked loop 22 is configured to receive the first indication signal vc0 and frequency lock in response to the first indication signal vc0.

Wherein the first dead zone width may be a phase value. Referring to fig. 3, the first dead zone width is greater than the phase difference between the reference clock signal Ref, which is the clock signal received by the phase-locked loop 20, and the divided clock signal div, which is obtained by dividing the frequency of the target signal output by the phase-locked loop 20, which is output by the phase-locked loop 20 after the frequency-locked loop is in the locked state.

Alternatively, the reference clock signal Ref may be a clock signal received by the phase-locked loop 20 after the frequency-locked loop 21 is in a locked state. The phase difference between the reference clock signal Ref and the divided clock signal div refers to the difference between the phase of the reference clock signal Ref and the phase of the divided clock signal div.

The first dead zone width may be stored in the frequency locked loop 21 in advance, or may be determined by the frequency locked loop 21 based on a phase difference between the reference clock signal Ref and the divided clock signal div. Alternatively, the first dead zone width may be stored in the state detection circuit 11 in advance, or may be determined by the state detection circuit 11 based on the phase difference between the reference clock signal Ref and the divided clock signal div.

Referring to fig. 4, in the phase t1, in the locked state of the frequency locked loop 21, after that, the first dead zone width h is greater than the frequency difference between the reference clock signal Ref and the divided clock signal div, and correspondingly, the first dead zone width h is greater than the phase difference between the reference clock signal Ref and the divided clock signal div.

The first dead zone width is larger than the phase difference between the reference clock signal Ref and the divided clock signal div after the frequency locked loop 21 is in the locked state, that is, the first dead zone width is sufficiently large, and because the first dead zone width is sufficiently large, the dead zone phase detector in the frequency locked loop 21 can control the first charge pump in the frequency locked loop 21 to be in the off state based on the first dead zone width, so that the frequency locked loop 21 is in the off state. Thus, it is possible to effectively ensure that the frequency locked loop 21 remains in an off state during the frequency locking of the undersampled phase locked loop 22 and after the undersampled phase locked loop 22 is in a locked state. Therefore, the problem of switching back and forth of the frequency locking loop 21 and the undersampled phase locking loop 22 can be effectively avoided, and meanwhile, the clock precision of the chip is improved, and the performance and the reliability of the chip are further improved.

In the embodiment of the present application, the state detection circuit 11 may detect the state of the frequency locked loop 21 during the power-up process, or may periodically detect the state of the frequency locked loop 21 during the operation process.

In summary, the embodiments of the present application provide a frequency locking circuit, where when a frequency locking control circuit in the frequency locking circuit detects that a frequency locking loop is in a locked state, the frequency locking loop is controlled to be in an open state based on a first dead zone width. Because the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal after the frequency locking loop is in the locking state, the frequency locking loop can be effectively ensured to be always in the disconnection state in the process of frequency locking the undersampled phase locking loop and after the undersampled phase locking loop is in the locking state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

The state detection circuit 11 is further configured to output a second control signal to the state control circuit 12 when detecting that the frequency locked loop 21 is in the unlocked state. The state control circuit 12 is further configured to output a second indication signal vc1 to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively, in response to the second control signal.

The frequency lock loop 21 is configured to receive the second indication signal vc1 output from the state control circuit 12, and perform frequency locking based on the second dead zone width in response to the second indication signal vc 1. The undersampled phase-locked loop 22 is configured to receive the second indication signal vc1, and is in an off state in response to the second indication signal vc 1.

Wherein the second dead zone width is a phase value. The first dead zone width is greater than the second dead zone width. The second dead zone width is less than a preset phase, and the preset phase is greater than or equal to 0. By way of example, the second dead zone width may be 0.

Referring to fig. 2, the second indication signal vc1 may be a high level signal with respect to the first indication signal vc0, or the second indication signal vc1 may be a low level signal with respect to the first indication signal vc0, and the embodiment of the present application will be described by taking the case that the second indication signal vc1 is a low level signal with respect to the first indication signal vc0, for example, the vc1 may be 0, and the vc0 may be 1.

In the embodiment of the application, the undersampled phase-locked loop 22 is in a disconnected state in the process of frequency locking the frequency locking loop 21, so that the problem that the frequency locking loop 21 and the undersampled phase-locked loop 22 are switched in the process of frequency locking the frequency locking loop 21 can be effectively avoided, the phenomenon of output frequency oscillation is avoided, the reliability and stability of frequency locking the frequency locking loop 21 are improved, and meanwhile, the clock precision of a chip is improved, and the performance and reliability of the chip are further improved.

In the embodiment of the present application, the frequency locking control circuit 10 can flexibly adjust the loop for frequency locking in the phase-locked loop 20 according to the state of the frequency locking loop 21, so that the flexibility of controlling the frequency locking of the phase-locked loop 20 is improved. Furthermore, since the frequency locked loop 21 is in a different state, only one of the frequency locked loop 21 and the undersampled phase locked loop 22 is frequency locked, and the other loop is in an open state. Therefore, the problem of back and forth switching of the frequency locking loop 21 and the undersampled phase-locked loop 22 can be effectively avoided, the phenomenon of output frequency oscillation is avoided, the reliability of the phase-locked loop 20 for frequency locking is improved, and meanwhile, the clock precision of a chip is improved, and the performance and the reliability of the chip are further improved.

In an embodiment of the present application, the frequency locked loop 21 being in an unlocked state may include the frequency locked loop 21 being in an unlocked state, or the frequency locked loop 21 being in a frequency locked process state. The frequency locked loop 21 being in the unlocked state means that the phase locked loop 20 is in the unlocked state, and the frequency locked loop 21 and the undersampled phase locked loop 22 are operated simultaneously when the phase locked loop 20 is in the unlocked state. The process state in which the frequency locked loop 21 is in frequency locking refers to a process in which the frequency locked loop 21 performs coarse locking of the frequency.

It will be appreciated that during the frequency locking process of the frequency locking loop 21, or during the phase locked state of the phase locked loop 20, the difference between the phase of the clock signal (i.e. the target signal) output by the phase locked loop 20 and the phase of the reference clock signal Ref is greater than or equal to the difference threshold, i.e. the difference between the phase of the clock signal output by the phase locked loop 20 and the phase of the reference clock signal Ref is greater.

After the frequency locked loop 21 is in the locked state, the undersampled phase locked loop 22 performs frequency locking, and the phase difference between the phase of the clock signal output by the phase locked loop 20 and the phase of the reference clock signal Ref is smaller than the difference threshold, i.e. the phase difference between the phase of the clock signal output by the phase locked loop 20 and the phase of the reference clock signal Ref is smaller.

In the case where the undersampled pll 22 is in the locked state, if the reference clock signal Ref changes greatly and the difference between the phases of the reference clock signal Ref after the change and the clock signal output by the frequency locked loop 21 is large, the frequency locked loop 21 and the undersampled pll 22 operate simultaneously, thereby causing the pll 20 to be in the unlocked state. Alternatively, in the case where the undersampled phase locked loop 22 is in a locked state, when any device in the frequency locked loop 21 is abnormal, the phase locked loop 20 may be caused to enter an unlocked state.

Referring to fig. 3, the frequency locked loop 21 may include a frequency divider 210, and the frequency divider 210 is configured to divide a received clock signal and output a divided clock signal div obtained by dividing the frequency.

In the process of frequency locking the frequency locked loop 21 and the frequency locked loop 21 being in the locked state, the clock signal received by the frequency divider 210 is the clock signal output by the frequency locked loop 21, the clock signal is the target signal output by the phase locked loop 20, and the frequency division clock signal is obtained by frequency division of the clock signal output by the frequency locked loop 21 by the frequency divider 210. During the frequency locking of the undersampled pll 22 and the undersampled pll 22 being in a locked state, the clock signal received by the frequency divider 210 may be a clock signal output by the undersampled pll 22, the clock signal is also a target signal output by the pll 20, and the divided clock signal is obtained by dividing the clock signal output by the undersampled pll 22 by the frequency divider 210.

Referring to fig. 3, the frequency locked loop 21 may further include a dead zone phase detector 211, and the dead zone phase detector 211 may be a phase frequency detector. The input end of the dead zone phase detector 211 is used for being connected with the output end of the reference clock source 200, the input end of the dead zone phase detector 211 is also connected with the output end of the frequency divider 210 and the state control circuit 12, and the output end of the dead zone phase detector 211 is connected with the state detection circuit 11.

The reference clock source 200 is configured to output a reference clock signal Ref to the dead band phase detector 211, and the frequency divider 210 is configured to output a divided clock signal div to the dead band phase detector 211.

Referring to fig. 5, the dead zone phase detector 211 generates a first clock signal up_pre and a second clock signal dn_pre from a reference clock signal Ref and a frequency-divided clock signal div, and outputs the first clock signal up_pre and the second clock signal dn_pre to the state detection circuit 11. The third clock signal up is generated from the first clock signal up_pre and the dead zone width, the fourth clock signal dn is generated from the second clock signal dn_pre and the dead zone width, and the third clock signal up and the fourth clock signal dn are output to the state detection circuit 11.

Wherein the dead zone width may include a first dead zone width or a second dead zone width. The dead zone phase detector 211 may previously store the second dead zone width. The dead band phase detector 211 may calculate a first dead band width based on the reference clock signal Ref and the divided clock signal div. Or the first dead zone width may be stored in advance in the dead zone phase detector 211. The first dead zone width has a larger value, so that no matter how the reference clock signal Ref changes, the first dead zone width can be larger than the phase difference between the reference clock signal Ref and the frequency division clock signal div.

Alternatively, the state detection circuit 11 stores the first dead zone width and the second dead zone width in advance, and the state detection circuit 11 may receive the reference clock signal Ref and the divided clock signal div, determine the first dead zone width based on the phase difference between the reference clock signal Ref and the divided clock signal div, and transmit the first dead zone width to the dead zone phase detector 211 through the state control circuit 12.

The state detection circuit 11 is configured to determine that the frequency locked loop 21 is in an unlocked state when the received first clock signal up_pre and the received second clock signal dn_pre are different and the received third clock signal up and the received fourth clock signal dn are different. And when the received first clock signal up_pre and second clock signal dn_pre are the same and the third clock signal up and fourth clock signal dn are the same, it may be determined that the frequency locked loop 21 is in a locked state.

Wherein the first clock signal up_pre and the second clock signal dn_pre are the same, which means that the phases of the first clock signal up_pre and the second clock signal dn_pre are the same. The difference between the first clock signal up_pre and the second clock signal dn_pre means that the phase of the first clock signal up_pre and the phase of the second clock signal dn_pre are different. The same third clock signal up and fourth clock signal dn means that the phase of the third clock signal up and the phase of the fourth clock signal dn are the same, and the different third clock signal up and fourth clock signal dn means that the phase of the third clock signal up and the phase of the fourth clock signal dn are different.

In the embodiment of the present application, the dead zone phase detector 211 is configured to generate the first clock signal up_pre and the second clock signal dn_pre according to the phase difference between the reference clock signal Ref and the frequency division clock signal div. The larger the phase difference between the reference clock signal Ref and the divided clock signal div, the larger the phase difference between the first clock signal up_pre and the second clock signal dn_pre, the smaller the phase difference between the reference clock signal Ref and the divided clock signal div, and the closer the phase of the first clock signal up_pre and the second clock signal dn_pre.

When the first clock signal up_pre is a pulse signal, the dead zone phase detector 211 generates a third clock signal up according to the first clock signal up_pre and the dead zone width, which means subtracting the dead zone width from the pulse width of the first clock signal up_pre, thereby obtaining the third clock signal up. When the second clock signal dn_pre is a pulse signal, the dead zone phase detector 211 generates a fourth clock signal dn from the second clock signal dn_pre and the dead zone width, which means subtracting the dead zone width from the pulse width of the second clock signal dn_pre, thereby obtaining the fourth clock signal dn.

For example, when the pulse width of the first clock signal up_pre is 10 nanoseconds (ns) and the dead zone width is 4, the pulse width of the third clock signal up is 6ns.

Alternatively, the state control circuit 12 is configured to output a first indication signal vc0 to the dead zone phase detector 211 in response to the first control signal, where the first indication signal vc0 may carry the first dead zone width. And outputting a second indication signal vc1 to the dead zone phase detector 211 in response to the second control signal, wherein the second indication signal vc1 may carry a second dead zone width.

The dead zone phase detector 211 is configured to generate a third clock signal up according to the first clock signal up_pre and the first dead zone width h, and generate a fourth clock signal dn according to the second clock signal dn_pre and the first dead zone width h in response to the first indication signal vc 0. And generating a third clock signal up from the first clock signal up_pre and the second dead zone width and generating a fourth clock signal dn from the second clock signal dn_pre and the second dead zone width in response to the second indication signal vc 1.

The dead zone phase detector 211 is configured to process the first clock signal up_pre and the second clock signal dn_pre based on the first dead zone width in response to the first indication signal vc0, thereby placing the frequency locked loop 21 in an off state. And processes the first clock signal up_pre and the second clock signal dn_pre based on the second dead zone width in response to the second indication signal vc1, thereby frequency-locking the frequency locking loop 21.

Referring to fig. 3, the frequency locked loop 21 may further include a first charge pump 212. The output end of the dead zone phase detector 211 is connected to the input end of the first charge pump 212, the dead zone phase detector 211 is configured to output a third clock signal up and a fourth clock signal dn to the first charge pump 212, and the first charge pump 212 is configured to charge under the control of the third clock signal up and discharge under the control of the fourth clock signal dn.

Optionally, the third clock signal up is a pulse signal, and when the width of the pulse is greater than 0, the first charge pump 212 can be charged under the control of the third clock signal up. When the third clock signal up is a non-pulse signal (i.e., a continuous high level signal or a continuous low level signal), the first charge pump 212 stops charging.

The fourth clock signal dn is a pulse signal, and when the pulse width is greater than 0, the first charge pump 212 can discharge under the control of the fourth clock signal dn. When the fourth clock signal dn is a non-pulse signal, the first charge pump 212 stops discharging.

Assuming that the second dead zone width is 0 and the phase difference between the reference clock signal Ref and the divided clock signal div is large, when the first clock signal up_pre is a pulse signal and the second clock signal dn_pre is a non-pulse signal, the dead zone phase detector 211 processes the first clock signal up_pre based on the second dead zone width to generate a third clock signal up which is also a pulse signal and has the same width as the pulse width of the first clock signal up_pre. The fourth clock signal dn generated by processing the second clock signal dn_pre based on the second dead zone width is also a non-pulse signal.

When the first clock signal up_pre is a non-pulse signal and the second clock signal dn_pre is a pulse signal, the dead zone phase detector 211 processes the first clock signal up_pre based on the second dead zone width to generate a third clock signal up which is also a non-pulse signal, processes the second clock signal dn_pre based on the second dead zone width to generate a fourth clock signal dn which is also a pulse signal, and the width of the pulse signal is the same as the pulse width of the second clock signal dn_pre.

After the frequency locked loop 21 is in the locked state, the phase difference of the reference clock signal Ref and the divided clock signal div is small, and the phase difference is smaller than the first dead zone width. At this time, the first clock signal up_pre and the second clock signal dn_pre are both pulse signals, the pulse width of the pulse signals is narrower, and the pulse width is smaller than the first dead zone width. The dead zone phase detector 211 is therefore non-pulsed for both the third clock signal up generated by processing the first clock signal up_pre based on the first dead zone width and the fourth clock signal dn generated by processing the second clock signal dn_pre based on the first dead zone width. At this time, the third clock signal up does not control the first charge pump 212 to charge, and the fourth clock signal dn does not control the first charge pump 212 to discharge, so that the first charge pump 212 is in an off state, and the frequency locked loop 21 is in an off state.

It will be appreciated that after the phase locked loop 20 is powered up, the frequency locked loop 21 operates based on the second dead zone width, where the difference between the phase of the clock signal output by the frequency locked loop 21 and the phase of the reference clock signal Ref is large. That is, the phase difference between the reference clock signal Ref and the divided clock signal div is greater than or equal to the phase difference value, and accordingly, the first clock signal up_pre and the second clock signal dn_pre are different, and the third clock signal up and the fourth clock signal dn output by the dead zone phase detector 211 are also different. Therefore, the state detection circuit 11 can determine that the frequency locked loop 21 is in the unlocked state based on the received first clock signal up_pre, second clock signal dn_pre, third clock signal up, and fourth clock signal dn, and further can transmit the second indication signal vc1 through the state control circuit 12.

Then, during the frequency locking process of the frequency locking loop 21, the phase difference between the clock signal outputted by the frequency locking loop 21 and the phase difference between the reference clock signal Ref is still larger, and accordingly, the first clock signal up_pre and the second clock signal dn_pre are different, and the third clock signal up and the fourth clock signal dn outputted by the dead zone phase detector 211 are also different.

During the process that the frequency locked loop 21 is in the locked state, the phase difference between the phase of the clock signal output by the frequency locked loop 21 and the phase of the reference clock signal Ref is smaller, and at this time, the phase difference between the reference clock signal Ref and the frequency-divided clock signal div is smaller than the phase difference. Accordingly, the first clock signal up_pre and the second clock signal dn_pre are the same, and the third clock signal up and the fourth clock signal dn output from the dead zone phase detector 211 are also the same. Therefore, the state detection circuit 11 can determine that the frequency lock loop 21 is in the locked state based on the received first clock signal up_pre, second clock signal dn_pre, third clock signal up, and fourth clock signal dn, and further can transmit the first instruction signal vc0 through the state control circuit 12.

In addition, in the case where the undersampled pll 22 is in the locked state, the reference clock signal Ref is greatly changed, and the phase difference between the changed reference clock signal Ref and the divided clock signal div is greater than or equal to the phase difference value and greater than the first dead zone width. At this time, the dead zone phase detector 211 generates a first clock signal up_pre and a second clock signal dn_pre based on the changed reference clock signal Ref and the frequency-divided clock signal div, generates a third clock signal up based on the first clock signal up_pre and the first dead zone width h, and generates a fourth clock signal dn based on the second clock signal dn_pre and the first dead zone width h, so that the frequency locked loop 21 and the undersampled phase locked loop 22 are both in an operation state, and the phase locked loop 20 is in an unlocking state.

Since the phase difference between the changed reference clock signal Ref and the frequency-divided clock signal div is greater than or equal to the phase difference value and greater than the first dead zone width, the state detection circuit 11 can determine that the frequency locked loop 21 is in the unlocked state according to the received first clock signal up_pre, second clock signal dn_pre, third clock signal up and fourth clock signal dn. Further, the state detection circuit 11 can control the frequency locked loop 21 to be frequency locked based on the second dead zone width by the state control circuit 12 again, and control the undersampled phase locked loop 22 to be in the off state after the frequency locked loop 21 is in the locked state. Therefore, the condition that the frequency locking loop 21 and the undersampled phase-locked loop 22 work simultaneously under the condition that the reference clock signal is greatly changed is effectively avoided.

In the case where the undersampled phase locked loop 22 is in the locked state, when the dead zone phase detector 211 is abnormal, the output third clock signal up and the fourth clock signal dn may be different, and the phase locked loop 20 may enter the unlocked state at this time, so the state detection circuit 11 may determine that the frequency locked loop 21 is in the unlocked state according to the received third clock signal up and the second clock signal dn_pre.

Referring to fig. 4, in the process of frequency locking the frequency locking loop 21 in the t0 stage, the phase difference between the reference clock signal Ref and the divided clock signal div is greater than or equal to the phase difference value, and the phase difference value between the reference clock signal Ref and the divided clock signal div is greater. During the period t1, the phase difference between the reference clock signal Ref and the divided clock signal div is smaller than the phase difference value, i.e. the phase difference between the reference clock signal Ref and the divided clock signal div is smaller.

In the period t2, during the frequency locking of the undersampled phase locked loop 22 while the frequency locked loop 21 is in the off state, the phase difference between the reference clock signal Ref and the divided clock signal div is greater than or equal to the phase difference value in the initial stage of switching from the frequency locked loop 21 in the locked state to the off state, but the frequency locked loop 21 is still in the off state due to the greater width of the first dead zone. After this, the phase difference of the reference clock signal Ref and the divided clock signal div is smaller than the phase difference value.

At stage t3, the frequency locked loop 21 is in an off state and the undersampled phase locked loop 22 is in a locked state, where the phase difference between the reference clock signal Ref and the divided clock signal div is less than the phase difference value.

Referring to fig. 5, the state detection circuit 11 may include a first detection sub-circuit 110, a first control sub-circuit 111, and a second detection sub-circuit 112.

The input terminal of the first detection sub-circuit 110 is connected to the output terminal of the dead zone phase detector 211, and the output terminal of the first detection sub-circuit 110 is connected to the first input terminal of the first control sub-circuit 111. The first detection sub-circuit 110 is configured to output a first pulse signal to the first control sub-circuit 111 when the first clock signal up_pre and the second clock signal dn_pre are different, and to output a second pulse signal to the first control sub-circuit 111 when the first clock signal up_pre and the second clock signal dn_pre are the same. The first detection sub-circuit 110 may store the first pulse signal and the second pulse signal in advance, where the pulse width of the first pulse signal is greater than 0, and the pulse width of the second pulse signal is 0.

An input of the second detection subcircuit 112 is connected to an output of the dead zone phase detector 211, and an output of the second detection subcircuit 112 is connected to a second input of the first control subcircuit 111. The second detection sub-circuit 112 is configured to output a third pulse signal to the first control sub-circuit 111 when the third clock signal up and the fourth clock signal dn are different, and to output a fourth pulse signal to the first control sub-circuit 111 when the third clock signal up and the fourth clock signal dn are the same.

The second detection sub-circuit 112 may store the third pulse signal and the fourth pulse signal in advance, where the pulse width of the third pulse signal is greater than 0, and the pulse width of the fourth pulse signal is 0. The third pulse signal may be the same as or different from the first pulse signal, and the fourth pulse signal may be the same as or different from the second pulse signal.

The control terminal of the first control sub-circuit 111 is connected to the input terminal of the state control circuit 12, and the first control sub-circuit 111 is configured to output a second control signal to the state control circuit 12 when receiving the first pulse signal and the third pulse signal, and output the first control signal to the state control circuit 12 when receiving the second pulse signal and the fourth pulse signal after the state control circuit 12 outputs the second indication signal vc1 to the undersampled phase-locked loop 22.

For example, referring to fig. 4, the first pulse signal and the second pulse signal may be represented by pd1, and the third pulse signal and the fourth pulse signal may be represented by pd 2.

In the process of frequency locking the frequency locking loop 21 in the t0 stage, since the first clock signal up_pre and the second clock signal dn_pre are different, the pulse width of the first pulse signal output by the first detection sub-circuit 110 is greater than 0. Since the third clock signal up and the fourth clock signal dn are different, the pulse width of the third pulse signal output from the second detection sub-circuit 112 is greater than 0.

In the stage t1, the frequency lock loop 21 is in the locked state, and the first clock signal up_pre and the second clock signal dn_pre are the same, so that the pulse width of the second pulse signal output from the first detection sub-circuit 110 is 0. Since the third clock signal up and the fourth clock signal dn are the same, the pulse width of the fourth pulse signal output from the second detection sub-circuit 112 is 0.

In the period t2, during the frequency locking of the undersampled phase locked loop 22 while the frequency locked loop 21 is in the off state, the first clock signal up_pre and the second clock signal dn_pre are different from each other in the initial period of switching from the locked state of the frequency locked loop 21 to the off state, and thus the second pulse signal output from the first detection sub-circuit 110 includes a plurality of pulses. Although the first clock signal up_pre and the second clock signal dn_pre are different, the phase difference between the reference clock signal Ref and the divided clock signal div is still smaller than the first dead zone width, so that the third clock signal up and the fourth clock signal dn output by the dead zone phase detector 211 are still the same, and the fourth pulse signal output by the second detection sub-circuit 112 is a non-pulse signal. After that, the second pulse signal output from the first detection sub-circuit 110 is a non-pulse signal, and the fourth pulse signal output from the second detection sub-circuit 112 is a non-pulse signal.

At the stage t3, the frequency locked loop 21 is in an off state, the undersampled phase locked loop 22 is in a locked state, and the phase difference between the reference clock signal Ref and the divided clock signal div is smaller than the phase difference value, so that the second pulse signal output by the first detection sub-circuit 110 is a non-pulse signal, and the fourth pulse signal output by the second detection sub-circuit 112 is a non-pulse signal.

In the embodiment of the present application, the state control circuit 12 is configured to, when the duration of receiving the first control signal reaches the first duration, output the first indication signal vc0 to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively, in response to the first control signal. By transmitting the first indication signal vc0 after it is determined that the time period for receiving the first control signal reaches the first time period, stability of the frequency locking loop 21 in the locked state can be ensured, and reliability of the output clock signal can be ensured.

The state control circuit 12 is configured to output a lock signal when the duration of outputting the first indication signal vc0 to the undersampled phase-locked loop 22 reaches the second duration. By outputting the lock signal after the time period of outputting the first indication signal vc0 reaches the second time period, the stability of frequency locking of the undersampled phase-locked loop 22 is ensured, and further, the reliability of the clock signal output by the phase-locked loop 20 is ensured.

Optionally, the state control circuit 12 is further configured to be coupled to an integrated circuit, the state control circuit 12 being configured to output a lock signal to the integrated circuit, thereby enabling the integrated circuit to operate based on the clock signal output by the phase locked loop 20 in response to the lock signal.

In the embodiment of the present application, the output end of the frequency divider 210 is further connected to the state control circuit 12, and the frequency divider 210 is further configured to output the divided clock signal div obtained by frequency division to the state control circuit 12.

The state control circuit 12 is further configured to determine that, after receiving the first control signal, the number of pulses of the received divided clock signal div reaches the first number, and that the duration of receiving the first control signal reaches the first duration. After outputting the first indication signal vc0 to the undersampled phase-locked loop 22, the number of pulses of the received divided clock signal div reaches the second number, and it may be determined that the duration of outputting the first indication signal vc0 to the undersampled phase-locked loop 22 reaches the second duration. The first number and the second number may be stored in the state control circuit 12 in advance.

Referring to fig. 5, the state control circuit 12 may include a first counter 121, and the first counter 121 may be a controller having a counting function or may have only a counting function. The input rn1 of the first counter 121 is connected to the output of the state detection circuit 11, and the output of the first counter 121 is connected to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively. The clock terminal ck1 of the first counter 121 is connected to an output terminal of the frequency divider 210, and the frequency divider 210 is configured to output the divided clock signal div obtained by frequency division to the first counter 121. The state detection circuit 11 is configured to output a second control signal and a first control signal to the first counter 121.

The first counter 121 is configured to:

after receiving the second control signal output from the state detection circuit 11, the reset is performed in response to the second control signal, and the second indication signal vc1 is output to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively. Wherein, the resetting of the first counter 121 refers to that the first counter 121 clears the data stored therein to 0.

After receiving the first control signal output from the state detection circuit 11, the number of pulses of the received divided clock signal div is counted in response to the first control signal, and when the number of pulses reaches the first number, a first indication signal vc0 may be output to the frequency locked loop 21 and the undersampled phase locked loop 22. Wherein the first number is stored in the first counter 121 in advance.

Referring to fig. 3, the undersampled phase locked loop 22 may include an undersampled phase detector 220 and a second charge pump 221.

Wherein the output of the first counter 121 is connected to the input of the undersampled phase detector 220, the input of the second charge pump 221 and the input of the dead zone phase detector 211, respectively. The first counter 121 is configured to count the number of pulses of the received divided clock signal div in response to the first control signal after receiving the first control signal output by the state detection circuit 11, and may output a first indication signal vc0 to the undersampled phase detector 220, the second charge pump 221, and the dead zone phase detector 211 when the number of pulses reaches the first number. Upon receiving the second control signal output from the state detection circuit 11, a second indication signal vc1 is output to the undersampled phase detector 220, the second charge pump 221, and the dead zone phase detector 211.

In the embodiment of the present application, the first control sub-circuit 111 may store the first dead zone width, or the first control sub-circuit 111 may be further connected to the input end of the phase-locked loop 20, receive the reference clock signal Ref, further determine the first dead zone width based on the reference clock signal Ref and the divided clock signal div, and send the first dead zone width to the dead zone phase detector 211 through the first counter 121. The first indication signal vc0 may carry a first dead zone width.

The undersampled phase detector 220 is configured to be in an off state in response to the second indication signal vc1, thereby causing the undersampled phase locked loop 22 to be in an off state, and to be in an on state in response to the first indication signal vc 0. The undersampled phase detector 220 is deactivated in response to the second indication signal vc1 and is thus in an off state.

The input terminal of the second charge pump 221 is further connected to the output terminal of the undersampled phase detector 220, and the second charge pump 221 is configured to receive the second indication signal vc1 and the first indication signal vc0, and in response to the second indication signal vc1 being in an off state, thereby causing the undersampled phase-locked loop 22 to be in an off state, and in response to the first indication signal vc0 to be in an active state. Alternatively, the second charge pump 221 is stopped in response to the second indication signal vc1, thereby being in an off state.

Referring to fig. 3, the frequency locked loop 21 may further include a loop filter 213 and a voltage controlled oscillator 214. The voltage controlled oscillator 214 is a loop voltage controlled oscillator.

The output end of the first charge pump 212 is connected to the input end of the loop filter 213, the output end of the loop filter 213 is connected to the input end of the voltage-controlled oscillator 214, the first charge pump 212 is configured to output a current pulse signal to the loop filter 213, and the loop filter 213 is configured to generate a voltage-controlled voltage to the voltage-controlled oscillator 214 according to the current pulse signal.

The output end of the voltage-controlled oscillator 214 is connected to the input end of the frequency divider 210, and the voltage-controlled oscillator 214 is configured to adjust the frequency of the clock signal output to the frequency divider 210 based on the received voltage-controlled voltage, so that the frequency of the output clock signal is close to the frequency of the input reference clock signal Ref until the frequency difference disappears, thereby implementing phase locking.

Referring to fig. 3, the undersampled phase locked loop 22 may further include a loop filter 213 and a voltage controlled oscillator 214, i.e., the undersampled phase locked loop 22 and the frequency locked loop 21 share the loop filter 213 and the voltage controlled oscillator 214.

The input of the undersampled phase detector 220 is further connected to the reference clock source 200 and to the output of the voltage controlled oscillator 214, and the output of the undersampled phase detector 220 is connected to the input of the second charge pump 221. The undersampled phase detector 220 is configured to generate a first reference signal and a second reference signal from the reference clock signal Ref and the clock signal output by the voltage controlled oscillator 214, and output the first reference signal and the second reference signal to the second charge pump 221.

The second charge pump 221 is configured to charge and discharge the loop filter 213 under control of the first reference signal and the second reference signal, thereby controlling the magnitude of the voltage-controlled voltage output from the loop filter 213 to the voltage-controlled oscillator 214. The voltage controlled oscillator 214 is also used to adjust the frequency of the clock signal output to the undersampled phase detector 220 based on the received voltage controlled voltage.

It will be appreciated that the second charge pump 221 and the undersampled phase detector 220 are both in an off state after receiving the second indication signal vc1, and thus the undersampled phase locked loop 22 is in an off state. Both the second charge pump 221 and the undersampled phase detector 220 are in operation upon receipt of the first indication signal vc0, so that the undersampled phase locked loop 22 is frequency locked.

Referring to fig. 5, the state control circuit 12 may further include a second control sub-circuit 122 and a second counter 123.

The second counter 123 may be a controller having a counting function or may have only a counting function. The output terminal of the first counter 121 is connected to the input terminal of the second control sub-circuit 122, and the first counter 121 is further configured to output a second indication signal vc1 to the second control sub-circuit 122 in response to the second control signal, and may output the first indication signal vc0 to the second control sub-circuit 122 when the number of pulses reaches the first number.

The output terminal of the second control sub-circuit 122 is further connected to the input terminal rn2 of the second counter 123, and the second control sub-circuit 122 is configured to output a reset signal to the second counter 123 in response to the second indication signal vc1, and output an enable signal to the second counter 123 in response to the first indication signal vc 0.

The clock terminal ck2 of the second counter 123 is further connected to the output terminal of the frequency divider 210, the second counter 123 is configured to reset in response to the reset signal, count the number of pulses of the divided clock signal div output by the frequency divider 210 in response to the enable signal, and output the locking signal locking when the number of pulses reaches the second number.

Optionally, the resetting of the second counter 123 refers to the second counter 123 clearing the stored data of 0. The second counter 123 is configured to be connected to the integrated circuit 300, and the second counter 123 is configured to output a locking signal locking to the integrated circuit 300.

In summary, the embodiments of the present application provide a frequency locking circuit, where when a frequency locking control circuit in the frequency locking circuit detects that a frequency locking loop is in a locked state, the frequency locking loop is controlled to be in an open state based on a first dead zone width. The first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal after the frequency locking loop is in the locking state, so that the frequency locking loop can be effectively ensured to be always in the disconnection state in the frequency locking process of the undersampled phase locking loop and after the undersampled phase locking loop is in the locking state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

An embodiment of the present application provides a frequency lock control circuit 10, referring to fig. 2, the frequency lock control circuit 10 includes: a state detection circuit 11, and a state control circuit 12 connected to the state detection circuit 11.

The state detection circuit 11 is further configured to be connected to the frequency locked loop 21 of the phase locked loop 20, and the state detection circuit 11 is configured to output a first control signal to the state control circuit 12 when detecting that the frequency locked loop 21 is in a locked state.

The state control circuit 12 is further configured to be connected to the frequency locked loop 21 and the undersampled phase locked loop 22 of the phase locked loop 20, and the state control circuit 12 is configured to output a first indication signal vc0 to the undersampled phase locked loop 22 and the frequency locked loop 21, respectively, in response to the first control signal, the first indication signal vc0 being configured to indicate that the frequency locked loop 21 is in an off state based on the first dead zone width, and to indicate that the undersampled phase locked loop 22 performs frequency locking.

The first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, the reference clock signal is a signal received by the phase-locked loop, the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in a locked state.

In summary, the embodiments of the present application provide a frequency lock control circuit of a phase locked loop, which controls a frequency lock loop to be in an off state based on a first dead zone width when detecting that the frequency lock loop is in a locked state. Because the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal, the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampled phase locking loop switching back and forth can be effectively avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

The state detection circuit 11 is configured to output a second control signal to the state control circuit 12 when detecting that the frequency locked loop 21 is in the unlocked state.

The state control circuit 12 is further configured to output a second indication signal vc1 to the undersampled phase-locked loop 22 and the frequency-locked loop 21, respectively, in response to the second control signal, the second indication signal vc1 being configured to indicate that the undersampled phase-locked loop 22 is in an off state and to indicate that the frequency-locked loop 21 performs frequency locking based on the second dead zone width. The second dead zone width is less than the preset phase.

Optionally, the state control circuit 12 is configured to:

when the time period of receiving the first control signal reaches the first time period, a first indication signal vc0 is output to the undersampled phase-locked loop 22 and the frequency-locked loop 21, respectively, in response to the first control signal.

When the duration of outputting the first indication signal vc0 to the undersampled phase locked loop 22 reaches the second duration, a lock signal is output.

Optionally, the state control circuit 12 is further configured to be connected to an output terminal of the frequency divider 210 of the frequency locked loop 21; the state control circuit 12 is further configured to:

after receiving the first control signal, the number of pulses of the divided clock signal div output by the received frequency divider 210 reaches the first number, and it is determined that the duration of receiving the first control signal reaches the first duration.

After outputting the first indication signal vc0 to the undersampled phase-locked loop 22, the number of pulses of the received divided clock signal div reaches a second number, and it is determined that the duration of outputting the first indication signal vc0 to the undersampled phase-locked loop 22 reaches a second duration.

Optionally, the state control circuit 12 includes: the output end of the first counter 121 is used for being connected with the frequency locking loop 21 and the undersampled phase-locked loop 22, and the input end of the first counter 121 is connected with the state detection circuit 11; a first counter 121 for:

Reset in response to the second control signal output from the state detection circuit 11, and output a second indication signal vc1 to the frequency locked loop 21 and the undersampled phase locked loop 22, respectively.

In response to the first control signal output from the state detection circuit 11, the number of pulses of the divided clock signal div is counted, and when the number of pulses reaches the first number, a first indication signal vc0 is output to the frequency locked loop 21 and the undersampled phase locked loop 22.

Optionally, the state control circuit 12 further includes: a second control sub-circuit 122 and a second counter 123;

the output end of the first counter 121 is connected to the input end of the second control sub-circuit 122, and the first counter 121 is further configured to output a second indication signal vc1 to the second control sub-circuit 122 in response to the second control signal, and output a first indication signal vc0 to the second control sub-circuit 122 when the number of pulses reaches the first number.

The output terminal of the second control sub-circuit 122 is connected to the input terminal rn2 of the second counter 123, and the second control sub-circuit 122 is configured to output a reset signal to the second counter 123 in response to the second indication signal vc1, and output an enable signal to the second counter 123 in response to the first indication signal vc0.

The clock terminal ck2 of the second counter 123 is used for being connected to the frequency divider 210, the second counter 123 is used for resetting in response to a reset signal, counting the number of pulses of the divided clock signal div in response to an enable signal, and outputting a lock signal when the number of pulses reaches the second number.

Optionally, the state detection circuit 11 is configured to:

when the first clock signal up_pre and the second clock signal dn_pre output from the dead zone phase detector 211 of the frequency locked loop 21 are the same and the third clock signal up and the fourth clock signal dn output from the dead zone phase detector 211 of the frequency locked loop 21 are the same, it is determined that the frequency locked loop 21 is in a locked state.

When the first clock signal up_pre and the second clock signal dn_pre are different and the third clock signal up and the fourth clock signal dn are different, it is determined that the frequency locked loop 21 is in an unlocked state.

Wherein the first clock signal up_pre is generated by the dead zone phase detector 211 from the reference clock signal Ref and the divided clock signal div, the third clock signal up is generated by the dead zone phase detector 211 from the first clock signal up_pre and the dead zone width, and the fourth clock signal dn is generated by the dead zone phase detector 211 from the second clock signal dn_pre and the dead zone width, the dead zone width including the first dead zone width or the second dead zone width.

Optionally, the state detection circuit 11 includes: a first detection sub-circuit 110, a first control sub-circuit 111 and a second detection sub-circuit 112.

The first detection sub-circuit 110 is configured to be connected to the dead zone phase detector 211 of the frequency locked loop 21, where the first detection sub-circuit 110 is further connected to the first control sub-circuit 111, and the first detection sub-circuit 110 is configured to output a first pulse signal to the first control sub-circuit 111 when the first clock signal up_pre and the second clock signal dn_pre output by the dead zone phase detector 211 are different, and output a second pulse signal to the first control sub-circuit 111 when the first clock signal up_pre and the second clock signal dn_pre are the same.

The second detection sub-circuit 112 is configured to be connected to the dead zone phase detector 211, the second detection sub-circuit 112 is further connected to the first control sub-circuit 111, and the second detection sub-circuit 112 is configured to output a third pulse signal to the first control sub-circuit 111 when the third clock signal up and the fourth clock signal dn output from the dead zone phase detector 211 are different, and to output a fourth pulse signal to the first control sub-circuit 111 when the third clock signal up and the fourth clock signal dn are the same.

The first control sub-circuit 111 is further connected to the state control circuit 12, and the first control sub-circuit 111 is configured to output a second control signal to the state control circuit 12 when receiving the first pulse signal and the third pulse signal, and output the first control signal to the state control circuit 12 when receiving the second pulse signal and the fourth pulse signal after the state control circuit 12 outputs the second indication signal vc1 to the undersampled phase-locked loop 22.

In summary, the embodiments of the present application provide a frequency lock control circuit of a phase locked loop, which controls a frequency lock loop to be in an off state based on a first dead zone width when detecting that the frequency lock loop is in a locked state. By setting the first dead zone width to be larger than the phase difference between the reference clock signal and the frequency division clock signal, the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

An embodiment of the present application provides a phase locked loop 20, referring to fig. 2, the phase locked loop 20 includes: a frequency locked loop 21 and an undersampled phase locked loop 22 connected to the frequency locked loop 21.

The frequency lock loop 21 is further configured to be connected to the state control circuit 12 in the frequency lock control circuit 10, and the frequency lock loop 21 is configured to receive the first indication signal vc0 output from the state control circuit 12, and is in an off state based on the first dead zone width in response to the first indication signal vc 0.

The first dead zone width is larger than the reference clock signal, the reference clock signal is a signal received by the phase-locked loop, the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in a locking state.

The undersampled phase-locked loop 22 is further arranged to be coupled to the state control circuit 12, the undersampled phase-locked loop 22 being arranged to receive the first indication signal vc0 and to frequency lock in response to the first indication signal vc 0.

In summary, the embodiments of the present application provide a phase locked loop, in which a frequency locked loop can be in an off state based on a first dead zone width in response to a first indication signal output by a frequency locking control circuit, and an undersampled phase locked loop in the phase locked loop performs frequency locking in response to the first indication signal. Because the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal, the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampling phase-locked loop switching back and forth can be effectively avoided, the phenomenon of output frequency oscillation is avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

The frequency locking loop 21 is further configured to receive a second indication signal vc1 output from the state control circuit 12, and perform frequency locking based on a second dead zone width in response to the second indication signal vc1, where the second dead zone width is greater than the preset phase.

The undersampled phase-locked loop 22 is further configured to receive a second indication signal vc1, and to be in an off state in response to the second indication signal vc 1.

Referring to fig. 3, the frequency locking loop 21 includes: the frequency divider 210, the output end of the frequency divider 210 is used for connecting with the state control circuit 12; frequency divider 210 for:

the received clock signal is divided, and the divided clock signal div obtained by the frequency division is output to the state control circuit 12, so that the state control circuit 12 receives the first control signal, the number of pulses of the received divided clock signal div reaches a first number, the time length of the received first control signal reaches a first time length, after the first indication signal vc0 is output to the undersampled phase-locked loop 22, the number of pulses of the received divided clock signal div reaches a second number, and the time length of the received first indication signal vc0 is output to the undersampled phase-locked loop 22 reaches a second time length.

Referring to fig. 3, the frequency locked loop 21 further includes: a dead zone phase detector 211;

The input end of the dead zone phase detector 211 is connected to the output end of the frequency divider 210, the output end of the dead zone phase detector 211 is connected to the state detection circuit 11, and the dead zone phase detector 211 is used for:

the first clock signal up_pre and the second clock signal dn_pre are generated from the reference clock signal Ref and the frequency-divided clock signal div output from the frequency divider 210, and the first clock signal up_pre and the second clock signal dn_pre are output to the state detection circuit 11.

The third clock signal up is generated from the first clock signal up_pre and the dead zone width, the fourth clock signal dn is generated from the second clock signal dn_pre and the dead zone width, and the third clock signal up and the fourth clock signal dn are output to the state detection circuit 11.

Fig. 6 is a flowchart of a method for controlling frequency lock of a phase-locked loop according to an embodiment of the present application, which can be applied to the frequency lock control circuit 10 of a phase-locked loop shown in the above embodiment, as shown in fig. 6, and includes:

step 601, determining a state of a frequency locked loop in the phase locked loop.

Step 602, when the frequency locking loop is in a locked state, outputting a first indication signal to an undersampled phase-locked loop and a frequency locking loop in the phase-locked loop respectively.

The first indication signal is used for indicating that the frequency locking loop is in an open state based on the first dead zone width and indicating that the undersampled phase locking loop performs frequency locking.

The first dead zone width is larger than the reference clock signal, the reference clock signal is a signal received by the phase-locked loop, the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal output by the phase-locked loop is output after the frequency locking loop is in a locked state.

In summary, the embodiment of the application provides a method for controlling frequency locking of a phase-locked loop, in which the first dead zone width is greater than the phase difference between a reference clock signal and a frequency-division clock signal, so that the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of an undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state, thereby effectively avoiding the problem that the frequency locking loop and the undersampled phase-locked loop are switched back and forth, and improving the clock precision of a chip, and further improving the performance and reliability of the chip.

Fig. 7 is a flowchart of a method for controlling frequency locking of a phase-locked loop according to an embodiment of the present application, which can be applied to the phase-locked loop 20 shown in the foregoing embodiment, as shown in fig. 7, and includes:

in step 701, the frequency locking loop receives a first indication signal output by the frequency locking control circuit, and is in an off state based on a first dead zone width in response to the first indication signal.

Step 702, the undersampled phase locked loop receives a first indication signal, and frequency locks in response to the first indication signal.

In summary, the embodiments of the present application provide a method for controlling frequency locking of a phase locked loop, in which a frequency locked loop in the phase locked loop can be in an off state based on a first dead zone width in response to a first indication signal output by a frequency locking control circuit, and the undersampled phase locked loop performs frequency locking in response to the first indication signal. Because the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal, the frequency locking loop can be effectively ensured to be always in an off state in the process of locking the frequency of the undersampled phase-locked loop and after the undersampled phase-locked loop is in a locked state. Therefore, the problem of frequency locking loop and undersampled phase locking loop switching back and forth can be effectively avoided, and meanwhile, the clock precision of the chip is improved, and the performance and reliability of the chip are further improved.

Fig. 8 is a flowchart of another method for controlling frequency lock of a phase-locked loop according to an embodiment of the present application, which may be applied to the frequency lock control circuit 10 and the phase-locked loop 20 of the phase-locked loop shown in the above embodiment, as shown in fig. 8, the method may include:

step 801, the frequency locking control circuit determines the state of the frequency locking loop.

Optionally, when the first clock signal and the second clock signal output by the dead zone phase detector in the frequency locked loop are the same, the third clock signal and the fourth clock signal output by the dead zone phase detector in the frequency locked loop are the same, and the undersampled phase locked loop is in the off state, it may be determined that the frequency locked loop is in the locked state.

When the first clock signal and the second clock signal are different and the third clock signal and the fourth clock signal are different, it is determined that the frequency locked loop is in an unlocked state.

Wherein the first clock signal is generated from the reference clock signal and the divided clock signal output by the frequency divider in the frequency locked loop by the dead zone phase detector and the second clock signal is generated from the first clock signal and the dead zone width by the dead zone phase detector and the fourth clock signal is generated from the second clock signal and the dead zone width by the dead zone phase detector.

Step 802, when the frequency locking control circuit determines that the frequency locking loop is in a locking state, the frequency locking control circuit outputs a first indication signal to the undersampled phase-locked loop and the frequency locking loop.

The first indication signal is used for indicating that the frequency locking loop is in an open state based on a first dead zone width and indicating that the undersampled phase locking loop performs frequency locking, wherein the first dead zone width is larger than the second dead zone width. The second dead zone width is smaller than the preset phase, the first dead zone width is larger than the phase difference between the reference clock signal and the frequency division clock signal, the reference clock signal is a signal received by the phase-locked loop, the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in a locked state.

Optionally, after the frequency locked loop is in the locked state, the number of pulses of the frequency division clock signal output by the frequency divider in the received frequency locked loop reaches a first number, and it is determined that the duration of the frequency locked loop in the locked state reaches a first duration.

Step 803, the frequency locked loop is in an off state based on the first dead band width in response to the first indication signal.

Step 804, the undersampled phase locked loop frequency locks in response to the first indication signal.

And step 805, when the frequency locking control circuit determines that the frequency locking loop is in an unlocked state, respectively outputting second indication signals to the undersampled phase locking loop and the frequency locking loop in the phase locking loop.

The second indication signal is used for indicating that the undersampled phase-locked loop is in an open state and indicating that the frequency locking loop performs frequency locking based on a second dead zone width.

Step 806, frequency locking the loop in response to the second indication signal based on the second dead band width.

Step 807, the undersampled phase locked loop is in an off state in response to the second indication signal.

Step 808, outputting a locking signal when detecting that the duration of outputting the first indication signal to the undersampled phase locked loop reaches the second duration.

Optionally, after the first indication signal is output to the undersampled phase-locked loop, when the number of pulses of the frequency division clock signal output by the frequency divider in the frequency locked loop reaches the second number, it is determined that the duration of outputting the first indication signal to the undersampled phase-locked loop reaches the second duration.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first," "second," and the like, as used in embodiments of the present application, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the application that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present application, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.

In the present application, unless explicitly stated or limited otherwise in the examples, the terms "connected," "connected," and "fixed" as used in the examples should be interpreted broadly, e.g., the connection may be a fixed connection, may be a removable connection, or may be integral, and it may be understood that the connection may also be a mechanical connection, an electrical connection, or the like; of course, it may be directly connected, or indirectly connected through an intermediate medium, or may be in communication with each other, or in interaction with each other. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to specific embodiments.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A frequency lock control circuit of a phase locked loop, the phase locked loop comprising: a frequency locked loop and an undersampled phase locked loop, the frequency locked control circuit comprising: a state detection circuit and a state control circuit;

the state control circuit is used for responding to the first control signal and outputting a first indication signal to the undersampled phase-locked loop and the frequency locking loop respectively, wherein the first indication signal is used for indicating that the frequency locking loop is in a disconnection state based on a first dead zone width and indicating the undersampled phase-locked loop to perform frequency locking;

the first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, and the reference clock signal is a clock signal received by the phase-locked loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in the locking state.

2. The phase-locked loop frequency lock control circuit of claim 1, wherein the state detection circuit is further configured to output a second control signal to the state control circuit upon detecting that the frequency lock loop is in an unlocked state;

the state control circuit is further configured to respond to the second control signal, and output second indication signals to the undersampled phase-locked loop and the frequency locked loop, where the second indication signals are used to indicate that the undersampled phase-locked loop is in the disconnected state, and indicate that the frequency locked loop performs frequency locking based on a second dead zone width, and the second dead zone width is smaller than a preset phase.

3. The phase-locked loop frequency lock control circuit of claim 2, wherein the state detection circuit is configured to:

when a first clock signal and a second clock signal output by a dead zone phase discriminator of the frequency locking loop are the same and a third clock signal and a fourth clock signal output by the dead zone phase discriminator are the same, determining that the frequency locking loop is in the locking state;

determining that the frequency locked loop is in the unlocked state when the first clock signal and the second clock signal are different and the third clock signal and the fourth clock signal are different;

Wherein the first clock signal and the second clock signal are generated by the dead zone phase detector from the reference clock signal and the divided clock signal, the third clock signal is generated by the dead zone phase detector from the first clock signal and a dead zone width, and the fourth clock signal is generated by the dead zone phase detector from the second clock signal and the dead zone width, the dead zone width including the first dead zone width or the second dead zone width.

4. A frequency lock control circuit of a phase locked loop according to claim 3, wherein the state detection circuit comprises: the first detection sub-circuit, the first control sub-circuit and the second detection sub-circuit;

the output end of the first detection sub-circuit is connected with the first input end of the first control sub-circuit, the input end of the first detection sub-circuit is used for being connected with the output end of the dead zone phase discriminator, when the first clock signal and the second clock signal output by the dead zone phase discriminator are different, a first pulse signal is output to the first control sub-circuit, and when the first clock signal and the second clock signal are the same, a second pulse signal is output to the first control sub-circuit;

The second detection sub-circuit is connected with the first control sub-circuit, and is used for being connected with the dead zone phase detector, outputting a third pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal output by the dead zone phase detector are different, and outputting a fourth pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal are the same;

the first control sub-circuit is further connected with the state control circuit, and is used for outputting the first control signal to the state control circuit when the second pulse signal and the fourth pulse signal are received, and outputting the second control signal to the state control circuit when the first pulse signal and the third pulse signal are received.

5. A frequency lock control circuit of a phase locked loop according to any one of claims 1 to 4, wherein the state control circuit is configured to:

when the time length of receiving the first control signal reaches a first time length, responding to the first control signal, and respectively outputting the first indication signals to the undersampled phase-locked loop and the frequency locked loop;

And outputting a locking signal when the time period for outputting the first indication signal to the undersampled phase-locked loop reaches a second time period.

6. The phase-locked loop frequency lock control circuit of claim 5, wherein the state control circuit is further configured to connect to an output of a frequency divider of the frequency lock loop, and determine that a duration of receiving the first control signal reaches the first duration when a number of pulses of the received divided clock signal reaches a first number after receiving the first control signal;

and after the first indication signal is output to the undersampled phase-locked loop, when the number of pulses of the received frequency division clock signal reaches a second number, determining that the duration of outputting the first indication signal to the undersampled phase-locked loop reaches the second duration.

7. The phase-locked loop frequency lock control circuit of claim 6, wherein the state control circuit comprises: the output end of the first counter is used for being connected with the frequency locking loop and the undersampled phase-locked loop, and the input end of the first counter is connected with the output end of the state detection circuit; the first counter is used for:

Counting the number of pulses of the divided clock signal in response to a first control signal output by the state detection circuit, and outputting the first indication signal to the frequency locked loop and the undersampled phase locked loop when the number of pulses reaches the first number;

8. The phase-locked loop frequency lock control circuit of claim 7, wherein the state control circuit further comprises: a second control sub-circuit and a second counter;

the output end of the first counter is connected with the input end of the second control sub-circuit, and the first counter is further used for responding to the second control signal to output the second indication signal to the second control sub-circuit, and outputting the first indication signal to the second control sub-circuit when the number of pulses reaches the first number;

the output end of the second control sub-circuit is connected with the input end of the second counter, and the second control sub-circuit is used for responding to the second indication signal, outputting a reset signal to the second counter and responding to the first indication signal, and outputting an enabling signal to the second counter;

The clock end of the second counter is used for being connected with the output end of the frequency divider, responding to the reset signal for resetting, responding to the enabling signal for counting the pulse number of the frequency division clock signal, and outputting the locking signal when the pulse number reaches the second number.

9. A phase locked loop, the phase locked loop comprising: a frequency locked loop and an undersampled phase locked loop;

the undersampled phase-locked loop is used for receiving a first indication signal output by the state control circuit and performing frequency locking in response to the first indication signal;

10. The phase locked loop of claim 9 wherein the frequency locked loop is further configured to receive a second indication signal output by the state control circuit and to frequency lock based on a second dead band width in response to the second indication signal, the second dead band width being less than a preset phase;

the undersampled phase-locked loop is further configured to receive the second indication signal and to be in the off state in response to the second indication signal.

11. The phase locked loop of claim 10, wherein the frequency locked loop further comprises: a dead zone phase detector;

the input end of the dead zone phase discriminator is connected with the output end of the frequency divider, the output end of the dead zone phase discriminator is used for being connected with the input end of the state detection circuit, a first clock signal and a second clock signal are generated according to a reference clock signal and the frequency division clock signal, and the first clock signal and the second clock signal are output to the state detection circuit;

generating a third clock signal from the first clock signal and a dead zone width, generating a fourth clock signal from the second clock signal and the dead zone width, and outputting the third clock signal and the fourth clock signal to the state detection circuit, the dead zone width including the first dead zone width or the second dead zone width.

12. A phase locked loop as claimed in any one of claims 9 to 11, wherein said frequency locked loop comprises: a frequency divider;

the frequency divider is used for dividing the frequency of the signal output by the phase-locked loop and outputting a frequency division clock signal obtained by frequency division to the state control circuit.

13. A frequency lock control method of a phase locked loop, applied to a frequency lock control circuit, the method comprising:

determining a state of a frequency locking loop in the phase-locked loop;

outputting a first indication signal to an undersampled phase-locked loop in the phase-locked loop and the frequency-locked loop when the frequency-locked loop is in a locked state;

the first indication signal is used for indicating that the frequency locking loop is in an off state based on a first dead zone width, and indicating that the undersampled phase locking loop performs frequency locking, the first dead zone width is larger than a phase difference between a reference clock signal and a frequency division clock signal, and the reference clock signal is a clock signal received by the phase locking loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in the locking state.

14. The method of controlling frequency lock of a phase locked loop of claim 13, further comprising:

15. The method of claim 14, wherein determining the state of the frequency locked loop in the phase locked loop comprises:

when a first clock signal and a second clock signal output by a dead zone phase detector in the frequency locking loop are the same and a third clock signal and a fourth clock signal output by the dead zone phase detector are the same, determining that the frequency locking loop is in the locking state;

16. The method according to any one of claims 13 to 15, wherein outputting a first instruction signal to the undersampled phase locked loop and the frequency locked loop when detecting that the frequency locked loop is in a locked state, comprises:

and outputting the first indication signal to the undersampled phase-locked loop and the frequency locking loop when the time length of the frequency locking loop in the locking state reaches a first time length.

17. The method of controlling frequency lock of a phase locked loop of claim 16, further comprising:

after the frequency locking loop is in the locking state, when the number of pulses of the received frequency division clock signal reaches a first number, determining that the duration of the frequency locking loop in the locking state reaches the first duration;

And outputting a locking signal when detecting that the time period for outputting the first indication signal to the undersampled phase-locked loop reaches a second time period.

18. The method of controlling frequency lock of a phase locked loop of claim 17, further comprising:

and after the first indication signal is output to the undersampled phase-locked loop, when the number of pulses of the frequency division clock signal received reaches a second number, determining that the duration of outputting the first indication signal to the undersampled phase-locked loop reaches the second duration.

19. The frequency locking control method of the phase-locked loop is characterized by being applied to the phase-locked loop, wherein the phase-locked loop comprises a frequency locking loop and an undersampled phase-locked loop; the method comprises the following steps:

the undersampled phase-locked loop receives the first indication signal and performs frequency locking in response to the first indication signal;

20. The method of controlling frequency lock of a phase locked loop of claim 19, further comprising:

the frequency locking loop receives a second indication signal output by the frequency locking control circuit and responds to the second indication signal to perform frequency locking based on a second dead zone width, and the second dead zone width is smaller than a preset phase;

the undersampled phase locked loop receives the second indication signal and is in the off state in response to the second indication signal.

21. The method of controlling frequency lock of a phase locked loop of claim 20, wherein the frequency locked loop further comprises: a dead zone phase detector; the method further comprises the steps of:

the dead zone phase detector generates a first clock signal and a second clock signal from a reference clock signal and the divided clock signal, generates a third clock signal from the first clock signal and a dead zone width, generates a fourth clock signal from the second clock signal and the dead zone width, and outputs the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to the frequency lock control circuit, the dead zone width including the first dead zone width or the second dead zone width.

22. A method of controlling frequency locking of a phase locked loop according to any one of claims 19 to 21, wherein the frequency locking loop comprises: a frequency divider; the method further comprises the steps of:

the frequency divider divides the frequency of the signal output by the phase-locked loop and outputs a frequency division clock signal obtained by frequency division to the frequency locking control circuit.

23. A frequency locking circuit, the frequency locking circuit comprising: a frequency lock control circuit and a phase locked loop, the frequency lock control circuit comprising: a state detection circuit and a state control circuit, the phase locked loop comprising: a frequency locked loop and an undersampled phase locked loop;

the frequency locking loop is used for responding to the first indication signal and is in an off state based on a first dead zone width, the first dead zone width is larger than the phase difference between a reference clock signal and a frequency division clock signal, and the reference clock signal is a clock signal received by the phase-locked loop; the frequency division clock signal is obtained by frequency division of a target signal output by the phase-locked loop, and the target signal is output by the phase-locked loop after the frequency locking loop is in the locking state;

24. The frequency locked loop of claim 23 wherein the state detection circuit is further configured to output a second control signal to the state control circuit upon detecting that the frequency locked loop is in an unlocked state;

the state control circuit is further used for responding to the second control signal and outputting second indication signals to the undersampled phase-locked loop and the frequency locked loop respectively;

the frequency locking loop is used for responding to the second indication signal and performing frequency locking based on a second dead zone width, and the second dead zone width is smaller than a preset phase;

the undersampled phase locked loop is configured to be in the off state in response to the second indication signal.

25. The frequency locking circuit of claim 24 wherein the frequency locking loop further comprises: and the dead zone phase discriminator is respectively connected with the frequency divider and the state detection circuit and is used for:

Generating a third clock signal from the first clock signal and a dead zone width, generating a fourth clock signal from the second clock signal and the dead zone width, and outputting the third clock signal and the fourth clock signal to the state detection circuit, the dead zone width including the first dead zone width or the second dead zone width;

the state detection circuit is configured to determine that the frequency locked loop is in the locked state when the first clock signal and the second clock signal are the same and the third clock signal and the fourth clock signal are the same; when the first clock signal and the second clock signal are different and the third clock signal and the fourth clock signal are different, determining that the frequency locked loop is in the unlocked state.

26. The frequency locking circuit of claim 25 wherein the state detection circuit comprises: the first detection sub-circuit, the first control sub-circuit and the second detection sub-circuit;

The second detection sub-circuit is used for being connected with the dead zone phase discriminator, the second detection sub-circuit is also connected with the first control sub-circuit, and is used for outputting a third pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal output by the dead zone phase discriminator are different, and outputting a fourth pulse signal to the first control sub-circuit when the third clock signal and the fourth clock signal are the same;

27. A frequency locking circuit according to any one of claims 23 to 26 wherein the state control circuit is configured to:

28. The frequency locking circuit of claim 27 wherein the state control circuit is further coupled to an output of the frequency divider; the state control circuit is further configured to:

after the first control signal is received, when the number of pulses of the received frequency division clock signal reaches a first number, determining that the time length for receiving the first control signal reaches the first time length;

29. The frequency locking circuit of claim 28 wherein the state control circuit comprises: the output end of the first counter is connected with the frequency locking loop and the undersampled phase-locked loop, and the input end of the first counter is connected with the output end of the state detection circuit; the first counter is used for:

Resetting in response to a second control signal output by the state detection circuit, and outputting a second indication signal to the frequency locked loop and the undersampled phase locked loop respectively;

and responding to a first control signal output by the state detection circuit, counting the number of pulses of the frequency division clock signal, and outputting the first indication signal to the frequency locking loop and the undersampled phase locking loop when the number of pulses reaches the first number.

30. The frequency locking circuit of claim 29 wherein the state control circuit further comprises: a second control sub-circuit and a second counter;

The clock end of the second counter is connected with the output end of the frequency divider, the second counter is used for responding to the reset signal to reset, responding to the enabling signal to count the pulse number of the frequency division clock signal, and outputting the locking signal when the pulse number reaches the second number.

31. A chip comprising the frequency locking circuit of any one of claims 23 to 30.

32. The chip of claim 31, wherein the chip further comprises: a reference clock source and an integrated circuit;

the integrated circuit is configured to operate based on the clock signal in response to the lock signal.

33. An electronic device comprising the chip of claim 31 or 32.