CN103297042A - Charge pump phase-locked loop circuit capable of performing locking fast - Google Patents
Charge pump phase-locked loop circuit capable of performing locking fast Download PDFInfo
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Abstract
The invention discloses a charge pump phase-locked loop circuit capable of performing locking fast. The charge pump phase-locked loop circuit comprises a crystal oscillator, a phase frequency detector, a digital auxiliary phase discrminator, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, wherein the digital auxiliary phase discrminator, the charge pump and the loop filter circuit form a phase-locked loop fast locking circuit. The crystal oscillator generates reference signals and outputs the reference signals to the phase frequency detector which compares phase difference of the input reference signals and feedback signals of a frequency divider and outputs voltage value of the phase difference to the charge pump, the charge pump converts the voltage value of the phase difference into current and outputs the current to the loop filter, the loop filter filters high-frequency components of the current to generate direct current controlled voltage, and the direct current control voltage adjusts frequency of output signals of a voltage-controlled oscillator, the output signals of the voltage-controlled oscillator serve as output signals of the charge pump phase-locked loop, frequency division is performed on the output signals of the charge pump phase-locked loop by the frequency divider, and the output signals are then fed back to the input end of the phase frequency detector.
Description
Technical field
The present invention relates to a kind of phase-locked loop circuit, more particularly, relate to a kind of size according to phase difference change charge pump charging and discharging currents, self adaptation adjustment loop bandwidth, the charge pump phase locking loop circuit of realization quick lock in.
Background technology
Phase-locked loop circuit is a kind of feedback circuit, and in the process of work, when output voltage and input voltage keep the phase difference value fixed, when output signal frequency equated with the frequency of input signal, the phase place of output voltage and input voltage was lockable.
Phase-locked loop is widely used in field of wireless communication, along with the Modern wireless communication technical development is rapid, the high mobility of Modern Communication System and the demand of high data transmission rate, the main application of phase-locked loop has: phase-locked loop becomes the critical function module of various communication systems as phase-locked loop frequency synthesizer, for communication system provides local oscillation signal and various clock signal.
Now modal is charge pump phase lock loop, comprises following module: crystal oscillator, phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider.Under the phase-locked loop lock-out state, the phase difference of the feedback signal of frequency divider and the input reference signal of crystal oscillator is zero or is a constant value, then the voltage controlled oscillator output signal frequency equal frequency input signal N doubly.If phase difference between the two changes, phase frequency detector will detect this variation, by charge pump the variation of phase difference is converted into the magnitude of current, again by loop filter filtering alternating current component wherein, produce direct-current control voltage at last and regulate the output frequency of voltage controlled oscillator, reduce the phase difference of output signal of frequency divider and input reference signal gradually, and finally reach the state of locking.
The research of phase-locked loop can launch from many aspects, output frequency is variable, locking time, shorter and shorter phase-locked loop structures was used more flexible, generally export a plurality of alternative clocks by changing feedback frequency dividing ration N, but when N changes, a plurality of parameters of whole loop are (as loop bandwidth, phase margin, damping factor etc.) all can change, so we must dynamically change other parameters of loop accordingly (as changing charge pump current Icp, linear gain Kvco of VCO etc.) guarantee that the characteristic of loop and stability remain unchanged substantially, as changing charge pump charging and discharging currents size adjustment loop locking time, but loop stability is constant.
When the phase difference of output signal of frequency divider and input reference signal hour, the output of phase frequency detector is also less, the charging and discharging currents of charge pump can't reflect phase difference, thereby formed the phase demodulation dead band, the general method that adopts is to add time-delay to eliminate the phase demodulation dead band in the phase frequency detector feedback circuit.Charge pump is made up of the current source of two belt switches, and deciding according to the output of phase frequency detector is that electric charge is pumped in the loop filter, still electric charge is pumped from loop.The electric charge pump performance directly affects the characteristic of phase-locked loop, can be by improving its structure, reduce the charging and discharging currents mismatch, electric charge is shared and non-ideal effects such as electric charge injection.Loop filter is actually a low pass filter, by electric capacity, resistance, the linear circuit that also may be made up of inductance or amplifier.The radio-frequency component that its filtering phase frequency detector of one side produces and output ripple, the inhibition zone external noise takes out the output frequency that flip-flop (namely controlling voltage) removes to control voltage controlled oscillator; It also is that important parameter of phase-locked loop is regulated device on the other hand, has determined the important loop parameters such as spuious inhibition, phase noise, loop stability, locking time of phase-locked loop.
Mainly determined by the time-delay that is input to output by each module of the charging and discharging currents size of the resistance capacitance parameter of loop filter, charge pump and phase-locked loop the locking time of phase-locked loop.The response speed of phase frequency detector, voltage controlled oscillator and the frequency divider of general phase-locked loop is than very fast, so the lock speed of phase-locked loop is mainly determined by the resistance capacitance parameter of charge pump current and loop filter.
Along with the development of the modern communications demand to high mobility and high data transmission rate, more and more harsher to the locking time of phase-locked loop, can effectively reduce locking time by the resistance capacitance parameter that changes charge pump current and loop filter.
Summary of the invention
(1) technical problem that will solve
At the problems referred to above, but the object of the present invention is to provide a kind of charge pump phase locking loop circuit of quick lock in, under the prerequisite that does not change loop stability, to improve the lock speed of phase-locked loop effectively.
(2) technical scheme
For achieving the above object, but the invention provides a kind of charge pump phase locking loop circuit of quick lock in, this charge pump phase locking loop circuit comprises crystal oscillator, phase frequency detector, the auxiliary phase discriminator of numeral, charge pump, loop filter, voltage controlled oscillator and frequency divider, phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider are in turn connected to form loop, crystal oscillator all is connected in phase frequency detector with the auxiliary phase discriminator of numeral, the auxiliary phase discriminator of numeral, charge pump and loop filter circuit constitute the phase locked loop fast lock circuit, wherein: crystal oscillator produces input reference signal and exports to phase frequency detector, phase frequency detector is the phase difference between the feedback signal of this input reference signal and frequency divider relatively, and the magnitude of voltage of phase difference output is given charge pump; Charge pump is converted into the magnitude of current with the magnitude of voltage of this phase difference, exports to loop filter; The high fdrequency component of this magnitude of current of loop filter filtering produces direct-current control voltage, and this direct-current control voltage is regulated the frequency of voltage controlled oscillator output signal; The output signal of voltage controlled oscillator is as the output signal of this charge pump phase lock loop; The output signal of charge pump phase lock loop further feeds back to the input of phase frequency detector behind the frequency divider frequency division.
In the such scheme, the described auxiliary phase discriminator of numeral that is connected in phase frequency detector is used for the size of control charge pump charging and discharging currents, if the magnitude of voltage of the phase difference of phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, then increase the charging and discharging currents of charge pump, thereby increase loop bandwidth, reduce the resistance value of loop filter, realize quick lock in, loop stability is constant; When the loop approach locking, reduce charge pump charging and discharging currents size, adjust bandwidth to default optimal value, guarantee the optimization of systematic function.
In the such scheme, the magnitude of voltage of the phase difference of described phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, the charge pump charging and discharging currents increases to original four times, the resistance of loop filter is reduced to original half, be reduced to original half in locking time, loop phase nargin is constant simultaneously, and loop stability is constant.
In the such scheme, the resistance sizes that the auxiliary phase discriminator of described numeral is regulated charge pump charging and discharging currents size and loop filter, the output signals UP B of phase frequency detector and DN through one or and delay circuit after produce signal Di, delay time T in the auxiliary phase discriminator of numeral
2Be the critical value of the phase error that is detected, by τ relatively
2With the size of phase error, the size that determines whether to open control switch control charge pump charging and discharging currents and loop filter resistance is finished quick lock in.
In the such scheme, add time-delay τ on the reset circuit of described phase frequency detector
1Eliminate the phase demodulation dead band.Described τ
1Be 6ns.
In the such scheme, described phase frequency detector adopts edge detection unit to replace d type flip flop in the phase discriminator, and the EDC structure prevents from the leakage of electric current from increasing the lock acquisition scope by the break-make of control Mk switch, eliminates the dead band, increases its stability.
In the such scheme, described charge pump adopts current mirror and operational amplifier, reduces current mismatch, avoids electric charge to share.
In the such scheme, described charge pump changes two output voltage U P of phase frequency detector and DN and becomes electric current output, and electric current discharges and recharges loop filter, because the integral action of loop filter changes into an analog voltage signal to current signal; Charge pump is constant according to the size of current of the phase difference output of phase frequency detector, owing to discharge and recharge asynchronism(-nization), so the duty ratio of electric current is variable, charge pump is equivalent to the current source of a belt switch.
In the such scheme, described charge pump adopts cascodes, and cascodes can improve output resistance, and the sensitiveness that electric current changes output voltage reduces, and the electric current that discharges and recharges is equal substantially, the charging and discharging currents coupling.
In the such scheme, the improvement structure of described charge pump adds unity gain amplifier, no matter be that MN1 and MP1 turn-off (this moment MN2 and MP2 conducting simultaneously) simultaneously, still MN2 and MP2 turn-off (this moment MN1 and MP2 conducting simultaneously) simultaneously, Vtune equals Vx, therefore there is not the variation of voltage in Vtune, has avoided electric charge to share.
In the such scheme, add one road electric current from described charge pump, by the auxiliary phase discriminator control switch of numeral, determine the size of loop bandwidth to determine quick lock in.
In the such scheme, described loop filter adopts three rank passive low ventilating filter filtering, the ripple on the filtering control signal.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following characteristics and good result:
But 1, the charge pump phase locking loop circuit of this quick lock in provided by the invention, the auxiliary phase discriminator of numeral is introduced the quick lock in module, phase difference and digital assisting in the phase discriminator by relatively phase frequency detector output are delayed time, increase charge pump current and reduce loop filter resistance, effectively reduced the locking time of phase-locked loop, stability is constant simultaneously.
But 2, the charge pump phase locking loop circuit of this quick lock in provided by the invention, phase frequency detector adopt the edge detection unit design, and phase frequency detector replaces phase discriminator and increases the lock acquisition scope, adds time delay module, eliminates the dead band, increases its stability.
But 3, the charge pump phase locking loop circuit of this quick lock in provided by the invention, charge pump adds unity gain amplifier, improves charge pump circuit, reduces current mismatch, avoids electric charge to share.
But 4, the charge pump phase locking loop circuit of this quick lock in provided by the invention, crystal oscillator produces input reference signal, phase frequency detector compares the phase difference of the feedback signal of input reference signal and frequency divider, export corresponding magnitude of voltage, charge pump is converted into the magnitude of current with phase difference, by loop filter filtering high fdrequency component wherein, produce the output frequency that direct-current control voltage is regulated voltage controlled oscillator, reduce the phase difference of output signal of frequency divider and input reference signal gradually.
But 5, the charge pump phase locking loop circuit of this quick lock in provided by the invention is when the phase error of the phase frequency detector output delay time T greater than the auxiliary phase discriminator of numeral
2The time, open the electric current that control switch S increases charge pump, thereby increase loop bandwidth, reduce the resistance value of loop filter, realize quick lock in, loop stability is constant; When the loop approach locking, adjust bandwidth to default optimal value, guaranteed the optimization of systematic function.
Description of drawings
But Fig. 1 is the structural representation of the charge pump phase locking loop circuit of quick lock in provided by the invention;
Fig. 2 is the structural representation of phase frequency detector provided by the invention;
Fig. 3 is the structural representation of edge detection unit circuit provided by the invention;
Fig. 4 is the structural representation of the auxiliary phase discriminator of numeral provided by the invention;
Fig. 5 is the schematic diagram of the auxiliary phase discriminator sequential of numeral provided by the invention;
Fig. 6 is the structural representation of charge pump circuit provided by the invention;
Fig. 7 is the structural representation of loop filter circuit provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
But Fig. 1 is the structural representation of the charge pump phase locking loop circuit of quick lock in provided by the invention, this charge pump phase locking loop circuit comprises crystal oscillator (OSC), phase frequency detector (PFD), the auxiliary phase discriminator (DAPD) of numeral, charge pump (CP), loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider (DIV), phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider are in turn connected to form loop, crystal oscillator all is connected in phase frequency detector with the auxiliary phase discriminator of numeral, the auxiliary phase discriminator of numeral, charge pump and loop filter circuit constitute the phase locked loop fast lock circuit.
Wherein, crystal oscillator produces input reference signal and also exports to phase frequency detector, and phase frequency detector is the phase difference between the feedback signal of this input reference signal and frequency divider relatively, and the magnitude of voltage of phase difference output is to charge pump; Charge pump is converted into the magnitude of current with the magnitude of voltage of this phase difference, exports to loop filter; The high fdrequency component of this magnitude of current of loop filter filtering produces direct-current control voltage, and this direct-current control voltage is regulated the frequency of voltage controlled oscillator output signal; The output signal of voltage controlled oscillator is as the output signal of this charge pump phase lock loop; The output signal of charge pump phase lock loop further feeds back to the input of phase frequency detector behind the frequency divider frequency division.
The described auxiliary phase discriminator of numeral that is connected in phase frequency detector is used for the size of control charge pump charging and discharging currents, if the magnitude of voltage of the phase difference of phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, then increase the charging and discharging currents of charge pump, thereby increase loop bandwidth, reduce the resistance value of loop filter, realize quick lock in, loop stability is constant; When the loop approach locking, reduce charge pump charging and discharging currents size, adjust bandwidth to default optimal value, guarantee the optimization of systematic function.The magnitude of voltage of the phase difference of phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, the charge pump charging and discharging currents increases to original four times, the resistance of loop filter is reduced to original half, be reduced to original half in locking time, loop phase nargin is constant simultaneously, and loop stability is constant.The auxiliary phase discriminator of numeral is regulated the resistance sizes of charge pump charging and discharging currents size and loop filter, the output signals UP B of phase frequency detector and DN through one or and a delay circuit after produce signal Di, digitally assist delay time T in the phase discriminator
2Be the critical value of the phase error that is detected, by τ relatively
2With the size of phase error, the size that determines whether to open control switch control charge pump charging and discharging currents and loop filter resistance is finished quick lock in.
State and add time-delay τ on the reset circuit of phase frequency detector (PFD)
1Eliminate the phase demodulation dead band, yet, τ
1Too smallly can not better eliminate phase demodulation dead band, τ
1Excessively can not realize stablizing phase demodulation, get τ as requested
1Be 6ns.Described PFD replaces d type flip flop in the traditional structure with EDC (edge detection unit), and the EDC structure prevents the leakage of electric current by the break-make of control Mk switch, thereby more stable than traditional phase frequency detector.
Charge pump adopts current mirror and operational amplifier, reduces current mismatch, avoids electric charge to share.Charge pump changes two output voltage U P of phase frequency detector and DN and becomes electric current output, and electric current discharges and recharges loop filter, because the integral action of loop filter changes into an analog voltage signal to current signal; Charge pump is constant according to the size of current of the phase difference output of phase frequency detector, owing to discharge and recharge asynchronism(-nization), so the duty ratio of electric current is variable, charge pump is equivalent to the current source of a belt switch.Charge pump adopts cascodes, and cascodes can improve output resistance, and the sensitiveness that electric current changes output voltage reduces, and the electric current that discharges and recharges is equal substantially, the charging and discharging currents coupling.The improvement structure of charge pump adds unity gain amplifier, no matter be that MN1 and MP1 turn-off (this moment MN2 and MP2 conducting simultaneously) simultaneously, still MN2 and MP2 turn-off (MN1 and MP2 while conducting this moment) simultaneously, and Vtune equals Vx, therefore there is not the variation of voltage in Vtune, has avoided electric charge to share.Add one road electric current from charge pump, by the auxiliary phase discriminator control switch of numeral, determine the size of loop bandwidth to determine quick lock in.
Loop filter adopts three rank passive low ventilating filter filtering, the ripple on the filtering control signal.
Fig. 2 shows phase frequency detector of the present invention (PFD) structural representation, adds time-delay τ on the reset circuit of PFD
1Eliminate the phase demodulation dead band.By increasing the single τ of time-delay
1, make UPB and DN that the sufficiently long reset delay time be arranged, can satisfy rising and the fall time of signal itself, also can satisfy the charge pump opening and closing time simultaneously is the requirement that loop filter discharges and recharges.τ
1Too smallly can not better eliminate phase demodulation dead band, τ
1Cross the electric current that conference makes charge pump export loop filter under the current mismatch situation and formed the ripple that influences VCO control voltage, increased the shake of phase-locked loop, also influence the maximum operation frequency of phase frequency detector simultaneously, can not realize stablizing phase demodulation, get τ
1For 6ns is appropriate value.
Fig. 3 shows edge detection unit of the present invention (EDC) electrical block diagram, and the break-make of control Mk prevents the leakage of electric current, thereby more stable than traditional phase frequency detector.When EDC detects the input rising edge, output signal (out) becomes high level, and then transistor Mk is turned off, and when detecting reset signal, then out becomes low level again.When being output as low level, Mk conducting, Mk conducting have prevented that weak current from leaking from X.The output signals UP B of PFD and DN are as the input signal of digital DAPD (the auxiliary phase discriminator of numeral) module.DAPD determines whether to enter the quick lock in pattern by comparing two paths of signals.
Fig. 4 and Fig. 5 formula have respectively gone out the auxiliary phase discriminator structure of numeral of the present invention and sequential schematic diagram, by comparing τ
2With the difference of UPB and DN, determine the mode of operation of circuit.If difference is greater than τ
2, then remain on fast locking time; If difference is less than τ
2, then forward the narrow bandwidth time to.Fig. 5 (a) and Fig. 5 (b) have shown that respectively phase difference is greater than τ
2With less than τ
2Situation.Sample lags behind Di when signal, shows that the phase difference of UPB and DN is greater than τ
2, the auxiliary phase discriminator output of numeral Mode is low level, opens the control switch in charge pump and the loop filter, enters the wide bandwidth pattern; When the phase-locked loop approach locking, the phase place of UPB and DN is very approaching, and phase difference is less than τ
2, output signal Mode becomes high level, enters the narrow bandwidth pattern.
Fig. 6 shows charge pump circuit structural representation of the present invention, and the current source IC of charge pump provides biasing by a reference current, adopts structure control Mn1, the Mn2 of current mirror and the length-width ratio of Mn8 to obtain corresponding charging and discharging currents value.Switch MOS pipe Mn4/Mn5, Mp4/Mp5 are that complementary switch is realized discharging and recharging of charge pump about adopting.Up and Upb, Dn and Dnb be inversion signal each other respectively, because current source is in conducting state all the time up and down, namely or be Up and all conductings of Dnb, or is Upb and all conductings of Dn.The current potential of n4 and n5 is stable all the time in the make and break process of switch, is beneficial to eliminate the non-ideal effects that electric charge is shared.Charging current Iup and discharging current Idn respectively by Mn1 and Mn2 from the Mn0 mirror image, wherein Mn1 has identical breadth length ratio with Mn2, is ignoring raceway groove mudulation effect and geometric figure mismatch ideally, the drain current of Mn1 and Mn2 equates.Equally, Mp1 has identical breadth length ratio with Mp2, i.e. drain current of Xiang Denging.So Iup equals Idn.But in the circuit of actual design, always there is the raceway groove mudulation effect in MOS transistor, and Mn1 is different with the source-drain voltage of Mn2, Mp1 and Mp2, will cause the mismatch of Iup and Idn.Tend to occur not the matching of charging and discharging currents of charge pump like this, when just charge pump charging and discharging currents switch was opened simultaneously, net current was non-vanishing.This net current can make the control voltage of VCO in fixed value of instantaneous increase (or minimizing) of each phase bit comparison, makes VCO control voltage produce periodic ripple.Loop will reduce the current mismatch of charge pump in order to reduce the ripple that VCO control voltage produces.The design has introduced operational amplifier A 1, A2, has reduced the mismatch of electric current I up and Idn.For the voltage that n1 is ordered equals the voltage that n3 is ordered, introduced operational amplifier A 1.In order to make the n2 point voltage equal the n1 point voltage, introduced operational amplifier A 2.N1, n2 and the n3 voltage of ordering all equates like this.Add Mp3 and Mn3 simultaneously, wherein Mp3 has the size identical with Mp4, Mp5, and the size of Mn3 is identical with Mn4, Mn5.So, the source-drain voltage of Mp1 and Mp2, Mn1 and Mn2 equates respectively, has so just reduced the influence of raceway groove mudulation effect, obtains Iup=Idn.Unity gain amplifier A2 has avoided situation about fluctuating widely at n2 place voltage when making Mn4 and Mp4 conducting simultaneously (this moment, Mn5 and Mp5 turn-offed simultaneously), therefore the current potential of n4 and n5 is stable in the switch state process, has also just avoided electric charge to share effect.The introducing of operational amplifier A 1, A2 helps to reduce the mismatch of Iup and Idn.Add control switch Mp6, Mp7, Mp8, Mn6, Mn7, Mn8 increases the charge pump charging and discharging currents, has increased loop bandwidth and has entered the quick lock in pattern.When the phase frequency detector module detects differing of output signal and reference signal when big, DAPD module output Mode is low level,
Be high level, namely the grid voltage of Mp6 and Mn6 is high, Mp6 and Mn6 conducting, and it is original four times that the charge pump charging and discharging currents increases, and increases loop bandwidth and realizes quick lock in.When approach locking, Mp6 and Mn6 turn-off, and self adaptation is regulated and reduced bandwidth, and loop stability reduces spuious.So this structure can reduce that charging and discharging currents mismatch, electric charge are shared and non-ideal effects such as electric charge injection.
Fig. 7 shows loop filter circuit structural representation of the present invention, and employing third order PLL path filter reduces the high frequency modulated noise and with reference to spuious, dotted portion has reduced the sheet inner area for the sheet external structure.When the auxiliary phase discriminator control switch of numeral is opened M
0And M
1Conducting simultaneously, charge pump current increase and are original 4 times, and loop filter resistance becomes originally 1/2 simultaneously, guarantees PLL loop bandwidth F
cWith zero frequency F
zIncrease twice simultaneously, it is constant to keep phase margin, and the stability of a system is constant, and is reduced to original 1/2 locking time.
The above further describes purpose of the present invention, technical scheme and beneficial effect, the present invention can realize that quick lock in does not change the stability of loop, design can be used for described phase-locked loop fields such as communication based on SMIC 40nmCMOS technology.Within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. but the charge pump phase locking loop circuit of a quick lock in, it is characterized in that, this charge pump phase locking loop circuit comprises crystal oscillator, phase frequency detector, the auxiliary phase discriminator of numeral, charge pump, loop filter, voltage controlled oscillator and frequency divider, phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider are in turn connected to form loop, crystal oscillator all is connected in phase frequency detector with the auxiliary phase discriminator of numeral, the auxiliary phase discriminator of numeral, charge pump and loop filter circuit constitute the phase locked loop fast lock circuit, wherein:
Crystal oscillator produces input reference signal and also exports to phase frequency detector, and phase frequency detector is the phase difference between the feedback signal of this input reference signal and frequency divider relatively, and the magnitude of voltage of phase difference output is to charge pump; Charge pump is converted into the magnitude of current with the magnitude of voltage of this phase difference, exports to loop filter; The high fdrequency component of this magnitude of current of loop filter filtering produces direct-current control voltage, and this direct-current control voltage is regulated the frequency of voltage controlled oscillator output signal; The output signal of voltage controlled oscillator is as the output signal of this charge pump phase lock loop; The output signal of charge pump phase lock loop further feeds back to the input of phase frequency detector behind the frequency divider frequency division.
2. but the charge pump phase locking loop circuit of quick lock in according to claim 1, it is characterized in that, the described auxiliary phase discriminator of numeral that is connected in phase frequency detector is used for the size of control charge pump charging and discharging currents, if the magnitude of voltage of the phase difference of phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, then increase the charging and discharging currents of charge pump, thereby increase loop bandwidth, reduce the resistance value of loop filter, realize quick lock in, loop stability is constant; When the loop approach locking, reduce charge pump charging and discharging currents size, adjust bandwidth to default optimal value, guarantee the optimization of systematic function.
3. but the charge pump phase locking loop circuit of quick lock in according to claim 2, it is characterized in that, the magnitude of voltage of the phase difference of described phase frequency detector output is greater than in the auxiliary phase discriminator of numeral during preset delay time, the charge pump charging and discharging currents increases to original four times, the resistance of loop filter is reduced to original half, be reduced to original half in locking time, loop phase nargin is constant simultaneously, and loop stability is constant.
4. but the charge pump phase locking loop circuit of quick lock in according to claim 2, it is characterized in that, the resistance sizes that the auxiliary phase discriminator of described numeral is regulated charge pump charging and discharging currents size and loop filter, the output signals UP B of phase frequency detector and DN through one or and delay circuit after produce signal Di, delay time T in the auxiliary phase discriminator of numeral
2Be the critical value of the phase error that is detected, by τ relatively
2With the size of phase error, the size that determines whether to open control switch control charge pump charging and discharging currents and loop filter resistance is finished quick lock in.
5. but the charge pump phase locking loop circuit of quick lock in according to claim 1 is characterized in that, adds time-delay τ on the reset circuit of described phase frequency detector
1Eliminate the phase demodulation dead band.
6. but the charge pump phase locking loop circuit of quick lock in according to claim 5 is characterized in that, described τ
1Be 6ns.
7. but the charge pump phase locking loop circuit of quick lock in according to claim 1, it is characterized in that, described phase frequency detector adopts the d type flip flop in the edge detection unit replacement phase discriminator, the EDC structure prevents the leakage of electric current by the break-make of control Mk switch, increase the lock acquisition scope, eliminate the dead band, increase its stability.
8. but the charge pump phase locking loop circuit of quick lock in according to claim 1 is characterized in that, described charge pump adopts current mirror and operational amplifier, reduces current mismatch, avoids electric charge to share.
9. but the charge pump phase locking loop circuit of quick lock in according to claim 8, it is characterized in that, described charge pump changes two output voltage U P of phase frequency detector and DN and becomes electric current output, electric current discharges and recharges loop filter, because the integral action of loop filter changes into an analog voltage signal to current signal; Charge pump is constant according to the size of current of the phase difference output of phase frequency detector, owing to discharge and recharge asynchronism(-nization), so the duty ratio of electric current is variable, charge pump is equivalent to the current source of a belt switch.
10. but the charge pump phase locking loop circuit of quick lock in according to claim 8, it is characterized in that, described charge pump adopts cascodes, cascodes can improve output resistance, the sensitiveness that electric current changes output voltage reduces, the electric current that discharges and recharges is equal substantially, the charging and discharging currents coupling.
11. but the charge pump phase locking loop circuit of quick lock in according to claim 8, it is characterized in that, the improvement structure of described charge pump adds unity gain amplifier, no matter be that MN1 and MP1 turn-off simultaneously, still MN2 and MP2 turn-off simultaneously, Vtune equals Vx, so there is not the variation of voltage in Vtune, has avoided electric charge to share.
12. but the charge pump phase locking loop circuit of quick lock in according to claim 8 is characterized in that add one road electric current from described charge pump, by the auxiliary phase discriminator control switch of numeral, the size of decision loop bandwidth is determined quick lock in.
13. but the charge pump phase locking loop circuit of quick lock in according to claim 1 is characterized in that described loop filter adopts three rank passive low ventilating filter filtering, the ripple on the filtering control signal.
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