CN112087228B - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN112087228B CN112087228B CN201910510846.2A CN201910510846A CN112087228B CN 112087228 B CN112087228 B CN 112087228B CN 201910510846 A CN201910510846 A CN 201910510846A CN 112087228 B CN112087228 B CN 112087228B
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- 238000001514 detection method Methods 0.000 claims abstract description 30
- 230000001105 regulatory effect Effects 0.000 claims abstract description 11
- 230000010355 oscillation Effects 0.000 claims abstract description 5
- 238000001914 filtration Methods 0.000 claims description 18
- 238000009825 accumulation Methods 0.000 claims description 11
- 238000004364 calculation method Methods 0.000 claims description 9
- 238000001228 spectrum Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The application discloses a phase-locked loop circuit, which comprises a main loop and a negative feedback compensation branch; the main loop includes: the phase frequency detector is used for detecting the phase difference between the reference signal and the input signal and outputting a corresponding detection result signal; a charge pump connected to the phase frequency detector; a first filter connected to the charge pump; a voltage-controlled oscillator connected to the first filter for generating and outputting an oscillation signal corresponding to the lock voltage; the voltage regulating circuit is connected with the voltage-controlled oscillator and is used for generating and outputting the input signal subjected to voltage regulation to the phase frequency detector; the input end of the negative feedback compensation branch is connected with the phase frequency detector, the output end of the negative feedback compensation branch is connected with the MOS tube capacitor in the first filter and is used for generating and outputting compensation current corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor. According to the application, the negative feedback compensation branch is introduced to provide compensation current for the MOS tube capacitor, so that reference clock burrs in an output frequency spectrum can be eliminated, and the output accuracy is improved.
Description
Technical Field
The present application relates to the field of circuit design, and in particular, to a phase-locked loop circuit.
Background
The analog Phase Lock Loop (PLL) circuit has the advantages of simple circuit, high performance, stability and the like, and is widely applied in modern wired communication systems. Referring to fig. 1, the PLL in the prior art mainly comprises a Phase Frequency Detector (PFD), a Charge Pump (CP), a filter (loop filter), a voltage controlled oscillator (voltage-controlled oscillator, VCO), and a frequency divider (divider). Typically, to reduce the area, most designers use an NMOS tube instead of the capacitor when designing the filter. In deep submicron processes, there is leakage due to the very thin gate oxide, which can result in severe reference clock glitches in the PLL's output spectrum, affecting output accuracy. In view of this, it has been a great need for a person skilled in the art to provide a solution to the above-mentioned technical problems.
Disclosure of Invention
The application aims to provide a phase-locked loop circuit so as to effectively eliminate reference clock burrs in an output frequency spectrum of the phase-locked loop circuit and improve output accuracy.
In order to solve the technical problems, in a first aspect, the application discloses a phase-locked loop circuit, which comprises a main loop and a negative feedback compensation branch; the main loop includes:
the phase frequency detector is used for detecting the phase difference between the reference signal and the input signal and outputting a corresponding detection result signal;
the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal;
A first filter coupled to the charge pump for filtering the voltage signal to output a lock-in voltage;
A voltage-controlled oscillator connected to the first filter, for generating and outputting an oscillation signal corresponding to the lock voltage;
The voltage regulating circuit is connected with the voltage-controlled oscillator and is used for regulating the amplitude of the oscillating signal, generating and outputting the input signal to the phase frequency detector;
The input end of the negative feedback compensation branch is connected with the phase frequency detector, and the output end of the negative feedback compensation branch is connected with the MOS tube capacitor in the first filter and is used for generating and outputting compensation current corresponding to the detection result signal so as to perform electric leakage compensation on the MOS tube capacitor.
Optionally, the bandwidth of the negative feedback compensation branch is smaller than the bandwidth of the main loop.
Optionally, the negative feedback compensation branch includes:
The input end of the bang-bang phase discriminator is connected with the phase frequency discriminator and is used for generating and outputting a symbol signal corresponding to the detection result signal;
an accumulator connected with the bang-bang phase discriminator and used for executing accumulation calculation according to the symbol signal and outputting a digital accumulation signal;
the digital-to-analog converter is connected with the accumulator and is used for converting the digital accumulated signals into analog voltage signals and outputting the analog voltage signals;
And the voltage-current converter is connected with the digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
Optionally, the accumulator is specifically configured to:
Performing a step-by-1 accumulation calculation when the symbol signal is low; when the symbol signal is at a high level, an accumulation calculation of step minus 1 is performed.
Optionally, the negative feedback compensation branch further includes:
A second filter connected between the digital-to-analog converter and the voltage-to-current converter.
Optionally, the second filter comprises a plurality of filtering units connected in series; each filtering unit comprises a first resistor and a first capacitor;
A first end of the first resistor is used as an input end of the filtering unit; the second end of the first resistor is connected with the first end of the first capacitor and is used as the output end of the filtering unit; the second end of the first capacitor is grounded.
Optionally, the negative feedback compensation branch includes:
the input end of the time-digital converter is connected with the phase frequency detector and is used for generating and outputting a digital signal corresponding to the detection result signal;
the sigma-delta digital-to-analog converter is connected with the time-to-digital converter and is used for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the sigma-delta digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
Optionally, the first filter includes a second capacitor, a third capacitor, and a second resistor;
The first end of the second capacitor is connected with the first end of the second resistor and is connected with the output end of the charge pump and the input end of the voltage-controlled oscillator; the second end of the second resistor is connected with the first end of the third capacitor; the second end of the second capacitor and the second end of the third capacitor are grounded.
Optionally, the ratio of the capacitance value of the third capacitor to the second capacitor is 10:1.
Optionally, the third capacitor is the MOS transistor capacitor, and a gate of the third capacitor is connected to the second end of the second resistor and the output end of the negative feedback compensation branch.
The phase-locked loop circuit provided by the application comprises a main loop and a negative feedback compensation branch; the main loop includes: the phase frequency detector is used for detecting the phase difference between the reference signal and the input signal and outputting a corresponding detection result signal; the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal; a first filter coupled to the charge pump for filtering the voltage signal to output a lock-in voltage; the voltage-controlled oscillator is connected with the first filter and is used for generating and outputting an oscillating signal corresponding to the locking voltage; the voltage regulating circuit is connected with the voltage-controlled oscillator and is used for regulating the amplitude of the oscillating signal, generating and outputting the input signal to the phase frequency detector; the input end of the negative feedback compensation branch is connected with the phase frequency detector, and the output end of the negative feedback compensation branch is connected with the MOS tube capacitor in the first filter and is used for generating and outputting compensation current corresponding to the detection result signal so as to perform electric leakage compensation on the MOS tube capacitor.
Therefore, the phase-locked loop circuit disclosed by the embodiment of the application introduces the negative feedback compensation branch on the basis of the main loop, and provides compensation current for the MOS tube capacitor in the main loop, so that the problem of electric leakage of the MOS tube capacitor is solved, the reference clock burr in the output frequency spectrum of the phase-locked loop circuit is eliminated, and the output accuracy of the phase-locked loop circuit is further effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to embodiments of the present application are only a part of embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any inventive effort, and the obtained other drawings also fall within the scope of the present application.
Fig. 1 is a circuit configuration diagram of a phase-locked loop circuit in the prior art;
fig. 2 is a circuit configuration diagram of a phase-locked loop circuit according to an embodiment of the present application;
FIG. 3 is a signal timing diagram of a leakage-free PLL circuit according to an embodiment of the present application;
FIG. 4 is a signal timing diagram of a leaky phase locked loop circuit according to an embodiment of the application;
Fig. 5 is a circuit configuration diagram of a specific phase-locked loop circuit according to an embodiment of the present application;
Fig. 6 is a circuit configuration diagram of a phase-locked loop circuit according to another embodiment of the present application;
Fig. 7 is a diagram of simulation results of a pll circuit according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a phase-locked loop circuit so as to effectively eliminate reference clock burrs in an output frequency spectrum of the phase-locked loop circuit, thereby improving the output accuracy.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Currently, in a pll circuit, an NMOS transistor is generally used as a capacitor. However, in the deep submicron process, the gate oxide is very thin, so that a leakage phenomenon exists, and further, a serious reference clock burr exists in the output frequency spectrum of the phase-locked loop circuit, and the output precision is affected. In view of the above, the present application provides a pll circuit that can effectively solve the above-mentioned problems.
Referring to fig. 2, an embodiment of the present application discloses a circuit structure of a phase-locked loop circuit, which mainly includes a main loop and a negative feedback compensation branch 20; the main loop includes:
A phase frequency detector 101 for detecting a phase difference between the reference signal ref and the input signal div and outputting a corresponding detection result signal;
a charge pump 102 connected to the phase frequency detector 101 for generating and outputting a voltage signal corresponding to the detection result signal;
a first filter 103 connected to the charge pump 102 for filtering the voltage signal to output a lock-in voltage vti;
A voltage-controlled oscillator 104 connected to the first filter 103 for generating and outputting an oscillation signal corresponding to the lock voltage vti;
the voltage regulating circuit 105 is connected with the voltage-controlled oscillator 104 and is used for regulating the amplitude of the oscillating signal, generating and outputting an input signal div to the phase frequency detector 101;
the input end of the negative feedback compensation branch 20 is connected with the phase frequency detector 101, and the output end of the negative feedback compensation branch 20 is connected with the MOS tube capacitor in the first filter 103, and is used for generating and outputting compensation current Icomp corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor.
Wherein the detection result signal outputted by the phase frequency detector 101 comprises a first detection result signal up and a second detection result signal dn.
It should be noted that, in order to reduce the area, generally, the first filter 103 is implemented based on MOS transistor devices. As a specific embodiment, the first filter 103 includes a second capacitor C2, a third capacitor C3, and a second resistor R2;
The first end of the second capacitor C2 is connected with the first end of the second resistor R2 and is connected with the output end of the charge pump 102 and the input end of the voltage-controlled oscillator 104; the second end of the second resistor R2 is connected with the first end of the third capacitor C3; the second end of the second capacitor C2 and the second end of the third capacitor C3 are grounded.
Further, the ratio of the capacitance of the third capacitor C3 to the capacitance of the second capacitor C2 may be specifically 10:1. Therefore, to save chip area, the third capacitor C3 may be specifically a MOS transistor capacitor implemented by a MOS transistor. Therefore, the gate of the MOS transistor can be used as one end of the third capacitor C3, connected to the second end of the second resistor R2, and connected to the output end of the negative feedback compensation branch 20; the drain and the source of the MOS tube may be connected to each other, and the second end of the third capacitor C3 is grounded.
However, in the deep submicron process, since the gate oxide is very thin, the MOS transistor will have leakage, so that the output spectrum of the pll circuit has serious reference clock glitches, and in particular, reference may be made to fig. 3 and 4. Fig. 3 is a signal timing diagram of a leakage-free phase-locked loop circuit according to an embodiment of the present application; fig. 4 is a signal timing diagram of a phase locked loop circuit with leakage according to an embodiment of the present application.
As can be seen from fig. 3, the locking voltage vti will remain stable under normal conditions without leakage. As can be seen from fig. 4, when there is a leakage phenomenon, the first detection result signal up output by the phase frequency detector 101 will be more than a period of time, i.e. Δt, to compensate the leakage, thereby causing the locking voltage vti to have a triangular wave-like spike burr.
Therefore, the phase-locked loop circuit provided by the embodiment of the application is further provided with the negative feedback compensation branch 20 on the basis of the main loop, and the negative feedback compensation branch is used for generating the compensation current Icomp and inputting the compensation current Icomp into the first filter 103 so as to perform leakage compensation on the MOS tube in the first filter 103, thereby avoiding the occurrence of peak burrs of the locking voltage vti of the phase-locked loop. Wherein the compensation current Icomp specifically corresponds to the detection result signal output by the phase frequency detector 101, specifically, the compensation branch should be the negative feedback compensation branch 20 so as to suppress the spike burr phenomenon through the negative feedback closed-loop control.
It should be noted that the introduction of the negative feedback compensation branch 20 should avoid the influence on the bandwidth performance of the main loop, and prevent the compensation loops where the two compensation branches are located from interfering with the main loop. Thus, further, the bandwidth of the negative feedback compensation branch 20 needs to be much smaller than the bandwidth of the main loop.
The phase-locked loop circuit disclosed in the embodiment of the application comprises a main loop and a negative feedback compensation branch 20; the main loop includes: a phase frequency detector 101 for detecting a phase difference between the reference signal ref and the input signal div and outputting a corresponding detection result signal; a charge pump 102 connected to the phase frequency detector 101 for generating and outputting a voltage signal corresponding to the detection result signal; a first filter 103 connected to the charge pump 102 for filtering the voltage signal to output a lock-in voltage vti; a voltage-controlled oscillator 104 connected to the first filter 103 for generating and outputting an oscillation signal corresponding to the lock voltage vti; the voltage regulating circuit 105 is connected with the voltage-controlled oscillator 104 and is used for regulating the amplitude of the oscillating signal, generating and outputting an input signal div to the phase frequency detector 101; the input end of the negative feedback compensation branch 20 is connected with the phase frequency detector 101, and the output end of the negative feedback compensation branch 20 is connected with the MOS tube capacitor in the first filter 103, and is used for generating and outputting compensation current Icomp corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor.
Therefore, the phase-locked loop circuit disclosed by the embodiment of the application introduces the negative feedback compensation branch 20 on the basis of the main loop, and provides the compensation current Icomp for the MOS tube capacitor in the main loop so as to solve the problem of electric leakage of the MOS tube capacitor, eliminate the reference clock burr in the output frequency spectrum of the phase-locked loop circuit and further effectively improve the output accuracy of the phase-locked loop circuit.
Referring to fig. 5, an embodiment of the present application discloses a specific circuit structure of a phase-locked loop circuit.
Based on the above, the pll circuit provided in this embodiment further includes a negative feedback compensation branch 20:
a Bang-Bang phase detector 201 (Bang-Bang Phase detector, bb_pd) with an input terminal connected to the phase frequency detector 101, for generating and outputting a symbol signal corresponding to the detection result signal;
An accumulator 202 (ACC) coupled to the bang-bang phase detector 201 for performing an accumulation calculation based on the sign signal and outputting a digital accumulated signal;
A digital-to-analog converter 203 (DAC) coupled to the accumulator 202 for converting the digital accumulated signal into an analog voltage signal and outputting the analog voltage signal;
The voltage-to-current converter 204 (VtoI) connected to the digital-to-analog converter 203 is configured to output the compensation current Icomp corresponding to the analog voltage signal to the MOS transistor capacitor in the first filter 103, and specifically, may output the compensation current Icomp to the gate of the third capacitor C3. The gate voltage after leakage compensation is lfv.
Wherein the bang-bang phase detector 201 is configured to detect a relative position of the first detection result signal up and the second detection result signal dn, and generate a sign signal. While accumulator 202 is specifically configured to: when the symbol signal is at a low level, namely 0, performing step-by-step addition 1 accumulation calculation; when the symbol signal is at a high level, i.e., 1, the accumulation calculation of step minus 1 is performed.
The high 7-bit output of the accumulator 202, i.e. AOUT <12:6>, is transferred to the digital-to-analog converter 203, the digital-to-analog converter 203 converts the high 7-bit digital signal into an analog voltage signal, and the analog voltage signal is converted into a compensation current Icomp by the voltage-to-current converter 204 to compensate the gate leakage of the MOS transistor capacitor in the first filter 103, thereby realizing the suppression of the spike burr of the locking voltage vti.
In addition, the negative feedback compensation branch 20 may further include a second filter 205 connected between the digital-to-analog converter 203 and the voltage-to-current converter 204, for stabilizing the analog voltage signal output from the digital-to-analog converter 203.
Further, the second filter 205 may include several filtering units connected in series; each filter unit comprises a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is used as the input end of the filtering unit; the second end of the first resistor R1 is connected with the first end of the first capacitor C1 and is used as the output end of the filtering unit; the second end of the first capacitor C1 is grounded.
In general, the filter units may be specifically set to 2. Of course, those skilled in the art may perform other arrangements according to practical situations, and the present application is not limited thereto.
Referring to fig. 6, another specific circuit configuration of the pll circuit is disclosed in an embodiment of the present application.
Based on the above, the pll circuit provided in this embodiment further includes a negative feedback compensation branch 20:
A time-to-digital converter 301 (Time to Digital Convert, TDC) having an input terminal connected to the phase frequency detector 101, for generating and outputting a digital signal corresponding to the detection result signal;
a sigma-delta digital-to-analog converter 302 connected to the time-to-digital converter 301 for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
The voltage-current converter 303 connected to the sigma-delta digital-to-analog converter 302 is configured to output the compensation current Icomp corresponding to the analog voltage signal to the MOS transistor capacitor in the first filter 103, specifically, output the compensation current Icomp to the gate of the third capacitor C3. The gate voltage after leakage compensation is lfv.
Further, based on the above, the negative feedback compensation branch 20 may further include a second filter 304 connected between the sigma-delta digital-to-analog converter 302 and the voltage-to-current converter 303, for stabilizing the analog voltage signal output by the sigma-delta digital-to-analog converter 302.
Further, the second filter 304 may include several filtering units connected in series; each filter unit comprises a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is used as the input end of the filtering unit; the second end of the first resistor R1 is connected with the first end of the first capacitor C1 and is used as the output end of the filtering unit; the second end of the first capacitor C1 is grounded.
The time-to-digital converter 301 may detect the time interval and directly output the digital signal result. In practice, the bang-bang phase detector 201 used in the negative feedback compensation branch 20 shown in fig. 5 can be regarded as a 1-bit output time-to-digital converter 301, and the time-to-digital converter 301 used in fig. 6 can perform multi-bit output setting, so as to have smaller quantization noise.
The sigma-delta digital-to-analog converter 302 is a cost-effective, high-speed, high-precision analog-to-digital converter commonly used in wireless and audio applications. The present embodiment can further effectively reduce circuit noise by using the high-speed sigma-delta digital-to-analog converter 302, thereby improving output accuracy.
The parts not described in detail in this embodiment may be referred to in the foregoing embodiments, and will not be described in detail herein.
Referring to fig. 7, fig. 7 is a diagram of simulation results of a pll circuit according to an embodiment of the present application.
During the period of 0-32us, the negative feedback compensation branch 20 is not started, and at this time, a voltage difference exists between vti and lfv due to the leakage of the MOS transistor. The lines presented in fig. 7 are thicker because of the presence of the triangular signal glitches in the vti signal. After 32us, the negative feedback compensation branch 20 starts to start, the compensation current Icomp gradually approaches the leakage current, so that the voltage difference between vti and lfv is smaller and smaller, when the compensation current Icomp is completely equal to the leakage current, vti and lfv coincide, after the circuit reaches a stable state, triangular wave burrs of the vti signal are eliminated, and the presented signal line is thinned.
In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred. For the apparatus disclosed in the examples, since it corresponds to the method disclosed in the examples, the description is relatively simple, and the relevant points are referred to in the description of the method section.
It should also be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The technical scheme provided by the application is described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present application may be modified and practiced without departing from the spirit of the present application.
Claims (8)
1.A phase-locked loop circuit is characterized by comprising a main loop and a negative feedback compensation branch; the main loop includes:
the phase frequency detector is used for detecting the phase difference between the reference signal and the input signal and outputting a corresponding detection result signal;
the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal;
A first filter coupled to the charge pump for filtering the voltage signal to output a lock-in voltage;
A voltage-controlled oscillator connected to the first filter, for generating and outputting an oscillation signal corresponding to the lock voltage;
The voltage regulating circuit is connected with the voltage-controlled oscillator and is used for regulating the amplitude of the oscillating signal, generating and outputting the input signal to the phase frequency detector;
the input end of the negative feedback compensation branch is connected with the phase frequency detector, and the output end of the negative feedback compensation branch is connected with the MOS tube capacitor in the first filter and is used for generating and outputting compensation current corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor;
The bandwidth of the negative feedback compensation branch is smaller than that of the main loop; the negative feedback compensation branch includes:
The input end of the bang-bang phase discriminator is connected with the phase frequency discriminator and is used for generating and outputting a symbol signal corresponding to the detection result signal;
an accumulator connected with the bang-bang phase discriminator and used for executing accumulation calculation according to the symbol signal and outputting a digital accumulation signal;
the digital-to-analog converter is connected with the accumulator and is used for converting the digital accumulated signals into analog voltage signals and outputting the analog voltage signals;
And the voltage-current converter is connected with the digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
2. The phase-locked loop circuit of claim 1, wherein the accumulator is configured to:
Performing a step-by-1 accumulation calculation when the symbol signal is low; when the symbol signal is at a high level, an accumulation calculation of step minus 1 is performed.
3. The phase locked loop circuit of claim 2, wherein the negative feedback compensation leg further comprises:
A second filter connected between the digital-to-analog converter and the voltage-to-current converter.
4. A phase locked loop circuit as claimed in claim 3, wherein said second filter comprises a plurality of filter units connected in series; each filtering unit comprises a first resistor and a first capacitor;
A first end of the first resistor is used as an input end of the filtering unit; the second end of the first resistor is connected with the first end of the first capacitor and is used as the output end of the filtering unit; the second end of the first capacitor is grounded.
5. The phase locked loop circuit of claim 1, wherein the negative feedback compensation leg comprises:
the input end of the time-digital converter is connected with the phase frequency detector and is used for generating and outputting a digital signal corresponding to the detection result signal;
the sigma-delta digital-to-analog converter is connected with the time-to-digital converter and is used for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the sigma-delta digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
6. A phase locked loop circuit as claimed in any one of claims 1 to 5, wherein the first filter comprises a second capacitor, a third capacitor and a second resistor;
The first end of the second capacitor is connected with the first end of the second resistor and is connected with the output end of the charge pump and the input end of the voltage-controlled oscillator; the second end of the second resistor is connected with the first end of the third capacitor; the second end of the second capacitor and the second end of the third capacitor are grounded.
7. The phase-locked loop circuit of claim 6, wherein a ratio of the capacitance of the third capacitor to the capacitance of the second capacitor is 10:1.
8. The pll circuit of claim 7 wherein the third capacitor is a capacitor of the MOS transistor, and a gate of the third capacitor is connected to the second end of the second resistor and the output end of the negative feedback compensation branch.
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| CN115800997B (en) * | 2023-01-31 | 2023-04-28 | 上海韬润半导体有限公司 | Novel sampling phase-locked loop circuit |
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