CN102006058A - PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit - Google Patents
PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit Download PDFInfo
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- CN102006058A CN102006058A CN 200910189689 CN200910189689A CN102006058A CN 102006058 A CN102006058 A CN 102006058A CN 200910189689 CN200910189689 CN 200910189689 CN 200910189689 A CN200910189689 A CN 200910189689A CN 102006058 A CN102006058 A CN 102006058A
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Abstract
The invention is suitable for the PLL (Phase-Locked Loop) field and provides a PLL leakage current compensation circuit and a PLL circuit. The PLL leakage current compensation circuit comprises a first compensation circuit connected to the output end of a charge pump circuit to compensate a leakage current generated in the charge pump circuit. The PLL leakage current compensation circuit provided by the invention compensates the leakage current generated in the charge pump circuit by adopting the first compensation circuit so as to eliminate adverse influences brought by the leakage current and ensure the stable performance of PLL output frequency, and meanwhile, the PLL leakage current compensation circuit also compensates a leakage current generated in a loop filter circuit by adopting a second compensation circuit to lessen the influence brought by the leakage current in the loop filter circuit, therefore, the performance of the PLL output frequency is ensured and the advantages of chip area reduction and cost saving are achieved..
Description
Technical field
The invention belongs to the phase-locked loop field, relate in particular to a kind of phase-locked loop leakage current compensating circuit and phase-locked loop circuit.
Background technology
In sub-micro or more advanced CMOS technology,, make leakage current become more and more serious because gate oxide thins down and subthreshold voltage is more and more lower.In 0.13umCMOS technology or 90nmCMOS technology, design work voltage is that (Phase LockedLoop PLL) will face the challenge of leakage current restriction for phase-locked loop about 1V; Leakage current can increase the extra power consumption of phase-locked loop, introduces noise, has influence on its performance index.
Generally, in these advanced CMOS technologies, leakage current mainly is divided into three types: (1) tunnel leaks (tunneling leakage) electric current, and it is relevant with the thickness of gate oxide; (2) sub-threshold leakage (subthreshold leakage) electric current, it is relevant with transistorized subthreshold voltage; (3) the pn junction diode leaks (junction diode leakage) electric current, and it has the pass with the pn of parasitism.
Fig. 1 shows the Leakage Current illustraton of model of phase-locked loop circuit in the prior art, and wherein, 1 is the phase demodulation discriminator, and 4 is frequency divider, and 6 is voltage controlled oscillator, and Ileak represents leakage current; For convenience of explanation, main charge pump circuit replaces with K switch 1, and inferior charge pump circuit replaces with K switch 2; The break-make of phase demodulation discriminator 1 output control signal and control switch K1 and K switch 2 can clearly be found out from figure, all has leakage current Ileak in phase demodulation discriminator 1, frequency divider 4, voltage controlled oscillator 6, K switch 1, K2 and the capacitor C 1.Phase detection discriminator 1 (Phase Frequency Detector, PFD) and frequency divider 4 (divider) in, leakage current has increased extra power consumption and noise; And in charge pump circuit, the type of leakage current mainly is a sub-threshold leakage current, when charge pump circuit turn-offs, it also may discharge and recharge loop filtering capacitor C 1, this can cause voltage controlled oscillator 6 (Voltage Control Oscillator, the voltage of control input end VCO) fluctuates back and forth, has influence on the frequency fluctuation of phase-locked loop output clock.In the low pass filter, in 0.13um or more advanced CMOS technology, can there be more serious tunnel leakage current in mos capacitance, and the mos capacitance area is big more, and its leakage current is also big more.
In the digital circuit the inside, leakage current can cause too high standby quiescent current; And in the analog circuit the inside, it will reduce the precision of circuit, influences performance index.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of phase-locked loop leakage current compensating circuit, and being intended to solve leakage current has increased the power consumption of phase-locked loop and the problem of noise.
The embodiment of the invention is achieved in that a kind of phase-locked loop leakage current compensating circuit, and described phase-locked loop leakage current compensating circuit comprises: first compensating circuit, be connected to the output of charge pump circuit, and be used for the leakage current that the compensation charge pump circuit produces.
Wherein, described charge pump circuit comprises: main charge pump circuit and time charge pump circuit; Described main charge pump circuit comprises:
Metal-oxide-semiconductor Mp1, its source electrode connects power supply, the grounded-grid of described metal-oxide-semiconductor Mp1;
Metal-oxide-semiconductor Mp2, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp1, and the grid of described metal-oxide-semiconductor Mp2 connects first control signal of phase demodulation discriminator output;
Metal-oxide-semiconductor Mn1, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp2, and the grid of described metal-oxide-semiconductor Mn1 connects second control signal of phase demodulation discriminator output; The link of described metal-oxide-semiconductor Mn1 and described metal-oxide-semiconductor Mp2 is as the output of described main charge pump circuit; And
Metal-oxide-semiconductor Mn2, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mn1, the source ground of described metal-oxide-semiconductor Mn2, described metal-oxide-semiconductor Mn2 grid connects power supply;
Described time charge pump circuit comprises:
Metal-oxide-semiconductor Mpr1, its source electrode connects power supply, the grounded-grid of described metal-oxide-semiconductor Mpr1;
Metal-oxide-semiconductor Mpr2, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mpr1, and the grid of described metal-oxide-semiconductor Mpr2 connects first control signal of phase demodulation discriminator output;
Metal-oxide-semiconductor Mnr1, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mpr2, and the grid of described metal-oxide-semiconductor Mnr1 connects second control signal of phase demodulation discriminator output; The link of described metal-oxide-semiconductor Mnr1 and described metal-oxide-semiconductor Mpr2 is as the output of described charge pump circuit; And
Metal-oxide-semiconductor Mnr2, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mnr1, the source ground of described metal-oxide-semiconductor Mnr2, described metal-oxide-semiconductor Mnr2 grid connects power supply.
Wherein, described first compensating circuit comprises: operational amplifier and leakage current generator;
The positive input of described operational amplifier is connected to the output of described charge pump circuit, and the reverse input end of described operational amplifier is connected to the output of described main charge pump circuit;
The input of described leakage current generator is connected to the output of described operational amplifier, first output of described leakage current generator is connected to the output of described main charge pump circuit, and second output of described leakage current generator is connected to the output of described charge pump circuit.
Wherein, described leakage current generator comprises:
Metal-oxide-semiconductor Mp3, its source electrode and grid are connected to power supply respectively;
Metal-oxide-semiconductor Mp4, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp3;
Metal-oxide-semiconductor Mn3, its grid is connected to the grid of described metal-oxide-semiconductor Mp4, and the drain electrode of described metal-oxide-semiconductor Mn3 is connected to the drain electrode of described metal-oxide-semiconductor Mp4;
Metal-oxide-semiconductor Mn4, its drain electrode is connected to the source electrode of described metal-oxide-semiconductor Mn3, and the grid of described metal-oxide-semiconductor Mn4 is connected back ground connection with source electrode;
Described metal-oxide-semiconductor Mp4 and described metal-oxide-semiconductor Mn3 grid link are as the input of described leakage current generator and be connected to the output of described operational amplifier; Described metal-oxide-semiconductor Mp4 and described metal-oxide-semiconductor Mn3 drain electrode link is as first output of described leakage current generator and be connected to the output of described main charge pump circuit;
Metal-oxide-semiconductor Mp5, its source electrode and grid are connected to power supply respectively;
Metal-oxide-semiconductor Mp6, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp5;
Metal-oxide-semiconductor Mn5, its grid is connected to the grid of described metal-oxide-semiconductor Mp6, and the drain electrode of described metal-oxide-semiconductor Mn5 is connected to the drain electrode of described metal-oxide-semiconductor Mp4;
Metal-oxide-semiconductor Mn6; Its drain electrode is connected to the source electrode of described metal-oxide-semiconductor Mn5, and the grid of described metal-oxide-semiconductor Mn6 is connected back ground connection with source electrode;
Described metal-oxide-semiconductor Mp6 and described metal-oxide-semiconductor Mn5 grid link are as the input of described leakage current generator and be connected to the output of described operational amplifier; Described metal-oxide-semiconductor Mp6 and described metal-oxide-semiconductor Mn5 drain electrode link is as second output of described leakage current generator and be connected to the output of described charge pump circuit.
Wherein, the big 10-20 of electric current of the described leakage current generator output of the current ratio of described main charge pump circuit output doubly.
Wherein, described phase-locked loop leakage current compensating circuit also comprises: second compensating circuit, be connected with the loop filtering circuit, and be used for the leakage current that the compensation loop filter circuit produces.
Wherein, described loop filtering circuit comprises: resistance R 1, capacitor C 1, capacitor C 2 and capacitor C 3; One end of described resistance R 1 is connected to the output of main charge pump circuit, and the other end of described resistance R 1 is by described capacitor C 1 ground connection; One end of described capacitor C 2 is connected to the output of main charge pump circuit, the other end ground connection of described capacitor C 2; One end of described capacitor C 3 is connected to the output of time charge pump circuit, the other end ground connection of described capacitor C 3;
Described capacitor C 1 is a mos capacitance, and described capacitor C 2 is a MIN electric capacity with described capacitor C 3.
Wherein, described second compensating circuit is a voltage buffer.
Wherein, described voltage buffer comprises: difference is imported module, and two pairs of difference input voltage signals are provided; Common source amplifies output stage, according to described difference input two pairs of difference input voltage signals that module provides is amplified back output with output voltage signal.
Another purpose of the embodiment of the invention is to provide a kind of phase-locked loop circuit, and it comprises phase demodulation discriminator and the charge pump circuit that is connected to the output of described phase demodulation discriminator; Described phase-locked loop circuit also comprises above-mentioned phase-locked loop leakage current compensating circuit.
The phase-locked loop leakage current compensating circuit that the embodiment of the invention provides adopts first compensating circuit that the leakage current that produces in the charge pump circuit is compensated, and has eliminated the harmful effect that leakage current brings, and has guaranteed the stable performance of phase-lock-ring output frequency; Adopt second compensating circuit that the leakage current in the loop filtering circuit is compensated simultaneously, reduced the influence that leakage current brings in the loop filtering circuit; Guarantee the performance of phase-lock-ring output frequency, saved chip area, saved cost; The power consumption and the noise of phase-locked loop have also been reduced simultaneously.
Description of drawings
Fig. 1 is the Leakage Current illustraton of model of phase-locked loop circuit in the prior art;
Fig. 2 is the modular structure schematic diagram of the phase-locked loop circuit that provides of first embodiment of the invention;
Fig. 3 is the circuit diagram of the phase-locked loop circuit that provides of first embodiment of the invention;
Fig. 4 is the modular structure schematic diagram of the phase-locked loop circuit that provides of second embodiment of the invention;
Fig. 5 is the circuit diagram of the phase-locked loop circuit that provides of second embodiment of the invention;
Fig. 6 is the circuit diagram of voltage buffer in the phase-locked loop leakage current compensating circuit that provides of second embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The phase-locked loop leakage current compensating circuit that the embodiment of the invention provides adopts first compensating circuit that the leakage current that produces in the charge pump circuit is compensated, and has eliminated the harmful effect that leakage current brings, and has guaranteed the stable performance of phase-lock-ring output frequency.
The phase-locked loop leakage current compensating circuit that the embodiment of the invention provides is mainly used in the phase-locked loop circuit, and the leakage current that phase-locked loop circuit is produced compensates.Fig. 2 shows the modular structure of the phase-locked loop circuit that first embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with first embodiment of the invention, and details are as follows.
Phase-locked loop circuit comprises phase demodulation discriminator 1, charge pump circuit, frequency divider 4, loop filtering circuit 5, voltage controlled oscillator 6 and phase-locked loop leakage current compensating circuit; Wherein phase-locked loop leakage current compensating circuit comprises first compensating circuit 7, is connected to the output of charge pump circuit, is used for the leakage current that the compensation charge pump circuit produces.
In embodiments of the present invention, charge pump circuit comprises: main charge pump circuit 2 and time charge pump circuit 3, first compensating circuit 7 is connected with time charge pump circuit 3 with main charge pump circuit 2 respectively, respectively the leakage current that produces in main charge pump circuit 2 and time charge pump circuit 3 is compensated.
Fig. 3 shows the circuit diagram of the phase-locked loop circuit that first embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with first embodiment of the invention, and details are as follows.
Main charge pump circuit 2 comprises: metal-oxide-semiconductor Mp1, metal-oxide-semiconductor Mp2, metal-oxide-semiconductor Mn1 and metal-oxide-semiconductor Mn2; Wherein the source electrode of metal-oxide-semiconductor Mp1 connects power vd D, the grounded-grid of metal-oxide-semiconductor Mp1; The source electrode of metal-oxide-semiconductor Mp2 is connected to the drain electrode of metal-oxide-semiconductor Mp1, and the grid of metal-oxide-semiconductor Mp2 connects the first control signal Up of phase demodulation discriminator 1 output; The drain electrode of metal-oxide-semiconductor Mn1 is connected to the drain electrode of metal-oxide-semiconductor Mp2, and the grid of metal-oxide-semiconductor Mn1 connects the second control signal Dn of phase demodulation discriminator 1 output; The link S1 of metal-oxide-semiconductor Mn1 and metal-oxide-semiconductor Mp2 is as the output of main charge pump circuit 2; The drain electrode of metal-oxide-semiconductor Mn2 is connected to the drain electrode of metal-oxide-semiconductor Mn1, the source ground of metal-oxide-semiconductor Mn2, and metal-oxide-semiconductor Mn2 grid connects power vd D.
Inferior charge pump circuit 3 comprises: metal-oxide-semiconductor Mpr1, metal-oxide-semiconductor Mpr2, metal-oxide-semiconductor Mnr1 and metal-oxide-semiconductor Mnr2; Wherein, the source electrode of metal-oxide-semiconductor Mpr1 connects power vd D, the grounded-grid of metal-oxide-semiconductor Mpr1; The source electrode of metal-oxide-semiconductor Mpr2 is connected to the drain electrode of metal-oxide-semiconductor Mpr1, and the grid of metal-oxide-semiconductor Mpr2 connects the first control signal Up of phase demodulation discriminator 1 output; The drain electrode of metal-oxide-semiconductor Mnr1 is connected to the drain electrode of metal-oxide-semiconductor Mpr2, and the grid of metal-oxide-semiconductor Mnr1 connects the second control signal Dn of phase demodulation discriminator 1 output; The link S2 of metal-oxide-semiconductor Mnr1 and metal-oxide-semiconductor Mpr2 is as the output of time charge pump circuit 3; The drain electrode of metal-oxide-semiconductor Mnr2 is connected to the drain electrode of metal-oxide-semiconductor Mnr1, the source ground of metal-oxide-semiconductor Mnr2, and metal-oxide-semiconductor Mnr2 grid connects power vd D.
First compensating circuit 7 comprises: operational amplifier 71 and leakage current generator 72; Wherein, the output S2 of the positive input of operational amplifier 71+be connected to time charge pump circuit 3, the reverse input end of operational amplifier 71-the be connected to output S1 of main charge pump circuit 2; The input of leakage current generator 72 is connected to the output of operational amplifier 71, first output of leakage current generator 72 is connected to the output S1 of main charge pump circuit 2, and second output of leakage current generator 72 is connected to the output S2 of time charge pump circuit 3.
As one embodiment of the present of invention, leakage current generator 72 is to be used for compensating the leakage current that produces in two charge pump circuits, in order not influence the operate as normal of main charge pump circuit 2, and compensate in the main charge pump circuit 2 leakage current as far as possible exactly to the influence of main charge pump circuit 2 output voltage V ct, the big 10-20 of electric current of current ratio leakage current generator 72 outputs of main charge pump circuit 2 outputs doubly.
In embodiments of the present invention, leakage current generator 72 comprises: metal-oxide-semiconductor Mp3, metal-oxide-semiconductor Mp4, metal-oxide-semiconductor Mn3, metal-oxide-semiconductor Mn4, metal-oxide-semiconductor Mp5, metal-oxide-semiconductor Mp6, metal-oxide-semiconductor Mn5 and metal-oxide-semiconductor Mn6; Wherein, the source electrode of metal-oxide-semiconductor Mp3 and grid are connected to power vd D respectively; The source electrode of metal-oxide-semiconductor Mp4 is connected to the drain electrode of metal-oxide-semiconductor Mp3; The grid of metal-oxide-semiconductor Mn3 is connected to the grid of metal-oxide-semiconductor Mp4, and the drain electrode of metal-oxide-semiconductor Mn3 is connected to the drain electrode of metal-oxide-semiconductor Mp4; The drain electrode of metal-oxide-semiconductor Mn4 is connected to the source electrode of metal-oxide-semiconductor Mn3, and the grid of metal-oxide-semiconductor Mn4 is connected back ground connection with source electrode; Metal-oxide-semiconductor Mp4 and metal-oxide-semiconductor Mn3 grid link are as the input S3 of leakage current generator 7 and be connected to the output of operational amplifier 71; Metal-oxide-semiconductor Mp4 and metal-oxide-semiconductor Mn3 drain electrode link S4 is as the first output S4 of leakage current generator 72 and be connected to the output S1 of main charge pump circuit 2; The source electrode of metal-oxide-semiconductor Mp5 and grid are connected to power vd D respectively; The source electrode of metal-oxide-semiconductor Mp6 is connected to the drain electrode of metal-oxide-semiconductor Mp5; The grid of metal-oxide-semiconductor Mn5 is connected to the grid of metal-oxide-semiconductor Mp6, and the drain electrode of metal-oxide-semiconductor Mn5 is connected to the drain electrode of metal-oxide-semiconductor Mp4; The drain electrode of metal-oxide-semiconductor Mn6 is connected to the source electrode of metal-oxide-semiconductor Mn5, and the grid of metal-oxide-semiconductor Mn6 is connected back ground connection with source electrode; Metal-oxide-semiconductor Mp6 and metal-oxide-semiconductor Mn5 grid link S5 are as the input of leakage current generator 72 and be connected to the output of operational amplifier 71; Metal-oxide-semiconductor Mp6 and metal-oxide-semiconductor Mn5 drain electrode link S6 is as second output of leakage current generator 72 and be connected to the output S2 of time charge pump circuit 3.
In embodiments of the present invention, two control signal Up of phase detection discriminator 1 output and Dn are used for controlling opening and turn-offing of charge pump circuit; Because time charge pump circuit 3 and main charge pump circuit 2 are identical, time charge pump circuit 3 also is the same with the leakage current that main charge pump circuit 2 produces so, the capacitor C 3 of time charge pump circuit 3 output terminations is smaller simultaneously, leakage current discharges and recharges caused voltage fluctuation amplitude just more greatly to it, is convenient to be detected by operational amplifier 71; Wherein operational amplifier 71 is to be used for the voltage Vct of more main charge pump circuit 2 outputs and the voltage Vct_cm of time charge pump circuit 3 outputs, operational amplifier 71 is according to the comparative result output control signal of these two voltages, and the opening and off state of the metal-oxide-semiconductor in the control leakage current generator 72, the leakage current that utilizes 72 generations of leakage current generator is respectively to the capacitor C in the loop filtering circuit 51, capacitor C 2 and capacitor C 3 discharge and recharge accordingly, thereby reach the good compensating action of leakage current in the main charge pump circuit 2; In the stabilized state, the voltage Vct of main charge pump circuit 2 outputs finally can trend towards equating with the voltage Vct_cm of time charge pump circuit 3 outputs.
Fig. 4 shows the modular structure of the phase-locked loop circuit that second embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with second embodiment of the invention, and details are as follows.
Phase-locked loop circuit comprises phase demodulation discriminator 1, charge pump circuit, frequency divider 4, loop filtering circuit 5, voltage controlled oscillator 6 and phase-locked loop leakage current compensating circuit; Wherein phase-locked loop leakage current compensating circuit comprises that first compensating circuit 7 and second compensating circuit, 8, the first compensating circuits 7 are connected to the output of charge pump circuit, are used for the leakage current that the compensation charge pump circuit produces; Second compensating circuit 8 is connected with loop filtering circuit 5, is used for the leakage current that compensation loop filter circuit 5 produces.
In embodiments of the present invention, charge pump circuit comprises: main charge pump circuit 2 and time charge pump circuit 3, first compensating circuit 7 is connected with time charge pump circuit 3 with main charge pump circuit 2 respectively, respectively the leakage current that produces in main charge pump circuit 2 and time charge pump circuit 3 is compensated.
Fig. 5 shows the circuit of the phase-locked loop circuit that second embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with second embodiment of the invention, and details are as follows.
Main charge pump circuit 2 in the circuit of main charge pump circuit 2 and time charge pump circuit 3 and the first embodiment of the invention is identical with the circuit of inferior charge pump circuit 3, does not repeat them here.
First compensating circuit 7 comprises: operational amplifier 71 and leakage current generator 72; Wherein, the output S2 of the positive input of operational amplifier 71+be connected to time charge pump circuit 3, the reverse input end of operational amplifier 71-the be connected to output S1 of main charge pump circuit 2; The input of leakage current generator 72 is connected to the output of operational amplifier 71, first output of leakage current generator 72 is connected to the output S1 of main charge pump circuit 2, and second output of leakage current generator 72 is connected to the output S2 of time charge pump circuit 3.
Second compensating circuit 8 can be voltage buffer Ab, wherein, the positive input of voltage buffer Ab+the be connected to output S1 of main charge pump circuit 2, the link of the reverse input end of voltage buffer Ab-be connected to resistance R 1 and capacitor C 1, the output of voltage buffer Ab be connected to the reverse input end of voltage buffer Ab-.
In embodiments of the present invention, when phase-locked loop was in stable state, the voltage Vct of main charge pump circuit 2 outputs finally can trend towards equating with the voltage Vct_cm of time charge pump circuit 3 outputs; But because there is leakage current in mos capacitance C1, can cause the voltage Vct1 at capacitor C 1 two ends to descend, meanwhile, the voltage Vct of main charge pump circuit 2 outputs also can follow decline, will reduce the performance of phase-locked loop like this; In order to compensate the influence of leakage current, increased a voltage buffer Ab, leakage current causes the voltage Vct1 at capacitor C 1 two ends slowly to descend, but because the decline of the voltage Vct of main charge pump circuit 2 outputs is to lag behind the voltage Vct1's at capacitor C 1 two ends, before the voltage Vct of main charge pump circuit 2 outputs descends or when just having begun to descend, by voltage buffer Ab mos capacitance C1 is charged, the voltage Vct1 at capacitor C 1 two ends is raise, equal the voltage Vct of main charge pump circuit 2 outputs; Influence that so just can compensating MOS capacitance leakage electric current.
In embodiments of the present invention, in order to make phase-locked loop output reference clock frequency big as much as possible to satisfy different practical applications, the voltage swing of the control input end Vct of voltage controlled oscillator 6 also must be big as much as possible, so the input voltage amplitude of oscillation of voltage buffer Ab and output voltage swing are that requirement is bigger; Simultaneously also require the open-loop gain of voltage buffer Ab also big as much as possible, its output stage can the big mos capacitance of fast driving.
Fig. 6 shows the circuit of the voltage buffer Ab that the embodiment of the invention provides, for convenience of explanation, only shows the part relevant with the embodiment of the invention, and details are as follows.
Voltage buffer Ab comprises: the difference input is amplified output stage 82 to module 81 and common source, wherein, the difference input provides two pairs of difference input voltage signals to module 81, and common source amplifies output stage 82 and according to the difference input two pairs of difference input voltage signals that module 81 provides amplified back output with output voltage signal.The difference input is right to the difference input that module 81 has complementarity, has increased the input voltage amplitude of oscillation of voltage buffer Ab; Common source amplifies open-loop gain and the output voltage swing that output stage 82 can increase voltage buffer Ab simultaneously.
The difference input comprises module 81: metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7 and metal-oxide-semiconductor M8; The grid of metal-oxide-semiconductor M5 is connected the back and connects positive input voltage Vin+ with the grid of metal-oxide-semiconductor M7, the source electrode of metal-oxide-semiconductor M5 is connected with the source electrode of metal-oxide-semiconductor M6; The negative input voltage vin of grid connection of metal-oxide-semiconductor M6-, metal-oxide-semiconductor M7 source electrode be connected with metal-oxide-semiconductor M8 source electrode, the negative input voltage vin of grid connection of metal-oxide-semiconductor M8-, the drain electrode of the drain electrode of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M8 is connected to the input that common source amplifies output stage 82 respectively; The drain electrode of metal-oxide-semiconductor M5 is connected to the drain electrode of metal-oxide-semiconductor M14 in the biasing circuit; The drain electrode of metal-oxide-semiconductor M7 is connected to the drain electrode of metal-oxide-semiconductor M3 in the biasing circuit.
Common source amplifies output stage 82 and comprises: metal-oxide-semiconductor M9 and metal-oxide-semiconductor M10, wherein the grid of metal-oxide-semiconductor M9 is connected output stage 82 is amplified in the back as common source input with the grid of metal-oxide-semiconductor M10, the drain electrode of metal-oxide-semiconductor M9 is connected output stage 82 is amplified in the back as common source output with the drain electrode of metal-oxide-semiconductor M10, the source electrode of metal-oxide-semiconductor M9 connects power vd D, the source ground of metal-oxide-semiconductor M10.
Biasing circuit comprises: metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M11, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, metal-oxide-semiconductor M14 and metal-oxide-semiconductor M15 because this biasing circuit is existing biasing circuit, therefore do not repeat them here.
The phase-locked loop leakage current compensating circuit that the embodiment of the invention provides adopts first compensating circuit that the leakage current that produces in the charge pump circuit is compensated, and has eliminated the harmful effect that leakage current brings, and has guaranteed the stable performance of phase-lock-ring output frequency; Adopt second compensating circuit that the leakage current in the loop filtering circuit is compensated simultaneously, reduced the influence that leakage current brings in the loop filtering circuit; Guarantee the performance of phase-lock-ring output frequency, saved chip area, saved cost; The power consumption and the noise of phase-locked loop have also been reduced simultaneously.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a phase-locked loop leakage current compensating circuit is characterized in that, described phase-locked loop leakage current compensating circuit comprises: first compensating circuit, be connected to the output of charge pump circuit, and be used for the leakage current that the compensation charge pump circuit produces.
2. phase-locked loop leakage current compensating circuit as claimed in claim 1 is characterized in that described charge pump circuit comprises: main charge pump circuit and time charge pump circuit; Described main charge pump circuit comprises:
Metal-oxide-semiconductor Mp1, its source electrode connects power supply, the grounded-grid of described metal-oxide-semiconductor Mp1;
Metal-oxide-semiconductor Mp2, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp1, and the grid of described metal-oxide-semiconductor Mp2 connects first control signal of phase demodulation discriminator output;
Metal-oxide-semiconductor Mn1, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp2, and the grid of described metal-oxide-semiconductor Mn1 connects second control signal of phase demodulation discriminator output; The link of described metal-oxide-semiconductor Mn1 and described metal-oxide-semiconductor Mp2 is as the output of described main charge pump circuit; And
Metal-oxide-semiconductor Mn2, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mn1, the source ground of described metal-oxide-semiconductor Mn2, described metal-oxide-semiconductor Mn2 grid connects power supply;
Described time charge pump circuit comprises:
Metal-oxide-semiconductor Mpr1, its source electrode connects power supply, the grounded-grid of described metal-oxide-semiconductor Mpr1;
Metal-oxide-semiconductor Mpr2, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mpr1, and the grid of described metal-oxide-semiconductor Mpr2 connects first control signal of phase demodulation discriminator output;
Metal-oxide-semiconductor Mnr1, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mpr2, and the grid of described metal-oxide-semiconductor Mnr1 connects second control signal of phase demodulation discriminator output; The link of described metal-oxide-semiconductor Mnr1 and described metal-oxide-semiconductor Mpr2 is as the output of described charge pump circuit; And
Metal-oxide-semiconductor Mnr2, its drain electrode is connected to the drain electrode of described metal-oxide-semiconductor Mnr1, the source ground of described metal-oxide-semiconductor Mnr2, described metal-oxide-semiconductor Mnr2 grid connects power supply.
3. phase-locked loop leakage current compensating circuit as claimed in claim 2 is characterized in that, described first compensating circuit comprises:
Operational amplifier and leakage current generator;
The positive input of described operational amplifier is connected to the output of described charge pump circuit, and the reverse input end of described operational amplifier is connected to the output of described main charge pump circuit;
The input of described leakage current generator is connected to the output of described operational amplifier, first output of described leakage current generator is connected to the output of described main charge pump circuit, and second output of described leakage current generator is connected to the output of described charge pump circuit.
4. phase-locked loop leakage current compensating circuit as claimed in claim 3 is characterized in that, described leakage current generator comprises:
Metal-oxide-semiconductor Mp3, its source electrode and grid are connected to power supply respectively;
Metal-oxide-semiconductor Mp4, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp3;
Metal-oxide-semiconductor Mn3, its grid is connected to the grid of described metal-oxide-semiconductor Mp4, and the drain electrode of described metal-oxide-semiconductor Mn3 is connected to the drain electrode of described metal-oxide-semiconductor Mp4;
Metal-oxide-semiconductor Mn4, its drain electrode is connected to the source electrode of described metal-oxide-semiconductor Mn3, and the grid of described metal-oxide-semiconductor Mn4 is connected back ground connection with source electrode;
Described metal-oxide-semiconductor Mp4 and described metal-oxide-semiconductor Mn3 grid link are as the input of described leakage current generator and be connected to the output of described operational amplifier; Described metal-oxide-semiconductor Mp4 and described metal-oxide-semiconductor Mn3 drain electrode link is as first output of described leakage current generator and be connected to the output of described main charge pump circuit;
Metal-oxide-semiconductor Mp5, its source electrode and grid are connected to power supply respectively;
Metal-oxide-semiconductor Mp6, its source electrode is connected to the drain electrode of described metal-oxide-semiconductor Mp5;
Metal-oxide-semiconductor Mn5, its grid is connected to the grid of described metal-oxide-semiconductor Mp6, and the drain electrode of described metal-oxide-semiconductor Mn5 is connected to the drain electrode of described metal-oxide-semiconductor Mp4;
Metal-oxide-semiconductor Mn6; Its drain electrode is connected to the source electrode of described metal-oxide-semiconductor Mn5, and the grid of described metal-oxide-semiconductor Mn6 is connected back ground connection with source electrode;
Described metal-oxide-semiconductor Mp6 and described metal-oxide-semiconductor Mn5 grid link are as the input of described leakage current generator and be connected to the output of described operational amplifier; Described metal-oxide-semiconductor Mp6 and described metal-oxide-semiconductor Mn5 drain electrode link is as second output of described leakage current generator and be connected to the output of described charge pump circuit.
5. phase-locked loop leakage current compensating circuit as claimed in claim 3 is characterized in that, the big 10-20 of electric current of the described leakage current generator output of the current ratio of described main charge pump circuit output doubly.
6. phase-locked loop leakage current compensating circuit as claimed in claim 2 is characterized in that, described phase-locked loop leakage current compensating circuit also comprises: second compensating circuit, be connected with the loop filtering circuit, and be used for the leakage current that the compensation loop filter circuit produces.
7. phase-locked loop leakage current compensating circuit as claimed in claim 6 is characterized in that, described loop filtering circuit comprises: resistance R 1, capacitor C 1, capacitor C 2 and capacitor C 3; One end of described resistance R 1 is connected to the output of main charge pump circuit, and the other end of described resistance R 1 is by described capacitor C 1 ground connection; One end of described capacitor C 2 is connected to the output of main charge pump circuit, the other end ground connection of described capacitor C 2; One end of described capacitor C 3 is connected to the output of time charge pump circuit, the other end ground connection of described capacitor C 3;
Described capacitor C 1 is a mos capacitance, and described capacitor C 2 is a MIN electric capacity with described capacitor C 3.
8. phase-locked loop leakage current compensating circuit as claimed in claim 6 is characterized in that described second compensating circuit is a voltage buffer.
9. phase-locked loop leakage current compensating circuit as claimed in claim 8 is characterized in that described voltage buffer comprises:
The difference input provides two pairs of difference input voltage signals to module;
Common source amplifies output stage, according to described difference input two pairs of difference input voltage signals that module provides is amplified back output with output voltage signal.
10. phase-locked loop circuit, it comprises phase demodulation discriminator and the charge pump circuit that is connected to the output of described phase demodulation discriminator; It is characterized in that described phase-locked loop circuit also comprises each described phase-locked loop leakage current compensating circuit of claim 1-9.
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| CN 200910189689 CN102006058B (en) | 2009-08-31 | 2009-08-31 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
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| CN 200910189689 CN102006058B (en) | 2009-08-31 | 2009-08-31 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
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| CN102571082A (en) * | 2012-03-22 | 2012-07-11 | 秉亮科技（苏州）有限公司 | Phase-locked loop for gate leakage current of V2I tube in dynamic compensation voltage-controlled oscillator |
| CN103021453A (en) * | 2012-12-31 | 2013-04-03 | 清华大学 | Dynamic random access memory cell with power leakage compensation |
| CN106169933A (en) * | 2015-05-21 | 2016-11-30 | 意法半导体国际有限公司 | Charge pump circuit used for a phase-locked loop |
| CN107769545A (en) * | 2017-11-09 | 2018-03-06 | 上海华力微电子有限公司 | A kind of charge pump circuit for being used for capacitor electric leakage compensation in PLL |
| CN109194119A (en) * | 2018-09-14 | 2019-01-11 | 京微齐力(北京)科技有限公司 | A kind of electric leakage compensation charge pump circuit of differential configuration |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5659588A (en) * | 1996-08-15 | 1997-08-19 | Lsi Logic Corporation | Phase-locked loop having filter leakage cancellation circuit |
| CN1549451A (en) * | 2003-05-17 | 2004-11-24 | 盛群半导体股份有限公司 | Fast frequency locking method and structure for realizing adaptive asymmetric electric charge pump current mechanism |
| US7132896B2 (en) * | 2004-11-04 | 2006-11-07 | International Business Machines Corporation | Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs) |
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| CN102571082A (en) * | 2012-03-22 | 2012-07-11 | 秉亮科技（苏州）有限公司 | Phase-locked loop for gate leakage current of V2I tube in dynamic compensation voltage-controlled oscillator |
| CN102571082B (en) * | 2012-03-22 | 2014-09-03 | 秉亮科技（苏州）有限公司 | Phase-locked loop for gate leakage current of V2I tube in dynamic compensation voltage-controlled oscillator |
| CN103021453A (en) * | 2012-12-31 | 2013-04-03 | 清华大学 | Dynamic random access memory cell with power leakage compensation |
| CN106169933A (en) * | 2015-05-21 | 2016-11-30 | 意法半导体国际有限公司 | Charge pump circuit used for a phase-locked loop |
| CN106169933B (en) * | 2015-05-21 | 2019-06-07 | 意法半导体国际有限公司 | Charge pump circuit used for a phase-locked loop |
| CN107769545A (en) * | 2017-11-09 | 2018-03-06 | 上海华力微电子有限公司 | A kind of charge pump circuit for being used for capacitor electric leakage compensation in PLL |
| CN109194119A (en) * | 2018-09-14 | 2019-01-11 | 京微齐力(北京)科技有限公司 | A kind of electric leakage compensation charge pump circuit of differential configuration |
| CN110798063A (en) * | 2018-11-22 | 2020-02-14 | 武汉新芯集成电路制造有限公司 | Charge pump system, control circuit and digital control method thereof |
| CN112087228A (en) * | 2019-06-13 | 2020-12-15 | 无锡有容微电子有限公司 | Phase-locked loop circuit |
| CN112087228B (en) * | 2019-06-13 | 2024-05-03 | 无锡有容微电子有限公司 | Phase-locked loop circuit |
| CN111510130A (en) * | 2020-05-15 | 2020-08-07 | 电子科技大学 | Phase-locked loop circuit capable of being used for synchronizing switching frequency of COT mode switching power supply |
| CN111510130B (en) * | 2020-05-15 | 2023-03-03 | 电子科技大学 | Phase-locked loop circuit capable of being used for synchronizing switching frequency of COT mode switching power supply |
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