CN102710242B - On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) - Google Patents
On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) Download PDFInfo
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Abstract
The invention provides an on-chip power-on reset detection circuit applied to but not limited in a high-frequency phase locked loop (PLL). When power voltage is not raised to a set value, the output of the power-on reset detection circuit is of low level all the time; and when the power voltage is raised to the set value, the output is high level signals, so that the circuit works normally. When the power voltage reaches a normal voltage value, the low level is output, and a power-on reset pulse signal is provided, so that power-on reset detection is realized. The circuit is easy to implement and low in static power consumption. A new solution is provided for avoiding a convenient point of a high-frequency circuit with power voltage power-on sensitivity.
Description
Technical field
The invention belongs to technical field of integrated circuits, specific design reset testing circuit, be particularly useful for electrification reset testing circuit in the sheet in high frequency PLL circuit.
Background technology
In sheet, electrification reset testing circuit is highly suitable for the mixed signal chip of CMOS technology.When powering up chip system, due to capacitive reasons on plate, the supply voltage in chip can slowly rise to normal working voltage from zero.But for arbitrary metal-oxide-semiconductor of the cmos device in chip, work and only need the voltage exceeding pipe threshold value, if supply voltage does not rise to the normal working voltage of chip system requirement, just make circuit start working to be easy to cause the error of digital circuit or memory cell, cause system cloud gray model mistake; For high frequency PLL circuit, if in power up, charge pump carries out discharge and recharge because phase frequency detector produces wrong output signal to electric capacity can be set to a fixed potential by voltage controlled oscillator control voltage signal, be easy to like this cause whole cycle of phase-locked loop losing lock, or annular oscillation circuit is under some PVT condition, in power up, enter low frequency degeneracy point, and produce loop deadlock, cannot normal clock be produced.So it is quite important for chip to study electrification reset testing circuit in a kind of new sheet.
Summary of the invention
The present invention, for solving the problems of the technologies described above, proposes a kind of being applicable to but electrification reset testing circuit in the sheet being not limited to high frequency PLL.Electrification reset testing circuit is not when supply voltage is elevated to set point, and export is low level always; When supply voltage is elevated to set point, exports and be set to high level signal, make circuit start normal work.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal.Open Enable Pin by power-on reset pulse signal, allow phase-locked loop in chip start working.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal, thus achieves electrification reset detection.Have and be easy to realize, the feature that quiescent dissipation is low.For the easy point of responsive high-frequency circuit of avoiding powering on to supply voltage, provide new solution.
The technical solution adopted for the present invention to solve the technical problems is: propose a kind of being applicable to but electrification reset testing circuit in the sheet being not limited to high frequency PLL, it is characterized in that: comprise power-up time delay circuit and electrification reset testing circuit, electrification reset testing circuit is not when supply voltage is elevated to set point, export is low level always, when supply voltage is elevated to set point, output is set to high level signal, circuit is made to start normal work, when supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal.Electrification reset testing circuit is not when supply voltage is elevated to set point, and export is low level always; When supply voltage is elevated to set point, exports and be set to high level signal, make circuit start normal work.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal.Open Enable Pin by power-on reset pulse signal, allow phase-locked loop in chip start working.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal, thus achieves electrification reset detection.Have and be easy to realize, the feature that quiescent dissipation is low.For the easy point of responsive high-frequency circuit of avoiding powering on to supply voltage.
It is also when sheet external power starts to power on, in sheet, power vd D+ with VDD-is charged by identical pin pin simultaneously, produce different two voltage IN+ and IN-of power-up speeds through power-up time delay circuit, IN+, IN-current potential is different can produce crosspoint due to power-up speeds difference.
It is also to adopt resistance, electric capacity and PMOS composition delay circuit, adds PMOS and strengthens delayed, can reduce resistance and capacitance under equal time delay condition.
It is also the mode adopting multi-stage cascade, uses small size resistance capacitance value to realize the delay effect of large resistance capacitance.
At the end of it is also to power on, IN-voltage is fixed as one lower than supply voltage value, and IN+ voltage is fixed as supply voltage.
It is also when IN-current potential is higher than IN+ current potential, and POR_OUT exports as low level; When IN+ current potential is higher than IN-current potential, POR_OUT exports as high level; When after voltage charging complete in sheet, IN+ current potential equals supply voltage in sheet, and POR_OUT exports as low level, completes electrification reset and detects.
It is also to adopt small area analysis comparator, inverter, single-ended common-source stage amplifier composition electrification reset testing circuit, and at the end of powering on, circuit is in low power consumpting state.
It is also along with the change in voltage that powers on, and comparator input pipe is in different conducting states, electro-detection reset effect in realization.
It is also that due at different temperatures, voltage and manufacture the deviation produced, the time delay that power-up time delay circuit produces can be different, but due to the gain of comparator enough large, electrification reset testing circuit still can realize electro-detection and reset function.
Compared with prior art, the present invention has following beneficial effect:
(1) use high-gain comparator, ensure chip power on do not reach requirement voltage time, output signal zero setting always.
(2) the electrification reset testing circuit used can by arranging the different service area of input pipe, and output level zero setting after realizing powering on completely, quiescent dissipation is very little.
(3) the easy point for the responsive high-frequency circuit that powers on to supply voltage is avoided, and provides new solution.
Accompanying drawing explanation
Fig. 1 is power-up time delay circuit schematic diagram of the present invention.
Fig. 2 is electrification reset testing circuit schematic diagram of the present invention.
Fig. 3 be use the present invention application a kind of high frequency PLL sheet in electrification reset testing circuit structural schematic block diagram.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further described.
Be applicable to but electrification reset testing circuit in the sheet being not limited to high frequency PLL, it is characterized in that: comprise power-up time delay circuit and electrification reset testing circuit, electrification reset testing circuit is not when supply voltage is elevated to set point, export is low level always, when supply voltage is elevated to set point, exports and is set to high level signal, circuit is made to start normal work, when supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal.Electrification reset testing circuit is not when supply voltage is elevated to set point, and export is low level always; When supply voltage is elevated to set point, exports and be set to high level signal, make circuit start normal work.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal.Open Enable Pin by power-on reset pulse signal, allow phase-locked loop in chip start working.When supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal, thus achieves electrification reset detection.
It is also when sheet external power starts to power on, in sheet, power vd D+ with VDD-is charged by identical pin pin simultaneously, produce different two voltage IN+ and IN-of power-up speeds through power-up time delay circuit, IN+, IN-current potential is different can produce crosspoint due to power-up speeds difference.
It is also to adopt resistance, electric capacity and PMOS composition delay circuit, adds PMOS and strengthens delayed, can reduce resistance and capacitance under equal time delay condition.
It is also the mode adopting multi-stage cascade, uses small size resistance capacitance value to realize the delay effect of large resistance capacitance.
At the end of it is also to power on, IN-voltage is fixed as one lower than supply voltage value, and IN+ voltage is fixed as supply voltage.
It is also when IN-current potential is higher than IN+ current potential, and POR_OUT exports as low level; When IN+ current potential is higher than IN-current potential, POR_OUT exports as high level; When after voltage charging complete in sheet, IN+ current potential equals supply voltage in sheet, and POR_OUT exports as low level, completes electrification reset and detects.
It is also to adopt small area analysis comparator, inverter, single-ended common-source stage amplifier composition electrification reset testing circuit, and at the end of powering on, circuit is in low power consumpting state.
It is also along with the change in voltage that powers on, and comparator input pipe is in different conducting states, electro-detection reset effect in realization.
It is also that due at different temperatures, voltage and manufacture the deviation produced, the time delay that power-up time delay circuit produces can be different, but due to the gain of comparator enough large, electrification reset testing circuit still can realize electro-detection and reset function.
Fig. 1 is power-up time delay circuit schematic diagram of the present invention, as shown in Figure 1: comprise PMOS M1, M2, resistance R1, R2, R3, R4, electric capacity C1, C2, electrification reset testing circuit, the wherein forward end of the source electrode connecting resistance R3 of M1, the forward end of electric capacity C2, the negative end of resistance R4, the grid of M2, the negative end of grid connecting resistance R3, the forward end resistance of electric capacity C1 produces the grid of IN+ voltage and M7, the grid of M9 is connected, the negative end of drain electrode and electric capacity C1, the negative end of resistance R2, the negative end of electric capacity C2, the drain electrode common ground of M2, the source electrode of M2 and the forward end of resistance R1, the forward end of resistance R4 connects power supply jointly, the negative end of R1, the forward end of resistance R2 is connected and produces IN-voltage and is connected with the grid of M8, Fig. 2 is electrification reset testing circuit schematic diagram of the present invention, as shown in Figure 2: comprise NMOS tube M7, M8, M9, M11, M12, PMOS M3, M4, M5, M6, M10, resistance R5.The wherein source electrode of M3, the source electrode of M4, the source electrode of M10, the forward end of R5 connects power supply jointly, the source electrode of M9, the source electrode of M11, the source electrode common ground of M12, the grid of M3, drain electrode is connected with the source electrode of M5, the grid of M4, drain electrode is connected with the source electrode of M6, the grid of M5 and the drain electrode of M6, the drain electrode of M8, the grid of M10, the grid of M11 is connected, the grid of M6 and the drain electrode of M5, the drain electrode of M7 is connected, the source electrode of M7 and the source electrode of M8, the drain electrode of M9 is connected, the drain electrode of M10 and the drain electrode of M11, the grid of M12 is connected, the drain electrode of M12 is connected to produce with the negative end of R5 and exports POR_OUT,
Wherein: PMOS M1 shown in Fig. 1, M2, resistance R3, R4, electric capacity C1, C2 form power-up time delay circuit, when sheet external power starts to power on, in sheet, power vd D+ with VDD-is charged by identical pin pin simultaneously, produces power-up speeds different two voltages IN+, IN-through power-up time delay circuit; IN+, IN-current potential is different can produce crosspoint due to power-up speeds difference.
NMOS tube M7 shown in Fig. 2, M8, M9, M11, M12, PMOS M3, M4, M5, M6, M10, resistance R5 forms electrification reset testing circuit.When IN-current potential is higher than IN+ current potential, POR_OUT exports as low level; When IN+ current potential is higher than IN-current potential, POR_OUT exports as high level; When after voltage charging complete in sheet, IN+ current potential equals supply voltage in sheet, and POR_OUT exports as low level.Complete electrification reset to detect.
As shown in Figure 1, PMOS M1, M2, resistance R3, R4, electric capacity C1, C2 form power-up time delay circuit, and when sheet external power starts to power on, in sheet, power vd D+ with VDD-is charged by identical pin pin simultaneously.Because power supply in chip is very low, VDD-does not have electric current to be in electronegative potential conducting always by the grid of resistance R4, M2, VDD-forms path with ground, to make in sheet power supply electrifying speed lower than VDD+, along with supply voltage continues to raise, A point current potential is close to VDD-voltage, because A point current potential is very low, do not have electric current to be in electronegative potential conducting always by the grid of resistance R3, M1, A point forms path with ground, A point power-up speeds is reduced, and IN+ point is equivalent to VDD-by time delay electrifying condition.By the IN-of the direct dividing potential drop of resistance, because do not have the relation of time delay, power-up speeds is identical with VDD+, but most combined potential is lower than IN+ point.
NMOS tube M7, M8, M9, M11, M12 as shown in Figure 2, PMOS M3, M4, M5, M6, M10, resistance R5 forms electrification reset testing circuit.Wherein PMOS M3, M4, M5, M6, NMOS tube M7, M8, M9 form comparator, M5, M6 cross-couplings, form cascodes load respectively with M3, M4.M5 grid drains with M6, the drain electrode of M8 is connected, and as exporting the inverter being given to M10, M11 composition, inverter exports and connects the single-ended common-source stage amplifier be made up of M12 and R5, exports electrification reset detection signal.
IN+ and the IN-power-up speeds one fast one produced by power-up time delay circuit is slow, and final level is one high and one low.When IN-current potential is higher than IN+ current potential, supply voltage is given to the drain electrode of NMOS tube M7, M8 after PMOS M3, M5 and PMOS M4, M6 dividing potential drop, and be greater than IN+ and IN-, now NMOS tube M7, M8 are in saturation region, due to PMOS M5, M6 cross-couplings, the voltage of IN-and IN+ are done difference and compare, it is zero that comparator is exported, inverter exports and sets high, the Current amplifier that voltage difference produces by common-source stage amplifier, and POR_OUT exports as low level.
When IN+ current potential is higher than IN-current potential, now supply voltage is given to the drain voltage of NMOS tube M7, M8 after PMOS M3, M5 and PMOS M4, M6 dividing potential drop, still be greater than IN+ and IN-, now NMOS tube M7, M8 keep saturation region, by PMOS M5, M6 cross-couplings, the voltage of IN-and IN+ is done difference to compare, it is one that comparator is exported, and inverter exports zero setting, the Current amplifier that voltage difference produces by common-source stage amplifier, POR_OUT exports as high level, now completes electro-detection.
When after voltage charging complete in sheet, IN+ current potential is equal to supply voltage in sheet, now supply voltage is given to the drain voltage of NMOS tube M7, M8 after PMOS M3, M5 and PMOS M4, M6 dividing potential drop, be less than IN+ voltage, be greater than IN-voltage, now NMOS tube M7, M9 are in linear zone, NMOS tube M8 is in saturation region, because IN+ is far longer than IN-, differential pair electric current is put a little over the ground by NMOS tube M7, M9 completely, and now comparator circuit can regard single inverter circuit as.Because what be less than M7 and M9 as the PMOS M3 of load pipe, M4, M5, M6 charging current puts an electric current, it is zero that comparator is exported, and inverter exports and is set to high level, the Current amplifier that voltage difference produces by common-source stage amplifier, POR_OUT exports as low level, completes electrification reset and detects.By emulation can design comparison device quiescent point electric current be lower value, after electrification reset testing circuit completes reset, the quiescent dissipation of integrated circuit can be very little, realizes low power dissipation design.
Due at different temperatures, voltage and manufacture the deviation produced, the time delay that power-up time delay circuit produces can be different, but due to the gain of comparator enough large, electrification reset testing circuit still can realize electro-detection and reset function.If the temperature drift of technique is larger, can suitably power-up time delay circuit time delay be strengthened.
Fig. 3 be use the present invention application a kind of high frequency PLL sheet in electrification reset testing circuit structural schematic block diagram, as shown in Figure 3, electrification reset testing circuit is not when supply voltage is elevated to set point, export is low level always, when supply voltage is elevated to set point, output is set to high level signal, circuit is made to start normal work, when supply voltage reaches normal voltage value, output low level, provide a power-on reset pulse signal, electrification reset testing circuit is not when supply voltage is elevated to set point, and export is low level always; When supply voltage is elevated to set point, output is set to high level signal, makes circuit start normal work, when supply voltage reaches normal voltage value, output low level, provide a power-on reset pulse signal, open Enable Pin by power-on reset pulse signal, allow phase-locked loop in chip start working, when supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal, thus achieves electrification reset detection.
Claims (8)
1. electrification reset testing circuit in the sheet being applied to high frequency PLL, it is characterized in that: comprise power-up time delay circuit and electrification reset testing circuit, electrification reset testing circuit is not when supply voltage is elevated to set point, export is low level always, and when supply voltage is elevated to set point, output valve is high level signal, circuit is made to start normal work, when supply voltage reaches normal voltage value, output low level, provides a power-on reset pulse signal, power-on reset pulse signal opens Enable Pin, allows phase-locked loop in chip start working, PMOS M1, M2, resistance R3, R4, electric capacity C1, C2 forms power-up time delay circuit, the wherein forward end of the source electrode connecting resistance R3 of M1, the forward end of electric capacity C2, the negative end of resistance R4, the grid of M2, the negative end of grid connecting resistance R3, the forward end resistance of electric capacity C1 produces the grid of IN+ voltage and M7, the grid of M9 is connected, the negative end of drain electrode and electric capacity C1, the negative end of resistance R2, the negative end of electric capacity C2, the drain electrode common ground of M2, the source electrode of M2 and the forward end of resistance R1, the forward end of resistance R4 connects power supply jointly, the negative end of R1, the forward end of resistance R2 is connected and produces IN-voltage and is connected with the grid of M8, when sheet external power starts to power on, in sheet, power vd D+ with VDD-is charged by identical pin pin simultaneously, two different voltage IN+ of power-up speeds are produced through power-up time delay circuit, IN-, IN+, IN-current potential is different can produce crosspoint due to power-up speeds difference, NMOS tube M7, M8, M9, M11, M12, PMOS M3, M4, M5, M6, M10, resistance R5 forms electrification reset testing circuit, the wherein source electrode of M3, the source electrode of M4, the source electrode of M10, the forward end of R5 connects power supply jointly, the source electrode of M9, the source electrode of M11, the source electrode common ground of M12, the grid of M3, drain electrode is connected with the source electrode of M5, the grid of M4, drain electrode is connected with the source electrode of M6, the grid of M5 and the drain electrode of M6, the drain electrode of M8, the grid of M10, the grid of M11 is connected, the grid of M6 and the drain electrode of M5, the drain electrode of M7 is connected, the source electrode of M7 and the source electrode of M8, the drain electrode of M9 is connected, the drain electrode of M10 and the drain electrode of M11, the grid of M12 is connected, the drain electrode of M12 is connected to produce with the negative end of R5 and exports POR_OUT, when IN-current potential is higher than IN+ current potential, POR_OUT exports as low level, when IN+ current potential is higher than IN-current potential, POR_OUT exports as high level, when after voltage charging complete in sheet, IN+ current potential equals supply voltage in sheet, and POR_OUT exports as low level, complete electrification reset to detect.
2. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 1, is characterized in that: add PMOS and strengthen delayed, at equal time delay condition decline low resistance and capacitance.
3. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 1, is characterized in that: the mode adopting multi-stage cascade, uses small size resistance capacitance value to realize the delay effect of large resistance capacitance.
4. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 1, is characterized in that: at the end of powering on, and IN-voltage is fixed as one lower than supply voltage value, and IN+ voltage is fixed as supply voltage.
5. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 1, it is characterized in that: electrification reset testing circuit adopts the small area analysis comparator be made up of PMOS M3, M4, M5, M6 and NMOS tube M7, M8, M9, the inverter be made up of PMOS M10 and NMOS tube M11 and the single-ended common-source stage amplifier that is made up of NMOS tube M12 and resistance R5 to form electrification reset testing circuit, and at the end of powering on, reset testing circuit is in low power consumpting state on the whole.
6. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 5, it is characterized in that: along with the change in voltage that powers on, comparator input pipe is in different conducting states, electro-detection reset effect in realization.
7. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 5, is characterized in that: at different temperatures, voltage and when manufacturing the deviation produced, the time delay that power-up time delay circuit produces is different.
8. electrification reset testing circuit in the sheet being applied to high frequency PLL according to claim 6 or 7, is characterized in that: the gain of comparator makes electrification reset testing circuit realize upper electro-detection and reset function.
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| CN201210198754.3A CN102710242B (en) | 2012-06-17 | 2012-06-17 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
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| CN201210198754.3A CN102710242B (en) | 2012-06-17 | 2012-06-17 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
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| CN105675955B (en) * | 2016-01-21 | 2018-08-10 | 中山芯达电子科技有限公司 | A kind of zero-power voltage detecting circuit |
| CN112204884B (en) * | 2018-05-31 | 2024-04-26 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7636019B1 (en) * | 2005-06-07 | 2009-12-22 | Cypress Semiconductor Corporation | Phase lock loop pre-charging system and method |
| CN100583633C (en) * | 2006-09-29 | 2010-01-20 | 联发科技股份有限公司 | Power-on reset circuits |
| CN101860353A (en) * | 2010-06-17 | 2010-10-13 | 广州市广晟微电子有限公司 | Clock circuit control device in digital-analog mixed chip and method thereof |
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| CN1980064B (en) * | 2005-11-29 | 2010-10-06 | 中芯国际集成电路制造(上海)有限公司 | Cock-phase-ring indicator |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7636019B1 (en) * | 2005-06-07 | 2009-12-22 | Cypress Semiconductor Corporation | Phase lock loop pre-charging system and method |
| CN100583633C (en) * | 2006-09-29 | 2010-01-20 | 联发科技股份有限公司 | Power-on reset circuits |
| CN101860353A (en) * | 2010-06-17 | 2010-10-13 | 广州市广晟微电子有限公司 | Clock circuit control device in digital-analog mixed chip and method thereof |
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Address after: 410000 Hunan province Changsha municipal environmental protection science and Technology Industrial Park in Yuhua District Business Center 3 floor Patentee after: HUNAN HKT TECHNOLOGY CO., LTD. Address before: 410000 Hunan province Changsha municipal environmental protection science and Technology Industrial Park in Yuhua District Business Center 3 floor Patentee before: Hunan Huakuantong Electronic Technology Co.,Ltd. |