CN112087228A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
- Publication number
- CN112087228A CN112087228A CN201910510846.2A CN201910510846A CN112087228A CN 112087228 A CN112087228 A CN 112087228A CN 201910510846 A CN201910510846 A CN 201910510846A CN 112087228 A CN112087228 A CN 112087228A
- Authority
- CN
- China
- Prior art keywords
- signal
- phase
- capacitor
- voltage
- outputting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 73
- 238000001514 detection method Methods 0.000 claims abstract description 30
- 230000001105 regulatory effect Effects 0.000 claims abstract description 12
- 230000010355 oscillation Effects 0.000 claims abstract description 9
- 238000001914 filtration Methods 0.000 claims description 21
- 238000009825 accumulation Methods 0.000 claims description 15
- 238000004364 calculation method Methods 0.000 claims description 9
- 238000001228 spectrum Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Abstract
The application discloses a phase-locked loop circuit, which comprises a main loop and a negative feedback compensation branch; the main loop includes: the phase frequency detector is used for detecting the phase difference between a reference signal and an input signal and outputting a corresponding detection result signal; the charge pump is connected with the phase frequency detector; a first filter coupled to the charge pump; the voltage-controlled oscillator is connected with the first filter and used for generating and outputting an oscillation signal corresponding to the locking voltage; the voltage regulating circuit is connected with the voltage controlled oscillator and is used for generating and outputting a voltage-regulated input signal to the phase frequency detector; the input end of the negative feedback compensation branch is connected with the phase frequency detector, and the output end of the negative feedback compensation branch is connected with the MOS tube capacitor in the first filter, so that the compensation current corresponding to the detection result signal is generated and output, and the leakage compensation is performed on the MOS tube capacitor. The application introduces the negative feedback compensation branch circuit, provides compensation current for MOS tube capacitance, can eliminate reference clock burrs in the output frequency spectrum, and improves the output accuracy.
Description
Technical Field
The application relates to the technical field of circuit design, in particular to a phase-locked loop circuit.
Background
An analog phase-locked loop (PLL) circuit has the advantages of simple circuit, high performance, stability, and the like, and is widely applied to modern wired communication systems. Referring to fig. 1, a PLL in the prior art mainly includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a filter (loop filter), a voltage-controlled oscillator (VCO), and a frequency divider (divider). Usually, in order to reduce the area, most designers replace the capacitor with an NMOS transistor when designing the filter. In the deep submicron process, because the gate oxide is very thin, leakage exists, and the leakage can cause serious reference clock glitch of the output frequency spectrum of the PLL and influence the output precision. In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.
Disclosure of Invention
An object of the present application is to provide a phase-locked loop circuit to effectively eliminate a reference clock glitch in an output spectrum of the phase-locked loop circuit, thereby improving output accuracy.
In order to solve the above technical problem, in a first aspect, the present application discloses a phase-locked loop circuit, including a main loop and a negative feedback compensation branch; the main loop includes:
the phase frequency detector is used for detecting the phase difference between a reference signal and an input signal and outputting a corresponding detection result signal;
the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal;
a first filter connected to the charge pump for filtering the voltage signal to output a locking voltage;
the voltage-controlled oscillator is connected with the first filter and used for generating and outputting an oscillating signal corresponding to the locking voltage;
the voltage regulating circuit is connected with the voltage controlled oscillator and is used for regulating the amplitude of the oscillation signal, generating and outputting the input signal to the phase frequency detector;
the input end of the negative feedback compensation branch circuit is connected with the phase frequency detector, and the output end of the negative feedback compensation branch circuit is connected with the MOS tube capacitor in the first filter, and is used for generating and outputting a compensation current corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor.
Optionally, a bandwidth of the negative feedback compensation branch is smaller than a bandwidth of the main loop.
Optionally, the negative feedback compensation branch comprises:
the bang-bang phase detector with an input end connected with the phase frequency detector is used for generating and outputting a sign signal corresponding to the detection result signal;
the accumulator is connected with the bang-bang phase discriminator and used for performing accumulation calculation according to the sign signal and outputting a digital accumulation signal;
the digital-to-analog converter is connected with the accumulator and used for converting the digital accumulation signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the digital-to-analog converter and used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
Optionally, the accumulator is specifically configured to:
when the symbol signal is at a low level, performing accumulation calculation of stepping plus 1; when the sign signal is high, an accumulation calculation of stepping minus 1 is performed.
Optionally, the negative feedback compensation branch further comprises:
a second filter connected between the digital-to-analog converter and the voltage-to-current converter.
Optionally, the second filter includes several filtering units connected in series; each filtering unit comprises a first resistor and a first capacitor;
a first end of the first resistor is used as an input end of the filtering unit; the second end of the first resistor is connected with the first end of the first capacitor and serves as the output end of the filtering unit; the second end of the first capacitor is grounded.
Optionally, the negative feedback compensation branch comprises:
the time-to-digital converter with an input end connected with the phase frequency detector is used for generating and outputting a digital signal corresponding to the detection result signal;
the sigma-delta digital-to-analog converter is connected with the time digital converter and is used for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the sigma-delta digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
Optionally, the first filter comprises a second capacitor, a third capacitor and a second resistor;
the first end of the second capacitor is connected with the first end of the second resistor, and is connected with the output end of the charge pump and the input end of the voltage-controlled oscillator; the second end of the second resistor is connected with the first end of the third capacitor; and the second end of the second capacitor and the second end of the third capacitor are both grounded.
Optionally, a ratio of the capacitance value of the third capacitor to the capacitance value of the second capacitor is 10: 1.
Optionally, the third capacitor is the MOS transistor capacitor, and a gate of the third capacitor is connected to the second end of the second resistor and the output end of the negative feedback compensation branch.
The phase-locked loop circuit provided by the application comprises a main loop and a negative feedback compensation branch; the main loop includes: the phase frequency detector is used for detecting the phase difference between a reference signal and an input signal and outputting a corresponding detection result signal; the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal; a first filter connected to the charge pump for filtering the voltage signal to output a locking voltage; the voltage-controlled oscillator is connected with the first filter and used for generating and outputting an oscillation signal corresponding to the locking voltage; the voltage regulating circuit is connected with the voltage controlled oscillator and is used for regulating the amplitude of the oscillation signal, generating and outputting the input signal to the phase frequency detector; the input end of the negative feedback compensation branch circuit is connected with the phase frequency detector, and the output end of the negative feedback compensation branch circuit is connected with the MOS tube capacitor in the first filter, and is used for generating and outputting a compensation current corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor.
Therefore, the phase-locked loop circuit disclosed by the embodiment of the application introduces the negative feedback compensation branch circuit on the basis of the main loop circuit to provide the compensation current for the MOS tube capacitor in the main loop circuit, so that the leakage problem of the MOS tube capacitor is solved, the reference clock burr in the output frequency spectrum of the phase-locked loop circuit is eliminated, and the output accuracy of the phase-locked loop circuit is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a circuit configuration diagram of a phase-locked loop circuit in the prior art;
fig. 2 is a circuit diagram of a phase-locked loop circuit according to an embodiment of the present disclosure;
FIG. 3 is a signal timing diagram of a leakage-free PLL circuit according to an embodiment of the present disclosure;
FIG. 4 is a timing diagram of a leakage PLL circuit according to an embodiment of the present disclosure;
fig. 5 is a circuit diagram of a specific pll circuit according to an embodiment of the present disclosure;
fig. 6 is a circuit diagram of another specific pll circuit according to an embodiment of the present disclosure;
fig. 7 is a diagram of simulation results of a phase-locked loop circuit according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a phase-locked loop circuit so as to effectively eliminate reference clock glitches in an output frequency spectrum of the phase-locked loop circuit, and therefore output accuracy is improved.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Currently, in a phase-locked loop circuit, an NMOS transistor is generally used as a capacitor. However, in the deep submicron process, the gate oxide is very thin, so that a leakage phenomenon exists, and further, the output frequency spectrum of the phase-locked loop circuit has serious reference clock burrs, and the output precision is influenced. In view of the above, the present application provides a phase-locked loop circuit, which can effectively solve the above problems.
Referring to fig. 2, the embodiment of the present application discloses a circuit structure of a phase-locked loop circuit, which mainly includes a main loop and a negative feedback compensation branch 20; the main loop includes:
the phase frequency detector 101 is configured to detect a phase difference between a reference signal ref and an input signal div, and output a corresponding detection result signal;
a charge pump 102 connected to the phase frequency detector 101, for generating and outputting a voltage signal corresponding to the detection result signal;
a first filter 103 connected to the charge pump 102 for filtering the voltage signal to output a locking voltage vti;
a voltage-controlled oscillator 104 connected to the first filter 103, for generating and outputting an oscillation signal corresponding to the lock voltage vti;
the voltage regulating circuit 105 is connected with the voltage controlled oscillator 104 and is used for regulating the amplitude of the oscillation signal, generating and outputting an input signal div to the phase frequency detector 101;
the input end of the negative feedback compensation branch 20 is connected to the phase frequency detector 101, and the output end of the negative feedback compensation branch 20 is connected to the MOS capacitor in the first filter 103, and is configured to generate and output a compensation current Icomp corresponding to the detection result signal, so as to perform leakage compensation on the MOS capacitor.
The detection result signal output by the phase frequency detector 101 includes a first detection result signal up and a second detection result signal dn.
It is noted that, in order to reduce the area, generally, the first filter 103 is implemented based on MOS device devices in many cases. As a specific embodiment, the first filter 103 includes a second capacitor C2, a third capacitor C3, and a second resistor R2;
a first end of the second capacitor C2 is connected to a first end of the second resistor R2, and is connected to an output end of the charge pump 102 and an input end of the voltage-controlled oscillator 104; a second end of the second resistor R2 is connected with a first end of the third capacitor C3; the second terminal of the second capacitor C2 and the second terminal of the third capacitor C3 are both grounded.
Further, the capacitance ratio of the third capacitor C3 to the second capacitor C2 may be 10: 1. Therefore, in order to save chip area, the third capacitor C3 may be embodied as a MOS transistor capacitor implemented by a MOS transistor. Therefore, the gate of the MOS transistor can be used as one end of the third capacitor C3, is connected to the second end of the second resistor R2, and is connected to the output end of the negative feedback compensation branch 20; the drain and the source of the MOS transistor may be connected to each other, and serve as the second terminal of the third capacitor C3 to be grounded.
However, in the deep submicron process, since the gate oxide is very thin, the MOS transistor may have leakage, which may cause serious reference clock glitch in the output spectrum of the phase-locked loop circuit, as shown in fig. 3 and 4. Fig. 3 is a signal timing diagram of a leakage-free pll circuit disclosed in an embodiment of the present application; fig. 4 is a signal timing diagram of a leaky pll circuit according to an embodiment of the disclosure.
As can be seen from fig. 3, under normal conditions without leakage, the locking voltage vti will remain stable. As can be seen from fig. 4, when there is a leakage phenomenon, the first detection result signal up output by the phase frequency detector 101 will have a pulse signal with a time Δ t added to compensate for the leakage, which will cause the locking voltage vti to have a triangular spike.
Therefore, the phase-locked loop circuit provided by the embodiment of the present application is further provided with a negative feedback compensation branch 20 on the basis of the main loop, and is configured to generate the compensation current Icomp, and input the compensation current Icomp to the first filter 103, so as to perform leakage compensation on the MOS transistor in the first filter 103, thereby avoiding spike glitch of the locking voltage vti of the phase-locked loop. The compensation current Icomp specifically corresponds to a detection result signal output by the phase frequency detector 101, and specifically, the compensation branch should be a negative feedback compensation branch 20, so as to suppress the spike and glitch phenomenon through negative feedback closed-loop control.
It is worth mentioning that the introduction of the negative feedback compensation branch 20 should avoid the influence on the bandwidth performance of the main loop, and prevent the compensation loop where the two compensation branches are located from interfering with the main loop. Therefore, further, the bandwidth of the negative feedback compensation branch 20 needs to be much smaller than the bandwidth of the main loop.
The phase-locked loop circuit disclosed by the embodiment of the application comprises a main loop and a negative feedback compensation branch circuit 20; the main loop includes: the phase frequency detector 101 is configured to detect a phase difference between a reference signal ref and an input signal div, and output a corresponding detection result signal; a charge pump 102 connected to the phase frequency detector 101, for generating and outputting a voltage signal corresponding to the detection result signal; a first filter 103 connected to the charge pump 102 for filtering the voltage signal to output a locking voltage vti; a voltage-controlled oscillator 104 connected to the first filter 103, for generating and outputting an oscillation signal corresponding to the lock voltage vti; the voltage regulating circuit 105 is connected with the voltage controlled oscillator 104 and is used for regulating the amplitude of the oscillation signal, generating and outputting an input signal div to the phase frequency detector 101; the input end of the negative feedback compensation branch 20 is connected to the phase frequency detector 101, and the output end of the negative feedback compensation branch 20 is connected to the MOS capacitor in the first filter 103, and is configured to generate and output a compensation current Icomp corresponding to the detection result signal, so as to perform leakage compensation on the MOS capacitor.
Therefore, the phase-locked loop circuit disclosed by the embodiment of the application introduces the negative feedback compensation branch 20 on the basis of the main loop to provide the compensation current Icomp for the MOS tube capacitor in the main loop, so that the leakage problem of the MOS tube capacitor is solved, the reference clock glitch in the output frequency spectrum of the phase-locked loop circuit is eliminated, and the output accuracy of the phase-locked loop circuit is effectively improved.
Referring to fig. 5, the embodiment of the present application discloses a specific circuit structure of a phase-locked loop circuit.
In the phase-locked loop circuit provided in this embodiment, on the basis of the above contents, the negative feedback compensation branch 20 further includes:
a Bang-base Phase detector 201 (BB _ PD) having an input end connected to the Phase frequency detector 101, and configured to generate and output a sign signal corresponding to the detection result signal;
an accumulator 202(ACC) connected to the bang-bang phase detector 201, for performing an accumulation calculation according to the sign signal and outputting a digital accumulation signal;
a digital-to-analog converter 203(DAC) connected to the accumulator 202 for converting the digital accumulation signal into an analog voltage signal and outputting it;
a voltage-to-current converter 204(VtoI) connected to the digital-to-analog converter 203 for outputting the compensation current Icomp corresponding to the analog voltage signal to the MOS transistor capacitor in the first filter 103, and in particular, outputting the compensation current Icomp to the gate of the third capacitor C3. The leakage compensated gate voltage is lfv.
The bang-bang phase detector 201 is configured to detect a relative position between the first detection result signal up and the second detection result signal dn, and generate a sign signal. And the accumulator 202 is specifically configured to: when the symbol signal is at low level, namely 0, performing accumulation calculation of stepping plus 1; when the sign signal is at a high level, i.e., 1, an accumulation calculation of step by 1 is performed.
The high 7-bit output of the accumulator 202, i.e. AOUT <12:6>, is transmitted to the digital-to-analog converter 203, the digital-to-analog converter 203 converts the high 7-bit digital signal into an analog voltage signal, and the analog voltage signal is converted into a compensation current Icomp by the voltage-current converter 204 to compensate the gate leakage of the MOS capacitor in the first filter 103, thereby realizing the suppression of the spike glitch of the locking voltage vti.
In addition, on the basis of the above, the negative feedback compensation branch 20 may further include a second filter 205 connected between the digital-to-analog converter 203 and the voltage-to-current converter 204 for stabilizing the analog voltage signal output by the digital-to-analog converter 203.
Further, the second filter 205 may include several filtering units connected in series; each filtering unit comprises a first resistor R1 and a first capacitor C1; a first end of the first resistor R1 is used as an input end of the filtering unit; the second end of the first resistor R1 is connected with the first end of the first capacitor C1 and is used as the output end of the filtering unit; the second terminal of the first capacitor C1 is connected to ground.
In general, the number of the filter units may be specifically set to 2. Of course, other arrangements can be made by those skilled in the art according to the practical application, and the present application does not limit this.
Referring to fig. 6, the embodiment of the present application discloses another specific circuit structure of a phase-locked loop circuit.
In the phase-locked loop circuit provided in this embodiment, on the basis of the above contents, the negative feedback compensation branch 20 further includes:
a Time-to-Digital converter 201 (TDC) having an input end connected to the phase frequency detector 101, and configured to generate and output a Digital signal corresponding to the detection result signal;
a sigma-delta digital-to-analog converter 202 connected to the time-to-digital converter 201, for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
the voltage-current converter 203 is connected to the sigma-delta dac 202, and is configured to output the compensation current Icomp corresponding to the analog voltage signal to the MOS transistor capacitor in the first filter 103, specifically, to output the compensation current Icomp to the gate of the third capacitor C3. The leakage compensated gate voltage is lfv.
Further, on the basis of the above, the negative feedback compensation branch 20 may further include a second filter 204 connected between the sigma-delta digital-to-analog converter 202 and the voltage-to-current converter 203, for stabilizing the analog voltage signal output by the sigma-delta digital-to-analog converter 202.
Further, the second filter 204 may include several filtering units connected in series; each filtering unit comprises a first resistor R1 and a first capacitor C1; a first end of the first resistor R1 is used as an input end of the filtering unit; the second end of the first resistor R1 is connected with the first end of the first capacitor C1 and is used as the output end of the filtering unit; the second terminal of the first capacitor C1 is connected to ground.
The time-to-digital converter 201 can detect the time interval and directly output the digital signal result. In fact, the bang-bang phase detector 201 used in the negative feedback compensation branch 20 shown in fig. 5 can be regarded as a time-to-digital converter 201 with 1-bit output, and the time-to-digital converter 201 used in fig. 6 can perform multi-bit output setting, so that the quantization noise is smaller.
Sigma-delta dac 202 is a cost effective, high speed, high accuracy analog-to-digital converter, and is commonly used in wireless and audio applications. The present embodiment can further effectively reduce the circuit noise by using the high-speed sigma-delta dac 202, thereby improving the output accuracy.
For the parts not detailed in this embodiment, reference may be made to the related contents in the foregoing embodiments, and details are not repeated here.
Referring to fig. 7, fig. 7 is a diagram of a simulation result of a phase-locked loop circuit according to an embodiment of the present disclosure.
During the period of 0-32us, the negative feedback compensation branch 20 is not started, and a voltage difference exists between vti and lfv due to the leakage of the MOS transistor. The lines presented in fig. 7 are thicker due to the triangular signal glitch of the vti signal. After 32us, the negative feedback compensation branch 20 starts to start, the compensation current Icomp gradually approaches to the leakage current, so that the voltage difference between vti and lfv is smaller and smaller, when the compensation current Icomp is completely equal to the leakage current, vti is overlapped with lfv, after the circuit reaches a stable state, triangular wave burrs of the vti signal are eliminated, and the presented signal line becomes thin.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (10)
1. A phase-locked loop circuit, comprising a main loop and a negative feedback compensation branch; the main loop includes:
the phase frequency detector is used for detecting the phase difference between a reference signal and an input signal and outputting a corresponding detection result signal;
the charge pump is connected with the phase frequency detector and is used for generating and outputting a voltage signal corresponding to the detection result signal;
a first filter connected to the charge pump for filtering the voltage signal to output a locking voltage;
the voltage-controlled oscillator is connected with the first filter and used for generating and outputting an oscillating signal corresponding to the locking voltage;
the voltage regulating circuit is connected with the voltage controlled oscillator and is used for regulating the amplitude of the oscillation signal, generating and outputting the input signal to the phase frequency detector;
the input end of the negative feedback compensation branch circuit is connected with the phase frequency detector, and the output end of the negative feedback compensation branch circuit is connected with the MOS tube capacitor in the first filter, and is used for generating and outputting a compensation current corresponding to the detection result signal so as to perform leakage compensation on the MOS tube capacitor.
2. The phase-locked loop circuit of claim 1, wherein a bandwidth of the negative feedback compensation branch is less than a bandwidth of the main loop.
3. The phase-locked loop circuit of claim 2, wherein the negative feedback compensation branch comprises:
the bang-bang phase detector with an input end connected with the phase frequency detector is used for generating and outputting a sign signal corresponding to the detection result signal;
the accumulator is connected with the bang-bang phase discriminator and used for performing accumulation calculation according to the sign signal and outputting a digital accumulation signal;
the digital-to-analog converter is connected with the accumulator and used for converting the digital accumulation signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the digital-to-analog converter and used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
4. The phase-locked loop circuit of claim 3, wherein the accumulator is specifically configured to:
when the symbol signal is at a low level, performing accumulation calculation of stepping plus 1; when the sign signal is high, an accumulation calculation of stepping minus 1 is performed.
5. The phase-locked loop circuit of claim 4, wherein the negative feedback compensation branch further comprises:
a second filter connected between the digital-to-analog converter and the voltage-to-current converter.
6. The phase-locked loop circuit of claim 5, wherein the second filter comprises a plurality of filtering units connected in series; each filtering unit comprises a first resistor and a first capacitor;
a first end of the first resistor is used as an input end of the filtering unit; the second end of the first resistor is connected with the first end of the first capacitor and serves as the output end of the filtering unit; the second end of the first capacitor is grounded.
7. The phase-locked loop circuit of claim 2, wherein the negative feedback compensation branch comprises:
the time-to-digital converter with an input end connected with the phase frequency detector is used for generating and outputting a digital signal corresponding to the detection result signal;
the sigma-delta digital-to-analog converter is connected with the time digital converter and is used for converting the digital signal into an analog voltage signal and outputting the analog voltage signal;
and the voltage-current converter is connected with the sigma-delta digital-to-analog converter and is used for outputting compensation current corresponding to the analog voltage signal to the MOS tube capacitor in the first filter.
8. The phase-locked loop circuit of any of claims 1 through 7, wherein the first filter comprises a second capacitor, a third capacitor, and a second resistor;
the first end of the second capacitor is connected with the first end of the second resistor, and is connected with the output end of the charge pump and the input end of the voltage-controlled oscillator; the second end of the second resistor is connected with the first end of the third capacitor; and the second end of the second capacitor and the second end of the third capacitor are both grounded.
9. The phase-locked loop circuit of claim 8, wherein a ratio of a capacitance value of the third capacitor to a capacitance value of the second capacitor is 10: 1.
10. The phase-locked loop circuit of claim 9, wherein the third capacitor is the MOS transistor capacitor, and a gate of the third capacitor is connected to the second terminal of the second resistor and the output terminal of the negative feedback compensation branch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910510846.2A CN112087228A (en) | 2019-06-13 | 2019-06-13 | Phase-locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910510846.2A CN112087228A (en) | 2019-06-13 | 2019-06-13 | Phase-locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112087228A true CN112087228A (en) | 2020-12-15 |
Family
ID=73733665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910510846.2A Pending CN112087228A (en) | 2019-06-13 | 2019-06-13 | Phase-locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112087228A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115580297A (en) * | 2022-12-05 | 2023-01-06 | 成都芯矩阵科技有限公司 | Phase-locked loop circuit with extremely low jitter and phase-locked loop module |
| CN115800997A (en) * | 2023-01-31 | 2023-03-14 | 上海韬润半导体有限公司 | Brand-new sampling phase-locked loop circuit |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200402193A (en) * | 2002-07-19 | 2004-02-01 | Sun Microsystems Inc | Loop filter capacitor leakage current control |
| US20060267691A1 (en) * | 2005-05-25 | 2006-11-30 | Satoru Takase | System and method for phase-locked loop leak compensation |
| CN1956337A (en) * | 2005-10-24 | 2007-05-02 | 北京六合万通微电子技术有限公司 | Method and device for removing parasitic reference frequency in phaselocked loop frequency synthesizer |
| CN101025638A (en) * | 2007-03-20 | 2007-08-29 | 北京中星微电子有限公司 | Device and method for compensating MOS device grid leakage current |
| US20080008284A1 (en) * | 2006-07-10 | 2008-01-10 | Mediatek Inc. | Pll device with leakage current compensation unit |
| CN101578807A (en) * | 2007-01-09 | 2009-11-11 | 拉姆伯斯公司 | Receiver with clock recovery circuit and adaptive sample and equalizer timing |
| TW201004151A (en) * | 2008-07-01 | 2010-01-16 | Univ Nat Taiwan | Phase locked loop (PLL) with leakage current calibration |
| CN101931408A (en) * | 2004-12-13 | 2010-12-29 | 睦塞德技术公司 | Phase-locked loop circuitry using charge pumps with current mirror circuitry |
| CN101958709A (en) * | 2009-07-17 | 2011-01-26 | 瑞昱半导体股份有限公司 | Clock generating apparatus having low clock jitter and related method thereof |
| CN102006058A (en) * | 2009-08-31 | 2011-04-06 | 安凯(广州)微电子技术有限公司 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
| CN102291129A (en) * | 2011-06-01 | 2011-12-21 | 浙江大学 | Phase-locked loop circuit used for inhibiting VCO (voltage-controlled oscillator) voltage ripple |
| CN102571082A (en) * | 2012-03-22 | 2012-07-11 | 秉亮科技（苏州）有限公司 | Phase-locked loop for gate leakage current of V2I tube in dynamic compensation voltage-controlled oscillator |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of performing locking fast |
| CN107342738A (en) * | 2015-08-26 | 2017-11-10 | 深圳清华大学研究院 | Support the two-point modulator of High Data Rate |
| CN107769545A (en) * | 2017-11-09 | 2018-03-06 | 上海华力微电子有限公司 | A kind of charge pump circuit for being used for capacitor electric leakage compensation in PLL |
-
2019
- 2019-06-13 CN CN201910510846.2A patent/CN112087228A/en active Pending
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200402193A (en) * | 2002-07-19 | 2004-02-01 | Sun Microsystems Inc | Loop filter capacitor leakage current control |
| CN101931408A (en) * | 2004-12-13 | 2010-12-29 | 睦塞德技术公司 | Phase-locked loop circuitry using charge pumps with current mirror circuitry |
| US20060267691A1 (en) * | 2005-05-25 | 2006-11-30 | Satoru Takase | System and method for phase-locked loop leak compensation |
| CN1956337A (en) * | 2005-10-24 | 2007-05-02 | 北京六合万通微电子技术有限公司 | Method and device for removing parasitic reference frequency in phaselocked loop frequency synthesizer |
| US20080008284A1 (en) * | 2006-07-10 | 2008-01-10 | Mediatek Inc. | Pll device with leakage current compensation unit |
| CN101106375A (en) * | 2006-07-10 | 2008-01-16 | 联发科技股份有限公司 | PLL device and current compensation method |
| CN101578807A (en) * | 2007-01-09 | 2009-11-11 | 拉姆伯斯公司 | Receiver with clock recovery circuit and adaptive sample and equalizer timing |
| CN101025638A (en) * | 2007-03-20 | 2007-08-29 | 北京中星微电子有限公司 | Device and method for compensating MOS device grid leakage current |
| TW201004151A (en) * | 2008-07-01 | 2010-01-16 | Univ Nat Taiwan | Phase locked loop (PLL) with leakage current calibration |
| CN101958709A (en) * | 2009-07-17 | 2011-01-26 | 瑞昱半导体股份有限公司 | Clock generating apparatus having low clock jitter and related method thereof |
| CN102006058A (en) * | 2009-08-31 | 2011-04-06 | 安凯(广州)微电子技术有限公司 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
| CN102291129A (en) * | 2011-06-01 | 2011-12-21 | 浙江大学 | Phase-locked loop circuit used for inhibiting VCO (voltage-controlled oscillator) voltage ripple |
| CN102571082A (en) * | 2012-03-22 | 2012-07-11 | 秉亮科技（苏州）有限公司 | Phase-locked loop for gate leakage current of V2I tube in dynamic compensation voltage-controlled oscillator |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of performing locking fast |
| CN107342738A (en) * | 2015-08-26 | 2017-11-10 | 深圳清华大学研究院 | Support the two-point modulator of High Data Rate |
| CN107769545A (en) * | 2017-11-09 | 2018-03-06 | 上海华力微电子有限公司 | A kind of charge pump circuit for being used for capacitor electric leakage compensation in PLL |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115580297A (en) * | 2022-12-05 | 2023-01-06 | 成都芯矩阵科技有限公司 | Phase-locked loop circuit with extremely low jitter and phase-locked loop module |
| CN115800997A (en) * | 2023-01-31 | 2023-03-14 | 上海韬润半导体有限公司 | Brand-new sampling phase-locked loop circuit |
| CN115800997B (en) * | 2023-01-31 | 2023-04-28 | 上海韬润半导体有限公司 | Novel sampling phase-locked loop circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7633347B2 (en) | Apparatus and method for operating a phase-locked loop circuit | |
| US8531245B2 (en) | Temperature compensation in a PLL | |
| US8957712B2 (en) | Mixed signal TDC with embedded T2V ADC | |
| US6392494B2 (en) | Frequency comparator and clock regenerating device using the same | |
| US7420427B2 (en) | Phase-locked loop with a digital calibration loop and an analog calibration loop | |
| US10158366B2 (en) | Digital fractional-N PLL based upon ring oscillator delta-sigma frequency conversion | |
| US8378721B2 (en) | Phase-locked loop circuit | |
| US20080008284A1 (en) | Pll device with leakage current compensation unit | |
| US9312867B2 (en) | Phase lock loop device with correcting function of loop bandwidth and method thereof | |
| US8283984B2 (en) | Method and apparatus of phase locking for reducing clock jitter due to charge leakage | |
| WO2011115653A1 (en) | Phase locked loop (pll) with analog and digital feedback controls | |
| JP2010119074A (en) | Control circuitry | |
| US7786773B2 (en) | Phase-locked loop circuit | |
| CN112087228A (en) | Phase-locked loop circuit | |
| US9374038B2 (en) | Phase frequency detector circuit | |
| US7038509B1 (en) | Method and system for providing a phase-locked loop with reduced spurious tones | |
| CN112636748B (en) | Spread spectrum clock circuit and communication chip | |
| US11115038B2 (en) | Method for managing the startup of a phase-locked loop and corresponding integrated circuit | |
| US8248123B2 (en) | Loop filter | |
| CN107846216B (en) | Phase-locked loop self-calibration circuit | |
| US6919759B2 (en) | Digitally controlled tuner circuit | |
| CN111211776B (en) | Phase-locked loop circuit | |
| CN113315509A (en) | Phase-locked loop circuit and communication chip | |
| US7541850B1 (en) | PLL with low spurs | |
| KR101796877B1 (en) | CMOS charge pump and Pulse-Locked Loop apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |