CN113315509A - Phase-locked loop circuit and communication chip - Google Patents

Phase-locked loop circuit and communication chip Download PDF

Info

Publication number
CN113315509A
CN113315509A CN202110578359.7A CN202110578359A CN113315509A CN 113315509 A CN113315509 A CN 113315509A CN 202110578359 A CN202110578359 A CN 202110578359A CN 113315509 A CN113315509 A CN 113315509A
Authority
CN
China
Prior art keywords
field effect
effect transistor
voltage
output
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110578359.7A
Other languages
Chinese (zh)
Inventor
赵景仪
吴建东
赵鹏
宋阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen State Micro Electronics Co Ltd
Original Assignee
Shenzhen State Micro Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen State Micro Electronics Co Ltd filed Critical Shenzhen State Micro Electronics Co Ltd
Priority to CN202110578359.7A priority Critical patent/CN113315509A/en
Publication of CN113315509A publication Critical patent/CN113315509A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase-locked loop circuit and a communication chip belong to the field of integrated circuits.A modulation circuit outputs a first feedback current and a second feedback current according to a modulation voltage and a frequency division control signal; the phase frequency detector detects a phase difference between an input clock signal and a first clock signal and generates a first control signal; the charge pump carries out charge and discharge according to the first control signal and the second feedback current so as to output a first control voltage; the main loop filter adjusts an adjustable resistor in the main loop filter according to the first feedback current so as to modulate the first control voltage and generate a modulation voltage; the voltage-controlled oscillator outputs an output clock signal with a frequency proportional to the modulation voltage; the feedback frequency divider divides the frequency of the output clock signal by a preset frequency division ratio according to the frequency division control signal to output a first clock signal; the square root of the quotient of the preset frequency dividing ratio and the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is a constant; the loop stability of the phase-locked loop is improved.

Description

Phase-locked loop circuit and communication chip
Technical Field
The application belongs to the field of integrated circuits, and particularly relates to a phase-locked loop circuit and a communication chip.
Background
Phase-locked loops have become an indispensable part of modern integrated circuits due to the advantages of flexible frequency adjustment, frequency synthesis and the like. Although the phase-locked loop circuit structures are basically the same, the requirements for the performance parameters of the phase-locked loop are different due to different application occasions, such as input and output frequency ranges, frequency division ranges, output signal jitter, phase noise, power consumption, area and the like. A different clock generation circuit needs to be specifically designed for each application. If a phase locked loop can cover the application range of a plurality of systems, different clock generating circuits are not required to be designed for each system, and the design time and cost can be greatly reduced.
For example, a conventional second-order pll circuit is shown in fig. 1. When the frequency of an input clock signal changes, a traditional phase-locked loop needs an additional band-gap reference circuit and a current bias circuit, the loop stability of the traditional phase-locked loop is influenced by factors such as an input reference frequency, a frequency division ratio and the like, the loop bandwidth of the traditional phase-locked loop is limited, and the situation that a damping factor is over-damped or under-damped occurs due to poor loop stability.
Therefore, the traditional phase-locked loop cannot dynamically adjust the working state of each module of the phase-locked loop so as to output a high-performance frequency signal within the whole working range, so that when the wide-frequency output is carried out, the loop stability is poor, the damping factor changes along with the input reference frequency, and the influence of the process, the voltage and the temperature condition is caused.
Disclosure of Invention
The application aims to provide a phase-locked loop circuit and a communication chip, and aims to solve the problems that a traditional phase-locked loop circuit is poor in loop stability, damping factors change along with input reference frequency and are influenced by process, voltage and temperature conditions when wide-frequency output is carried out.
The embodiment of the application provides a phase-locked loop circuit, which comprises a main loop circuit, a modulation circuit and a main loop filter;
the modulation circuit is configured to output a first feedback current and a second feedback current according to a modulation voltage and a received frequency division control signal;
the main loop filter is connected with the modulation circuit and is configured to filter a first control voltage and adjust an adjustable resistor in the main loop filter according to the first feedback current so as to modulate the first control voltage and generate the modulation voltage;
the main loop circuit includes:
a phase frequency detector configured to detect a phase difference between an input clock signal and a first clock signal when receiving the input clock signal and generate the first control signal according to the phase difference;
the charge pump is connected with the modulation circuit, the phase frequency detector and the main loop filter, and is configured to charge and discharge according to the first control signal and the second feedback current so as to output the first control voltage;
a voltage controlled oscillator connected to the modulation circuit, the charge pump, and the main loop filter, and configured to output an output clock signal having a frequency proportional to a voltage analog of the modulation voltage;
the feedback frequency divider is connected with the voltage-controlled oscillator and the main loop phase discriminator and is configured to divide the frequency of the output clock signal by a preset frequency division ratio according to the frequency division control signal so as to output the first clock signal; the frequency division control signal is associated with the preset frequency division ratio.
The square root of the quotient of the preset frequency dividing ratio divided by the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is a constant.
In one embodiment, the modulation circuit comprises:
a voltage-to-current conversion component coupled to the charge pump and the main loop filter and configured to convert the modulated voltage to a first current;
a first current mirror assembly, connected to the voltage-to-current conversion assembly and the main loop filter, configured to convert a first current according to the frequency division control signal to output the first feedback current;
a second current mirror assembly connected with the voltage-current conversion assembly and the charge pump and configured to convert the first current to output the second feedback current;
wherein a scaling factor of the first feedback current and the second feedback current is equal to the preset frequency division ratio.
In one embodiment, the first current mirror assembly comprises a first current source, i first fets, a second fet, and i switches; wherein i is an integer greater than or equal to 2;
the input end of the first current source is connected to the first current input end of the first current mirror component, the output end of the first current source is connected with the first ends of the i switches, the grids of the i first field effect transistors and the grid of the second field effect transistor M2, the second end of the jth switch is connected with the drain electrode of the jth first field effect transistor, the source electrodes of the i first field effect transistors and the source electrode of the second field effect transistor are connected to a power ground in common, and the drain electrode of the second field effect transistor is connected to the first feedback current output end of the first current mirror component, wherein j is a natural number smaller than or equal to i.
In one embodiment, the second current mirror assembly comprises a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a first resistor, a second resistor and a third resistor;
the drain electrode of the third field effect transistor, the drain electrode of the fourth field effect transistor and the drain electrode of the fifth field effect transistor are commonly connected to the first current input end of the second current mirror assembly, the gate electrode of the third field effect transistor is connected with the gate electrode of the fourth field effect transistor, the gate electrode of the fifth field effect transistor, the source electrode of the third field effect transistor and the first end of the first resistor, the second end of the first resistor is connected with the drain electrode of the sixth field effect transistor, the gate electrode of the sixth field effect transistor is connected with the source electrode of the fourth field effect transistor and the drain electrode of the eighth field effect transistor, the source electrode of the sixth field effect transistor is connected with the drain electrode of the seventh field effect transistor, the gate electrode of the seventh field effect transistor and the gate electrode of the eighth field effect transistor are commonly connected to a first power supply, and the source electrode of the eighth field effect transistor is connected with the first end of the second resistor, the source electrode of the seventh field effect transistor and the second end of the second resistor are connected to a power ground in common, the source electrode of the fifth field effect transistor is connected with the first end of the third resistor, and the second end of the third resistor is connected to the second feedback current output end of the second current mirror component.
In one embodiment, the main loop filter comprises an adjustable resistor, a first capacitor and a second capacitor;
the first end of the adjustable resistor and the first end of the first capacitor are connected to the modulation voltage output end of the main loop filter and the first control voltage input end of the main loop filter together, the first end of the adjustable resistor is connected with the first end of the second capacitor, the second end of the first capacitor and the second end of the second capacitor are connected to a power ground together, and the adjusting end of the adjustable resistor is connected to the first feedback current input end of the main loop filter.
In one embodiment, the adjustable resistor comprises a follower, a ninth field effect transistor and a tenth field effect transistor;
the input end of the follower and the source electrode of the tenth field effect transistor are connected to the first end of the adjustable resistor, the output end of the follower is connected with the source electrode of the ninth field effect transistor, the grid electrode of the tenth field effect transistor and the drain electrode of the ninth field effect transistor are connected to the adjusting end of the adjustable resistor, and the drain electrode of the tenth field effect transistor is connected to the second end of the adjustable resistor.
In one embodiment, the method further comprises the following steps:
the starting circuit is connected with the voltage-controlled oscillator, the modulation circuit, the charge pump and the main loop filter and is configured to output a starting signal with preset duration when the circuit is powered on;
the modulation circuit is further configured to output the first feedback current and the second feedback current according to the start signal and the received frequency division control signal;
the voltage controlled oscillator is further configured to output the output clock signal having a frequency proportional to a voltage analog of the enable signal.
In one embodiment, the start-up circuit includes:
a trigger component configured to output an enable signal when powered up;
a reference component connected to the trigger component, the voltage-controlled oscillator, the modulation circuit, the charge pump, and the main loop filter, and configured to output the enable signal based on the enable signal and stop outputting the enable signal based on a first logic signal; the starting signal is a ramp voltage;
a Schmitt trigger coupled to the reference element, the voltage controlled oscillator, the modulation circuit, the charge pump, and the main loop filter and configured to flip a level to output the first logic signal when a ramp voltage is greater than a preset voltage.
The time length of the ramp voltage rising to the preset voltage is the preset time length.
In one embodiment, the charge pump comprises an operational amplifier, a first inverter, a second inverter, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor and a sixteenth field effect transistor;
a drain of the eleventh field effect transistor is connected to a second feedback current input terminal of the charge pump, a non-inverting input terminal of the operational amplifier, a drain of the twelfth field effect transistor, a source of the eleventh field effect transistor, a drain of the thirteenth field effect transistor, a source of the thirteenth field effect transistor, and a drain of the fifteenth field effect transistor are commonly connected to a first control voltage output terminal of the charge pump, a gate of the thirteenth field effect transistor, an input of the first inverter, a gate of the fifteenth field effect transistor, and an input of the second inverter are commonly connected to a first control signal input terminal of the charge pump, an output of the first inverter is connected to a gate of the twelfth field effect transistor, an output of the second inverter is connected to a gate of the fourteenth field effect transistor, a source of the twelfth field effect transistor is connected to a drain of the fourteenth field effect transistor, a positive input terminal of the operational amplifier, a drain of the twelfth field effect transistor, a source of the eleventh field effect transistor, a drain of the thirteenth field effect transistor, a source of the operational amplifier, a source of the thirteenth field effect transistor, a source of the thirteenth field effect, a source of the thirteenth field effect transistor, a source of the operational amplifier, a source of the thirteenth field effect transistor, a source of the thirteenth field effect, a source, The output end of the operational amplifier is connected with the inverting input end of the operational amplifier, the source electrode of the fourteenth field effect transistor is connected with the drain electrode of the sixteenth field effect transistor and the source electrode of the fifteenth field effect transistor, the source electrode of the sixteenth field effect transistor is connected with a power ground, the eleventh field effect transistor is connected with a first bias power supply, and the sixteenth field effect transistor M16 is connected with a second bias power supply.
The embodiment of the invention also provides a communication chip which comprises the phase-locked loop circuit.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the square root of the quotient of the preset frequency dividing ratio and the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is a constant; the damping factor of the phase-locked loop is irrelevant to the frequency dividing ratio and other parameters, so that the problem that the damping factor of the traditional phase-locked loop is influenced by the frequency dividing ratio is solved, and the loop stability of the phase-locked loop is improved during wide-frequency output.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic diagram of a conventional PLL circuit;
fig. 2 is a schematic structural diagram of a phase-locked loop circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a modulation circuit in a pll circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of another structure of a phase-locked loop circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a start circuit in a pll circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an exemplary circuit in a phase-locked loop circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 2 shows a schematic structural diagram of a phase-locked loop circuit provided in a preferred embodiment of the present application, and for convenience of description, only the relevant portions of the phase-locked loop circuit are shown, which are detailed as follows:
the phase-locked loop circuit includes a main loop circuit 10, a modulation circuit 11, and a main loop filter 12.
The modulation circuit 11 is configured to output a first feedback current and a second feedback current according to a modulation voltage and a received frequency division control signal;
a main loop filter 12 connected to the modulation circuit 11, and configured to filter the first control voltage and adjust an adjustable resistor in the main loop filter 12 according to the first feedback current, so as to modulate the first control voltage and generate a modulation voltage;
the main loop circuit 10 includes a phase frequency detector 13, a charge pump 14, a voltage controlled oscillator 15, and a feedback frequency divider 16.
A phase frequency detector 13 configured to detect a phase difference between an input clock signal and a first clock signal when receiving the input clock signal, and generate a first control signal according to the phase difference;
a charge pump 14 connected to the modulation circuit 11, the phase frequency detector 13, and the main loop filter 12, and configured to charge and discharge according to a first control signal and a second feedback current to output a first control voltage;
a voltage-controlled oscillator 15 connected to the modulation circuit 11, the charge pump 14, and the main loop filter 12, and configured to output an output clock signal having a frequency proportional to a voltage analog quantity of the modulation voltage;
a feedback frequency divider 16 connected to the voltage-controlled oscillator 15 and the main loop phase detector, and configured to divide the output clock signal by a preset division ratio according to the division control signal to output a first clock signal; wherein the division control signal is associated with a preset division ratio.
It should be noted that the square root of the quotient of the preset frequency dividing ratio divided by the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is constant.
Because of the phase-locked loopDamping factor
Figure BDA0003085122850000061
Where R is the resistance of the resistor in the main loop filter 12, IB _ CP is the second feedback current, KVCOFor the VCO 15 parameters, C is the capacitance coefficient of the capacitor in the main loop filter 12, and in the second-order PLL circuit, the capacitance coefficient C is
Figure BDA0003085122850000062
C1Is the capacitance value, C, of the first capacitor in the main loop filter 122Is the capacitance value of the second capacitor in the main loop filter 12, and N is the preset frequency dividing ratio; the ratio of the resistance value of the adjustable resistor to the first coefficient is constant, so that the damping factor of the phase-locked loop only follows the capacitance coefficient C and the 15 parameter K of the voltage-controlled oscillatorVCOThe size of the phase-locked loop is related to the frequency dividing ratio N and other parameters, so that the problem that the damping factor of the traditional phase-locked loop is influenced by the frequency dividing ratio is solved, and the loop stability of the phase-locked loop is improved when the wide frequency is output.
As shown in fig. 3, the modulation circuit 11 includes a voltage-to-current conversion component 111, a first current mirror component 112, and a second current mirror component 113.
A voltage-to-current conversion component 111, connected to the charge pump 14 and the main loop filter 12, configured to convert the modulated voltage into a first current;
a first current mirror component 112, connected to the voltage-to-current conversion component 111 and the main loop filter 12, configured to convert the first current according to the frequency division control signal to output a first feedback current;
a second current mirror component 113 connected to the voltage-to-current conversion component 111 and the charge pump 14, and configured to convert the first current to output a second feedback current;
and the ratio coefficient of the first feedback current and the second feedback current is equal to the preset frequency dividing ratio.
With the above-described configuration of the modulation circuit 11, two feedback currents having a proportionality coefficient of a preset frequency division ratio are generated.
As shown in fig. 4, the phase-locked loop circuit further includes a start circuit 17.
And the starting circuit 17 is connected with the voltage-controlled oscillator 15, the modulation circuit 11, the charge pump 14 and the main loop filter 12 and is configured to output a starting signal with a preset duration when the power is on.
The modulation circuit 11 is further configured to output a first feedback current and a second feedback current according to the start signal and the received frequency division control signal.
The voltage controlled oscillator 15 is further configured to output an output clock signal having a frequency proportional to the voltage analog of the start signal.
Through the starting circuit 17, the phase-locked loop circuit is powered on and started, and the starting circuit 17 stops working after the phase-locked loop circuit is powered on and started for a preset time, so that electric energy is saved.
As shown in fig. 5, the start-up circuit 17 includes a trigger element 171, a reference element 172, and a schmitt trigger 173.
The trigger component 171 is configured to output an enable signal when powered up.
A reference component 172 connected to the trigger component 171, the voltage-controlled oscillator 15, the modulation circuit 11, the charge pump 14, and the main loop filter 12, and configured to output a start signal based on the enable signal and stop outputting the start signal based on the first logic signal; the start signal is a ramp voltage.
The schmitt trigger 173 is connected to the reference element 172, the voltage-controlled oscillator 15, the modulation circuit 11, the charge pump 14, and the main loop filter 12, and configured to flip the level to output the first logic signal when the ramp voltage is greater than a preset voltage.
The time length of the ramp voltage rising to the preset voltage is the preset time length.
Through the structure of the starting circuit 17, the initial bias state of the phase-locked loop circuit is realized, and the locking time after power-on is accelerated.
Fig. 6 shows a partial exemplary circuit structure of a phase-locked loop circuit provided by an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the main loop filter 12 comprises an adjustable resistor Rd, a first capacitor C1 and a second capacitor C2;
a first end of the adjustable resistor Rd and a first end of the first capacitor C1 are commonly connected to the modulation voltage output end of the main loop filter 12 and the first control voltage input end of the main loop filter 12, the first end of the adjustable resistor Rd is connected to a first end of the second capacitor C2, a second end of the first capacitor C1 and a second end of the second capacitor C2 are commonly connected to the power ground, and an adjusting end of the adjustable resistor Rd is connected to the first feedback current input end of the main loop filter 12.
The adjustable resistor Rd comprises a follower U1, a ninth field effect transistor M9 and a tenth field effect transistor M10;
an input end of the follower U1 and a source electrode of the tenth field-effect transistor M10 are commonly connected to a first end of the adjustable resistor Rd, an output end of the follower U1 is connected with a source electrode of the ninth field-effect transistor M9, a gate electrode of the ninth field-effect transistor M9, a gate electrode of the tenth field-effect transistor M10 and a drain electrode of the ninth field-effect transistor M9 are commonly connected to an adjusting end of the adjustable resistor Rd, and a drain electrode of the tenth field-effect transistor M10 is connected to a second end of the adjustable resistor Rd.
By the structure of the adjustable resistor Rd, the resistance of the adjustable resistor is as large as
Figure BDA0003085122850000071
Wherein, gmTransconductance which is an adjustable resistance; beta is apThe parameters of the ninth fet M9 and the parameters of the tenth fet M10.
The first current mirror assembly 112 includes a first current source I1, I first fets (M01-M0I), a second fet M2, and I switches (K1-Ki); wherein i is an integer of 2 or more.
The input end of the first current source I1 is connected to the first current input end of the first current mirror component 112, the output end of the first current source I1 is connected to the first ends of the I switches, the gates of the I first fets and the gate of the second fet M2, the second end of the jth switch is connected to the drain of the jth first fet, where j is a natural number less than or equal to I, the sources of the I first fets and the source of the second fet M2 are commonly connected to the power ground, and the drain of the second fet M2 is connected to the first feedback current output end of the first current mirror component 112.
The frequency division word signals (M <1> to M < i >) with the preset frequency division ratio N are used as switch signals of the i switches to control the corresponding current to be switched on and off, and the sizes of the first field effect transistors (M01 to M0i) which correspond to the sequence of the signals are determined as the size of the mirror image current, so that the first feedback current IB _ LPF is regulated and controlled by the preset frequency division ratio N.
The second current mirror assembly 113 includes a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6, a seventh fet M7, an eighth fet M8, a first resistor R1, a second resistor R2, and a third resistor R3.
The drain of the third fet M3, the drain of the fourth fet M4 and the drain of the fifth fet M5 are commonly connected to the first current input terminal of the second current mirror assembly 113, the gate of the third fet M3 is connected to the gate of the fourth fet M4, the gate of the fifth fet M5, the source of the third fet M3 and the first end of the first resistor R1, the second end of the first resistor R1 is connected to the drain of the sixth fet M6, the gate of the sixth fet M6 is connected to the source of the fourth fet M4 and the drain of the eighth fet M8, the source of the sixth fet M6 is connected to the drain of the seventh fet M7, the gate of the seventh fet 7 and the gate of the eighth fet M8 are commonly connected to the first power supply VAA, the source of the eighth fet M8 is connected to the first end of the second resistor R42, the source of the seventh fet M7 is commonly connected to the second terminal of the second fet 2, the source of the fifth fet M5 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the second feedback current output terminal of the second current mirror assembly 113.
A current mirror with a mirror ratio coefficient of 1:1 is realized by the second current mirror assembly 113 described above. The second current mirror assembly 113 has the advantages of simple circuit structure and accurate current control.
The charge pump 14 includes an operational amplifier U2, a first inverter U3, a second inverter U4, an eleventh fet M11, a twelfth fet M12, a thirteenth fet M13, a fourteenth fet M14, a fifteenth fet M15, and a sixteenth fet M16.
The drain of the eleventh fet M11 is connected to the second feedback current input terminal of the charge pump 14, the non-inverting input terminal of the operational amplifier U2, the drain of the twelfth fet M12, the source of the eleventh fet M11, the drain of the thirteenth fet M13, the source of the thirteenth fet M13 and the drain of the fifteenth fet M15 are commonly connected to the first control voltage output terminal of the charge pump 14, the gate of the thirteenth fet M13, the input terminal of the first inverter U3, the gate of the fifteenth fet M15 and the input terminal of the second inverter U4 are commonly connected to the first control signal input terminal of the charge pump 14, the output terminal of the first inverter U3 is connected to the gate of the twelfth fet M12, the output terminal of the second inverter U4 is connected to the gate of the fourteenth fet M14, the source of the twelfth fet M12 is connected to the drain of the fourteenth fet M14, and the drain of the fourteenth fet M14, The output end of the operational amplifier U2 and the inverting input end of the operational amplifier U2 are connected, the source of the fourteenth field effect transistor M14 is connected to the drain of the sixteenth field effect transistor M16 and the source of the fifteenth field effect transistor M15, the source of the sixteenth field effect transistor M16 is connected to the power ground, the eleventh field effect transistor M11 is connected to the first bias power supply Vbiasp, and the sixteenth field effect transistor M16 is connected to the second bias power supply Vbiasn.
Through the circuit of the charge pump 14, the generation of the charge and discharge current according to the second feedback current and the first control signal output by the phase frequency detector 13 is realized, and the first control voltage is output.
The description of fig. 6 is further described below in conjunction with the working principle:
the voltage-current conversion component 111 converts the modulation voltage into a first current; the first current mirror component 112 converts the first current according to the frequency division control signal to output a first feedback current; in the first current mirror assembly 112, frequency division control signals (M <1> to M < i >) with a preset frequency division ratio N are used as switching signals of i switches to control the on and off of corresponding currents, the sizes of i first fets (M01 to M0i) corresponding to the sequence of the signals are determined as the magnitude of mirror currents, wherein the width-to-length ratio of the ith first fet Mi is 2 times that of the i-1 st first fet Mi-1, the width-to-length ratio of the i-1 st first fet Mi-1 is 2 times that of the i-2 nd first fet Mi-2, and so on. The first feedback current IB _ LPF can be regulated and controlled by a preset frequency division ratio N, where the preset frequency division ratio N is:
N＝2(i-1)*M<i>+2(i-2)*M<i-1>+…20*M<1>
the mirror ratio coefficient I1: IB _ LPF of the current of the first current mirror component 112 is N:1, I1 is the first current, and the first feedback current IB _ LPF is:
Figure BDA0003085122850000091
the second current mirror component 113 converts the first current to output a second feedback current; in the second current mirror module 113, the first current is mirrored to output the second feedback current, wherein the mirror ratio coefficient is 1: 1.
Therefore, the first feedback current IB _ LPF is proportional to the second feedback current IB _ CP by: IB _ LPF × N — IB _ CP × X is a constant. Namely: the ratio coefficient of the first feedback current and the second feedback current is equal to a preset frequency dividing ratio.
The phase frequency detector 13 detects a phase difference between the input clock signal and the first clock signal when receiving the input clock signal, and generates a first control signal according to the phase difference.
The charge pump 14 charges and discharges according to the first control signal and the second feedback current to output a first control voltage. Specifically, the charge pump 14 employs complementary switches of opposite signals, which are controlled by a positive first control signal UP and a negative first control signal DN, respectively. When the UP signal of the second positive control signal is at a low level and the DN signal of the second negative control signal is at a low level, the thirteenth fet M3 and the fourteenth fet M14 are turned on, the twelfth fet M12 and the fifteenth fet M15 are turned off, and at this time, the output first control voltage is charged. When the positive first control signal UP is at a high level and the negative first control signal DN is at a high level, the thirteenth fet M13 and the fourteenth fet M14 are turned off, the twelfth fet M12 and the fifteenth fet M15 are turned on, and at this time, the discharging operation is performed on the output first control voltage.
The main loop filter 12 filters the first control voltage and adjusts an adjustable resistor in the main loop filter 12 according to the first feedback current to modulate the first control voltage and generate a modulated voltage. In the main loop filter 12, the modulated voltage is output through the voltage follower U1, the voltage of the source of the ninth fet M9 and the voltage of the source of the tenth fet M10 are kept identical, and the ninth fet M9 and the tenth fet M10 form a mirror current tube. The first feedback current IB _ LPF is an input current, the input current is mirrored from the ninth fet M9 to the tenth fet M10, at this time, the working state of the tenth fet M10 is the same as that of the ninth fet M9, the adjustable resistor Rd of the loop filter is adjusted by the first feedback current IB _ LPF generated by the first current mirror assembly 112 regulated by a preset frequency division ratio, and the size of the adjustable resistor Rd is equal to that of the adjustable resistor Rd
Figure BDA0003085122850000101
Wherein, gmTransconductance which is an adjustable resistance; beta is apSubstituting the relationship between the first feedback current IB _ LPF and the second feedback current IB _ CP (the proportionality coefficient between the first feedback current IB _ LPF and the second feedback current IB _ CP is equal to the preset frequency dividing ratio) for the parameters of the ninth field effect transistor M9 and the parameters of the tenth field effect transistor M10, and then
Figure BDA0003085122850000102
X is constant, and the resistance R of the adjustable resistor Rd are realized
Figure BDA0003085122850000103
Is in direct proportion. And because of the damping factor of the phase-locked loop
Figure BDA0003085122850000104
Therefore, the damping factor xi is not controlled by the preset frequency dividing ratio and only corresponds to the 15 parameter K of the voltage-controlled oscillatorVCOAnd the magnitude of the capacitance coefficient C.
The voltage-controlled oscillator 15 outputs an output clock signal whose frequency is proportional to the voltage analog quantity of the modulation voltage; the feedback frequency divider 16 divides the frequency of the output clock signal by a preset frequency division ratio according to the frequency division control signal to output a first clock signal; the division control signal is associated with a preset division ratio.
According to the embodiment of the invention, a modulation circuit outputs a first feedback current and a second feedback current according to a modulation voltage and a received frequency division control signal; when receiving an input clock signal, the phase frequency detector detects a phase difference between the input clock signal and a first clock signal and generates a first control signal according to the phase difference; the charge pump carries out charge and discharge according to a first control signal and the second feedback current so as to output a first control voltage; the main loop filter filters the first control voltage and adjusts an adjustable resistor in the main loop filter according to the first feedback current so as to modulate the first control voltage and generate a modulation voltage; the voltage-controlled oscillator outputs an output clock signal of which the frequency is in direct proportion to the voltage analog quantity of the modulation voltage; the feedback frequency divider divides the frequency of the output clock signal by a preset frequency division ratio according to the frequency division control signal to output a first clock signal; the frequency division control signal is associated with a preset frequency division ratio; the square root of a quotient obtained by dividing the preset frequency dividing ratio by the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is a constant; because the ratio of the resistance value of the adjustable resistor to the first coefficient is constant, the damping factor of the phase-locked loop is irrelevant to the frequency dividing ratio and other parameters, the problem that the damping factor of the traditional phase-locked loop is influenced by the frequency dividing ratio is solved, and the loop stability of the phase-locked loop is improved when wide frequency is output.
The embodiment of the invention also provides a communication chip which comprises the phase-locked loop circuit.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A phase-locked loop circuit includes a main loop circuit, a modulation circuit, and a main loop filter;
the modulation circuit is configured to output a first feedback current and a second feedback current according to a modulation voltage and a received frequency division control signal;
the main loop filter is connected with the modulation circuit and is configured to filter a first control voltage and adjust an adjustable resistor in the main loop filter according to the first feedback current so as to modulate the first control voltage and generate the modulation voltage;
the main loop circuit includes:
a phase frequency detector configured to detect a phase difference between an input clock signal and a first clock signal when receiving the input clock signal and generate the first control signal according to the phase difference;
the charge pump is connected with the modulation circuit, the phase frequency detector and the main loop filter, and is configured to charge and discharge according to the first control signal and the second feedback current so as to output the first control voltage;
a voltage controlled oscillator connected to the modulation circuit, the charge pump, and the main loop filter, and configured to output an output clock signal having a frequency proportional to a voltage analog of the modulation voltage;
the feedback frequency divider is connected with the voltage-controlled oscillator and the main loop phase discriminator and is configured to divide the frequency of the output clock signal by a preset frequency division ratio according to the frequency division control signal so as to output the first clock signal; the frequency division control signal is associated with the preset frequency division ratio.
The square root of the quotient of the preset frequency dividing ratio divided by the second feedback current is a first coefficient, and the ratio of the resistance value of the adjustable resistor to the first coefficient is a constant.
2. The phase-locked loop circuit of claim 1, wherein the modulation circuit comprises:
a voltage-to-current conversion component coupled to the charge pump and the main loop filter and configured to convert the modulated voltage to a first current;
a first current mirror assembly, connected to the voltage-to-current conversion assembly and the main loop filter, configured to convert a first current according to the frequency division control signal to output the first feedback current;
a second current mirror assembly connected with the voltage-current conversion assembly and the charge pump and configured to convert the first current to output the second feedback current;
wherein a scaling factor of the first feedback current and the second feedback current is equal to the preset frequency division ratio.
3. The phase-locked loop circuit of claim 2, wherein the first current mirror assembly comprises a first current source, i first fets, a second fet, and i switches; wherein i is an integer greater than or equal to 2;
the input end of the first current source is connected to the first current input end of the first current mirror component, the output end of the first current source is connected with the first ends of the i switches, the grids of the i first field effect transistors and the grid of the second field effect transistor M2, the second end of the jth switch is connected with the drain electrode of the jth first field effect transistor, the source electrodes of the i first field effect transistors and the source electrode of the second field effect transistor are connected to a power ground in common, and the drain electrode of the second field effect transistor is connected to the first feedback current output end of the first current mirror component, wherein j is a natural number smaller than or equal to i.
4. The phase-locked loop circuit of claim 2, wherein the second current mirror assembly comprises a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a first resistor, a second resistor, and a third resistor;
the drain electrode of the third field effect transistor, the drain electrode of the fourth field effect transistor and the drain electrode of the fifth field effect transistor are commonly connected to the first current input end of the second current mirror assembly, the gate electrode of the third field effect transistor is connected with the gate electrode of the fourth field effect transistor, the gate electrode of the fifth field effect transistor, the source electrode of the third field effect transistor and the first end of the first resistor, the second end of the first resistor is connected with the drain electrode of the sixth field effect transistor, the gate electrode of the sixth field effect transistor is connected with the source electrode of the fourth field effect transistor and the drain electrode of the eighth field effect transistor, the source electrode of the sixth field effect transistor is connected with the drain electrode of the seventh field effect transistor, the gate electrode of the seventh field effect transistor and the gate electrode of the eighth field effect transistor are commonly connected to a first power supply, and the source electrode of the eighth field effect transistor is connected with the first end of the second resistor, the source electrode of the seventh field effect transistor and the second end of the second resistor are connected to a power ground in common, the source electrode of the fifth field effect transistor is connected with the first end of the third resistor, and the second end of the third resistor is connected to the second feedback current output end of the second current mirror component.
5. The phase-locked loop circuit of claim 1, wherein the main loop filter comprises an adjustable resistor, a first capacitor, and a second capacitor;
the first end of the adjustable resistor and the first end of the first capacitor are connected to the modulation voltage output end of the main loop filter and the first control voltage input end of the main loop filter together, the first end of the adjustable resistor is connected with the first end of the second capacitor, the second end of the first capacitor and the second end of the second capacitor are connected to a power ground together, and the adjusting end of the adjustable resistor is connected to the first feedback current input end of the main loop filter.
6. The phase-locked loop circuit of claim 5, wherein the adjustable resistance comprises a follower, a ninth fet, and a tenth fet;
the input end of the follower and the source electrode of the tenth field effect transistor are connected to the first end of the adjustable resistor, the output end of the follower is connected with the source electrode of the ninth field effect transistor, the grid electrode of the tenth field effect transistor and the drain electrode of the ninth field effect transistor are connected to the adjusting end of the adjustable resistor, and the drain electrode of the tenth field effect transistor is connected to the second end of the adjustable resistor.
7. The phase-locked loop circuit of claim 1, further comprising:
the starting circuit is connected with the voltage-controlled oscillator, the modulation circuit, the charge pump and the main loop filter and is configured to output a starting signal with preset duration when the circuit is powered on;
the modulation circuit is further configured to output the first feedback current and the second feedback current according to the start signal and the received frequency division control signal;
the voltage controlled oscillator is further configured to output the output clock signal having a frequency proportional to a voltage analog of the enable signal.
8. The phase-locked loop circuit of claim 7, wherein the startup circuit comprises:
a trigger component configured to output an enable signal when powered up;
a reference component connected to the trigger component, the voltage-controlled oscillator, the modulation circuit, the charge pump, and the main loop filter, and configured to output the enable signal based on the enable signal and stop outputting the enable signal based on a first logic signal; the starting signal is a ramp voltage;
a Schmitt trigger coupled to the reference element, the voltage controlled oscillator, the modulation circuit, the charge pump, and the main loop filter and configured to flip a level to output the first logic signal when a ramp voltage is greater than a preset voltage.
The time length of the ramp voltage rising to the preset voltage is the preset time length.
9. The phase-locked loop circuit of claim 1, wherein the charge pump comprises an operational amplifier, a first inverter, a second inverter, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, and a sixteenth field effect transistor;
a drain of the eleventh field effect transistor is connected to a second feedback current input terminal of the charge pump, a non-inverting input terminal of the operational amplifier, a drain of the twelfth field effect transistor, a source of the eleventh field effect transistor, a drain of the thirteenth field effect transistor, a source of the thirteenth field effect transistor, and a drain of the fifteenth field effect transistor are commonly connected to a first control voltage output terminal of the charge pump, a gate of the thirteenth field effect transistor, an input of the first inverter, a gate of the fifteenth field effect transistor, and an input of the second inverter are commonly connected to a first control signal input terminal of the charge pump, an output of the first inverter is connected to a gate of the twelfth field effect transistor, an output of the second inverter is connected to a gate of the fourteenth field effect transistor, a source of the twelfth field effect transistor is connected to a drain of the fourteenth field effect transistor, a positive input terminal of the operational amplifier, a drain of the twelfth field effect transistor, a source of the eleventh field effect transistor, a drain of the thirteenth field effect transistor, a source of the operational amplifier, a source of the thirteenth field effect transistor, a source of the thirteenth field effect, a source of the thirteenth field effect transistor, a source of the operational amplifier, a source of the thirteenth field effect transistor, a source of the thirteenth field effect, a source, The output end of the operational amplifier is connected with the inverting input end of the operational amplifier, the source electrode of the fourteenth field effect transistor is connected with the drain electrode of the sixteenth field effect transistor and the source electrode of the fifteenth field effect transistor, the source electrode of the sixteenth field effect transistor is connected with a power ground, the eleventh field effect transistor is connected with a first bias power supply, and the sixteenth field effect transistor M16 is connected with a second bias power supply.
10. A communication chip comprising a phase locked loop circuit as claimed in any one of claims 1 to 9.
CN202110578359.7A 2021-05-26 2021-05-26 Phase-locked loop circuit and communication chip Pending CN113315509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110578359.7A CN113315509A (en) 2021-05-26 2021-05-26 Phase-locked loop circuit and communication chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110578359.7A CN113315509A (en) 2021-05-26 2021-05-26 Phase-locked loop circuit and communication chip

Publications (1)

Publication Number Publication Date
CN113315509A true CN113315509A (en) 2021-08-27

Family

ID=77375033

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110578359.7A Pending CN113315509A (en) 2021-05-26 2021-05-26 Phase-locked loop circuit and communication chip

Country Status (1)

Country Link
CN (1) CN113315509A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116032253A (en) * 2023-03-24 2023-04-28 深圳市思远半导体有限公司 Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101588178A (en) * 2008-05-23 2009-11-25 中芯国际集成电路制造(上海)有限公司 Self-biased phase-locked loop
US20110063004A1 (en) * 2009-09-14 2011-03-17 Sunplus Technology Co., Ltd. Frequency synthesis system with self-calibrated loop stability and bandwidth
US20120319786A1 (en) * 2011-06-20 2012-12-20 Texas Instruments Incorporated Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency
US20140347105A1 (en) * 2013-05-23 2014-11-27 Broadcom Corporation Compensation of slow time-varying variations in voltage controlled oscillator (vco) frequency in cellular transceivers
JP2016063445A (en) * 2014-09-19 2016-04-25 株式会社ソシオネクスト Pll circuit and semiconductor integrated circuit
CN106559072A (en) * 2015-09-25 2017-04-05 中芯国际集成电路制造(上海)有限公司 Self-biased phase-locked loop
CN107634759A (en) * 2017-09-15 2018-01-26 北京华大九天软件有限公司 A kind of phase-locked loop circuit of adaptive loop circuit bandwidth
CN109728809A (en) * 2019-01-18 2019-05-07 柳州阜民科技有限公司 Phase-locked loop frequency integrator
CN112636748A (en) * 2020-11-30 2021-04-09 深圳市国微电子有限公司 Spread spectrum clock circuit and communication chip

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101588178A (en) * 2008-05-23 2009-11-25 中芯国际集成电路制造(上海)有限公司 Self-biased phase-locked loop
US20110063004A1 (en) * 2009-09-14 2011-03-17 Sunplus Technology Co., Ltd. Frequency synthesis system with self-calibrated loop stability and bandwidth
US20120319786A1 (en) * 2011-06-20 2012-12-20 Texas Instruments Incorporated Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency
US20140347105A1 (en) * 2013-05-23 2014-11-27 Broadcom Corporation Compensation of slow time-varying variations in voltage controlled oscillator (vco) frequency in cellular transceivers
JP2016063445A (en) * 2014-09-19 2016-04-25 株式会社ソシオネクスト Pll circuit and semiconductor integrated circuit
CN106559072A (en) * 2015-09-25 2017-04-05 中芯国际集成电路制造(上海)有限公司 Self-biased phase-locked loop
CN107634759A (en) * 2017-09-15 2018-01-26 北京华大九天软件有限公司 A kind of phase-locked loop circuit of adaptive loop circuit bandwidth
CN109728809A (en) * 2019-01-18 2019-05-07 柳州阜民科技有限公司 Phase-locked loop frequency integrator
CN112636748A (en) * 2020-11-30 2021-04-09 深圳市国微电子有限公司 Spread spectrum clock circuit and communication chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116032253A (en) * 2023-03-24 2023-04-28 深圳市思远半导体有限公司 Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment
CN116032253B (en) * 2023-03-24 2023-07-21 深圳市思远半导体有限公司 Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment

Similar Documents

Publication Publication Date Title
US7633347B2 (en) Apparatus and method for operating a phase-locked loop circuit
US6614313B2 (en) Precision oscillator circuits and methods with switched capacitor frequency control and frequency-setting resistor
EP0574982B1 (en) Switched capacitor charge pump, as well as sawtooth oscillator comprising such a switched capacitor charge pump
US8026769B2 (en) Frequency-locked clock generator
US8373502B1 (en) Gm-C filter tuning circuit based on relaxation oscillator
CN107634759B (en) Phase-locked loop circuit capable of adapting to loop bandwidth
US8274325B2 (en) Phase-locked loop
US8659362B2 (en) Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation
US7443254B2 (en) Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency
US20060284687A1 (en) Phase-locked loop having a bandwidth related to its input frequency
WO2001026230A1 (en) Pll loop filter with switched-capacitor resistor
WO2009109636A2 (en) Phase-locked loop
KR20050063619A (en) The voltage controlled digital analog oscillator and the frequency synthesizer using the same
CN101414784A (en) Charge pump
CN110572150B (en) Clock generation circuit and clock generation method
US20030107420A1 (en) Differential charge pump
KR20170120514A (en) Signal generation circuit and signal generation method
CN113315509A (en) Phase-locked loop circuit and communication chip
CN114499512A (en) Double-loop phase-locked loop
EP2713518A1 (en) Voltage translation circuit and a voltage-controlled oscillator including the latter
US7649408B2 (en) Loop filters
US20060132208A1 (en) Controllable idle time current mirror circuit for switching regulators, phase-locked loops, and delay-locked loops
US8213560B2 (en) PLL circuit
US8248123B2 (en) Loop filter
CN110572151B (en) Phase-locked loop circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20210827