CN116032253B - Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment - Google Patents

Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment Download PDF

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Publication number
CN116032253B
CN116032253B CN202310293209.0A CN202310293209A CN116032253B CN 116032253 B CN116032253 B CN 116032253B CN 202310293209 A CN202310293209 A CN 202310293209A CN 116032253 B CN116032253 B CN 116032253B
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Prior art keywords
signal
clock signal
subunit
unit
timing
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CN116032253A (en
Inventor
陆维立
罗冬哲
张航
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Shenzhen Siyuan Semiconductor Co ltd
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Shenzhen Siyuan Semiconductor Co ltd
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Priority to CN202310833344.XA priority Critical patent/CN116886077A/en
Priority to CN202310293209.0A priority patent/CN116032253B/en
Publication of CN116032253A publication Critical patent/CN116032253A/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a clock signal generation circuit, a charge pump phase-locked loop circuit, a chip and terminal equipment. The timing unit is used for receiving the clock signal and performing at least one timing operation in response to the clock signal. The time length of each time of the timing operation is a first preset time length, and a timing signal is output when the timing unit executes the timing operation. The logic unit determines a first preset duration based on the timing signal, and outputs a control signal based on the first duration and the first preset duration of the clock signal at the first level. The voltage conversion unit is used for receiving the control signal to output a voltage signal and adjusting the voltage signal based on the control signal. The oscillation unit is used for receiving the voltage signal to output a clock signal and adjusting the frequency of the clock signal based on the voltage signal. By the mode, the stability of the clock signal can be improved.

Description

Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a clock signal generating circuit, a charge pump phase-locked loop circuit, a chip, and a terminal device.
Background
A Phase-Locked Loop (PLL) circuit is a feedback control circuit. The phase-locked loop circuits commonly used today include charge pump phase-locked loop circuits.
At present, the charge pump phase-locked loop circuit is generally a system with two poles, and a corresponding compensation circuit is generally required to be arranged for compensation so as to improve the stability of the charge pump phase-locked loop circuit.
However, when the compensation circuit cannot provide a sufficient phase margin for the loop in the charge pump pll circuit, the stability of the frequency of the clock signal output by the charge pump pll circuit is poor.
Disclosure of Invention
The application aims to provide a clock signal generating circuit, a charge pump phase-locked loop circuit, a chip and terminal equipment, which can improve the stability of a clock signal.
To achieve the above object, in a first aspect, the present application provides a clock signal generating circuit, including:
the timing unit is used for receiving the clock signal and responding to the clock signal to execute at least one timing operation, wherein the duration of each timing operation is a first preset duration, and the timing unit outputs a timing signal when executing the timing operation;
the logic unit is connected with the timing unit and is used for receiving the clock signal and the timing signal, determining a first preset duration based on the timing signal and outputting a control signal based on the first duration of the clock signal at the first level and the first preset duration;
The voltage conversion unit is connected with the logic unit and is used for receiving the control signal to output a voltage signal and adjusting the voltage signal based on the control signal;
the oscillating unit is respectively connected with the timing unit, the logic unit and the voltage conversion unit, and is used for receiving the voltage signal to output a clock signal and adjusting the frequency of the clock signal based on the voltage signal.
In an alternative manner, the timing unit is further configured to start timing each time the clock signal is at the first edge, and stop timing when the clock signal is for a first preset period of time, so as to perform a timing operation.
In an alternative manner, the control signal includes a first control sub-signal and a second control sub-signal;
the logic unit is further configured to output a first control sub-signal when the first time length is longer than a first preset time length, and output a second control sub-signal when the first time length is shorter than the first preset time length;
the voltage conversion unit is further used for reducing the voltage signal when the first control sub-signal is received and increasing the voltage signal when the second control sub-signal is received;
the oscillating unit is further configured to increase the frequency of the clock signal when the voltage signal increases and to decrease the frequency of the clock signal when the voltage signal decreases.
In an alternative way, the timing unit comprises:
the trigger subunit is connected with the oscillation unit, and is used for receiving the clock signal and responding to the clock signal to output a trigger signal;
the energy storage subunit is connected with the trigger subunit and used for changing voltage when receiving the trigger signal;
the comparison subunit is respectively connected with the energy storage subunit and the logic unit, and is used for receiving the first voltage on the energy storage subunit and the first reference voltage, and executing timing operation when the first voltage is not equal to the first reference voltage so as to output a timing signal.
In an alternative way, the timing unit further comprises:
a current mirror unit connected to the first current source, the current mirror unit configured to output a first current and a second current that are equal based on a current output of the first current source, wherein the first current is configured to change a voltage of the energy storage subunit when the energy storage subunit receives the trigger signal;
a resistor subunit connected with the current mirror unit, the resistor subunit being configured to output a first reference voltage based on the second current;
The reset subunit is respectively connected with the comparison subunit and the trigger subunit, and is used for outputting a reset signal to the trigger subunit when the comparison subunit stops executing timing operation so as to enable the trigger subunit to stop outputting the trigger signal.
In an alternative, the trigger subunit includes a D-flip-flop;
the clock input end of the D trigger is connected with the oscillating unit, the data input end of the D trigger is connected with the first power supply, and the inverted data output end of the D trigger is connected with the energy storage subunit.
In an alternative manner, the energy storage subunit includes a first switching tube and a first capacitor;
the first end of the first switch tube is connected with the trigger subunit, the second end of the first switch tube is grounded with the second end of the first capacitor, and the third end of the first switch tube is connected with the first end of the first capacitor and the comparison subunit respectively.
In an alternative, the comparison subunit includes a comparator and a schmitt trigger;
the first input end of the comparator inputs a first reference voltage, the second input end of the comparator is connected with the energy storage subunit, the output end of the comparator is connected with the input end of the Schmitt trigger, and the output end of the Schmitt trigger is used for outputting a timing signal.
In an alternative, the current mirror unit includes a second switching tube, a third switching tube, and a fourth switching tube;
the first end of the second switching tube is respectively connected with the third end of the second switching tube, the first end of the third switching tube, the first end of the fourth switching tube and the cathode of the first current source, the anode of the first current source is grounded, the second end of the second switching tube, the second end of the third switching tube and the second end of the fourth switching tube are all connected with the second power supply, the third end of the third switching tube is respectively connected with the energy storage subunit and the comparison subunit, and the third end of the fourth switching tube is respectively connected with the resistor subunit and the comparison subunit.
In an alternative, the resistor subunit includes a first resistor;
the first end of the first resistor is connected with the comparison subunit, and the second end of the first resistor is grounded.
In an alternative way, the reset subunit includes an inverter, a delay, and a nand gate;
the input end of the inverter is respectively connected with the input ends of the comparison subunit and the delay device, the output end of the inverter is connected with the first input end of the NAND gate, the output end of the delay device is connected with the second input end of the NAND gate, and the output end of the NAND gate is connected with the trigger subunit.
In an alternative manner, the clock signal generating circuit further includes a frequency dividing unit;
the frequency division unit is connected between the timing unit and the oscillation unit, and is also connected between the logic unit and the oscillation unit;
the frequency dividing unit is used for dividing the frequency of the clock signal and outputting frequency dividing signals, wherein the frequency dividing signals are respectively input to the timing unit and the logic unit, and the frequency of the frequency dividing signals is one-half of the frequency integer of the clock signal;
the timing unit is further configured to perform at least one timing operation in response to the frequency-divided signal;
the logic unit is also used for outputting a control signal based on the time period when the frequency division signal is at the first level and the first preset time period.
In an alternative way, the voltage conversion unit is a charge pump and/or the oscillation unit is a voltage controlled oscillator.
In a second aspect, the present application provides a charge pump phase locked loop circuit comprising a clock signal generation circuit as described above.
In a third aspect, the present application provides a chip comprising a charge pump phase locked loop circuit as described above.
In a fourth aspect, the present application provides a terminal device comprising a chip as described above.
The beneficial effects of this application are: the clock signal generation circuit comprises a timing unit, a logic unit, a voltage conversion unit and an oscillation unit. When the oscillating unit outputs a clock signal, the clock signal is respectively input to the timing unit and the logic unit. In one aspect, the timing unit performs at least one timing operation in response to the clock signal, and outputs the timing signal to the logic unit when the timing operation is performed, so that the logic unit can determine a duration of each time the timing operation is performed, i.e., a first preset duration, according to the received timing signal. On the other hand, the logic unit further outputs a control signal to the voltage conversion unit according to the duration of the clock signal at the first level and the first preset duration, so that the voltage conversion unit adjusts the output voltage signal. Since the voltage signal is input to the oscillation unit and the oscillation unit outputs the clock signal based on the voltage signal, the purpose of adjusting the frequency of the clock signal output by the oscillation unit can also be achieved by adjusting the voltage signal. By the method, the clock signal can be corrected in each cycle, so that the clock signal does not have a phase accumulation process, and the pole provided by the oscillating unit can be eliminated. The clock signal generation circuit only comprises one pole and the generated clock signal has higher stability. That is, compared with the system with two poles in the related art, the clock signal generating circuit provided by the application is a single-pole system, so that the purpose of improving the stability of the clock signal can be achieved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a clock signal according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a clock signal and a frequency-divided signal according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic circuit diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of signals in a clock signal generating circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of signals in the clock signal generating circuit according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram of a clock signal generating circuit 100 according to an embodiment of the present disclosure. The clock signal generating circuit 100 shown in fig. 1 includes a timing unit 10, a logic unit 20, a voltage converting unit 30, and an oscillating unit 40. The logic unit 20 is connected to the timer unit 10 and the voltage conversion unit 30, respectively. The oscillation unit 40 is connected to the timer unit 10, the logic unit 20, and the voltage conversion unit 30, respectively.
Specifically, the timing unit 10 receives the clock signal F1, and performs at least one timing operation in response to the clock signal F1. Referring to fig. 2, a graph of the clock signal F1 is shown in fig. 2. The clock signal F1 is a signal for alternately switching the high and low levels. The voltage corresponding to the high level in the clock signal F1 may be different according to the requirements of different application scenarios, for example, the voltage corresponding to the high level of the TTL standard is 5V.
Then, in some embodiments, the timing unit 10 may perform at least one timing operation in response to the clock signal F1. Wherein the duration of each time of the timing operation is a first preset duration, and the timing signal T1 is output when the timing unit 10 performs the timing operation. The first preset duration is a preset timing duration, the timing signal T1 may be any signal, the first preset duration and the timing signal T1 may be set according to actual application conditions, and the embodiment of the present application does not specifically limit this.
In an embodiment, the timing unit 10 is further configured to start timing each time the clock signal F1 is at the first edge, and stop timing when the first preset duration is counted, so as to perform a timing operation. Wherein the first edge may be a rising edge or a falling edge.
Still taking the clock signal shown in fig. 2 as an example. And takes as an example that the first preset time period is set as the time period ts1, and the timing unit 10 starts timing every time the clock signal is on the rising edge. As shown in fig. 2, the clock signal F1 is on the rising edge at time t1, and starts to count when the count duration reaches the duration ts1, i.e., stops counting at time t 2. Between time T1 and time T2, the timer unit 10 performs a time counting operation and keeps outputting the timing signal T1. Then, the time counting starts at the time t3, and stops when the time counting time reaches the time ts1, that is, at the time t 4. Between time T3 and time T4, the timer unit 10 performs a timer operation again, and the timer unit 10 keeps outputting the timer signal T1. Similarly, the corresponding timing signal T1 can be obtained based on the clock signal F1.
It should be noted that this embodiment only illustrates one way in which the timing unit 10 performs the timing operation in response to the clock signal F1, and in other embodiments, the timing unit 10 may be prompted to start timing in other manners, which is not particularly limited in the embodiments of the present application. For example, in some embodiments, the timing unit 10 may further perform a timing operation based on when the voltage corresponding to the clock signal F1 is greater than a preset voltage threshold.
Next, the logic unit 20 receives the clock signal F1 and the timing signal T1 at the same time. The logic unit 20 determines a first preset duration based on the timing signal T1, and outputs the control signal C1 based on the first duration and the first preset duration of the clock signal F1 at the first level. Wherein the first level may be a high level or a low level. Taking the clock signal illustrated in fig. 2 as an example, if the first level is high, the first duration of the clock signal F1 at the first level is the duration ts2. In an embodiment, the logic unit 20 may output the corresponding control signal C1 based on a magnitude relation between the first duration and the first preset duration.
In some embodiments, logic unit 20 may employ a micro control unit (Microcontroller Unit, MCU) or digital signal processing (Digital Signal Processing, DSP) controller, or the like.
Then, the control signal C1 output from the logic unit 20 is input to the voltage conversion unit 30. The voltage conversion unit 30 receives the control signal C1 to output a voltage signal V1. The voltage conversion unit 30 adjusts the voltage signal V1 based on the control signal C1.
In some embodiments, the voltage conversion unit 30 is a charge pump. A charge pump (charge pump) is a dc-dc converter, which uses a capacitor as an energy storage element, and is generally used to generate an output voltage greater than an input voltage or to generate a negative output voltage. In this embodiment, the control signal C1 is used as the input voltage of the charge pump and the voltage signal V1 is used as the output voltage of the charge pump.
Then, the voltage signal V1 is input to the oscillating unit 40, and the oscillating unit 40 receives the voltage signal to output a clock signal, that is, the oscillating unit 40 can output a corresponding clock signal F1 based on the voltage signal V1. Thus, by adjusting the voltage signal V1, the frequency of the clock signal F1 output from the oscillating unit 40 can be adjusted.
In some embodiments, the shock unit 40 is a voltage controlled oscillator. A voltage controlled oscillator refers to an oscillating circuit (VCO) whose output frequency corresponds to an input control voltage. The frequency of the clock signal output by the voltage-controlled oscillator is a function of the input signal voltage, i.e. the operating state of the voltage-controlled oscillator or the component parameters of the tank circuit are controlled by the input control voltage. In this embodiment, the voltage signal V1 is an input control voltage of the voltage-controlled oscillator, and the frequency of the clock signal F1 is an output frequency of the voltage-controlled oscillator.
In the above manner, the adjustment of the clock signal F1 can be achieved based on the clock signal T1 generated by the clock unit 10. The clock signal F1 can then be adjusted (also called corrected) at each cycle. Wherein one cycle includes starting from the output of the timing signal T1 by the timing unit 10 until the output of the clock signal F1 to the oscillating unit 40. Thus, the clock signal F1 does not have a phase accumulation process, and the pole provided by the oscillating unit 40 can be eliminated. Only one pole provided by the voltage converting unit 30 is included in the clock signal generating circuit 100, and the stability of the clock signal F1 generated by the clock signal generating circuit 100 is high. That is, compared with the system with two poles in the related art, the clock signal generating circuit provided by the application is a single-pole system, so that the purpose of improving the stability of the clock signal can be achieved. In addition, since only one pole exists, a corresponding compensation circuit is not required to be arranged as in the related art, so that the circuit structure is simplified and the cost is saved.
The embodiment of the application also provides a specific mode for adjusting the frequency of the clock signal F1. In this manner, the control signal includes a first control sub-signal and a second control sub-signal.
Specifically, the logic unit 20 is further configured to output the first control sub-signal when the first time period is longer than the first preset time period, and output the second control sub-signal when the first time period is shorter than the first preset time period. The voltage conversion unit 30 is further configured to decrease the voltage signal V1 when the first control sub-signal is received, and to increase the voltage signal V1 when the second control sub-signal is received. The oscillation unit 40 is also configured to increase the frequency of the clock signal F1 when the voltage signal V1 increases, and to decrease the frequency of the clock signal F1 when the voltage signal V1 decreases.
Taking the clock signal F1 shown in fig. 2, and taking the first time period as the time period ts2 as an example.
If the first preset duration is the duration ts1, the first duration ts2 is longer than the first preset duration ts1, and it can be determined that the frequency of the clock signal F1 is larger at this time. In this case, the logic unit 20 outputs the first control sub-signal. The voltage conversion unit 30 receives the first control sub-signal and reduces the voltage signal V1 outputted therefrom in response to the first control sub-signal. The oscillation unit 40 decreases the frequency of the clock signal F1 output therefrom as the input voltage signal V1 decreases.
If the first preset duration is the duration ts3, the first duration ts2 is smaller than the first preset duration ts3, and it can be determined that the frequency of the clock signal F1 is smaller at this time. In this case, the logic unit 20 outputs the second control sub-signal. The voltage conversion unit 30 receives the second control sub-signal and increases the voltage signal V1 outputted therefrom in response to the second control sub-signal. The oscillation unit 40 increases the frequency of the clock signal F1 output therefrom as the input voltage signal V1 increases.
In summary, through the magnitude relation between the first time length and the first preset time, it can be determined whether the frequency of the current clock signal F1 is larger or smaller, so as to adjust the decrease of the clock signal F1 when the clock signal F1 is larger, and adjust the increase of the clock signal F1 when the clock signal F1 is smaller. Thus, the process of frequency adjustment of the clock signal F1 is realized, the pole provided by the oscillation unit 40 is eliminated, and the stability of the clock signal F1 is improved.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a clock signal generating circuit according to another embodiment of the present application. As shown in fig. 3, the clock signal generation circuit 100 further includes a frequency division unit 50.
The frequency dividing unit 50 is connected between the timing unit 10 and the oscillating unit 40, and the frequency dividing unit 50 is also connected between the logic unit 20 and the oscillating unit 40. Specifically, the input end of the frequency dividing unit 50 is connected to the oscillating unit 40, and the output end of the frequency dividing unit 50 is connected to the timing unit 10 and the logic unit 20, respectively.
In this embodiment, the frequency dividing unit 50 is configured to divide the clock signal F1 and output a divided signal F2. The frequency of the frequency-divided signal F2 is an integer fraction of the frequency of the clock signal F1. The frequency-divided signal F2 is also a signal that alternately switches the high and low levels.
One plot of the clock signal F1 versus the divided signal F2 is shown schematically in fig. 4. As shown in fig. 4, the period between time t11 and time t12 is one cycle of the clock signal F1, and the period between time t11 and time t13 is one cycle of the frequency-divided signal F2. In this embodiment, the period of the frequency-divided signal F2 is 5 times the period of the clock signal F1, and the frequency is the inverse of the period, so the frequency of the frequency-divided signal F2 is one fifth of the clock signal F1. In summary, fig. 4 shows an embodiment in which the frequency dividing unit 50 divides the frequency of the clock signal F1, and the frequency of the divided frequency signal F2 after the frequency division is one fifth of the frequency of the clock signal F1.
Then, the frequency division signal F1 is input to the timing unit 10 and the logic unit 20, respectively. Wherein the timing unit 10 is further configured to perform at least one timing operation in response to the frequency-divided signal F1. And the timing unit 10 outputs a timing signal T1 when performing a timing operation.
In an embodiment, the timing unit 10 is further configured to start timing each time the frequency-divided signal F1 is at the first edge, and stop timing when the first preset time period is counted, so as to perform a timing operation once. Wherein the first edge may be a rising edge or a falling edge. The specific implementation process may refer to the detailed description of fig. 2, which is not repeated herein, and is within the scope of those skilled in the art to easily understand.
Next, the logic unit 20 is further configured to output the control signal C1 based on the duration of the frequency-divided signal F1 at the first level and the first preset duration. In an embodiment, the logic unit 20 may output the corresponding control signal C1 based on a magnitude relation between a duration of the frequency-divided signal F1 at the first level and a first preset duration. The control signal C1 is input to the voltage conversion unit 30 to adjust the voltage signal V1 output from the voltage conversion unit 30. And the purpose of adjusting the clock signal F1 output by the oscillating unit 40 is achieved by adjusting the voltage signal V1.
In this embodiment, the adjustment of the clock signal F1 is achieved based on the frequency-divided signal F1 and the clock signal T1. The clock signal F1 can also be modified at each cycle to eliminate the pole provided by the oscillating unit 40, thereby contributing to an improvement in the stability of the clock signal.
In an embodiment, based on the structure shown in fig. 3, a similar manner to the specific manner of adjusting the frequency of the clock signal F1 in the above-described embodiment can also be achieved. In this embodiment, the control signal also includes a first control sub-signal and a second control sub-signal.
Specifically, the logic unit 20 is further configured to output the first control sub-signal when the duration of the frequency-divided signal F1 at the first level is greater than the first preset duration, and output the second control sub-signal when the duration of the frequency-divided signal F1 at the first level is less than the first preset duration. The voltage conversion unit 30 is further configured to decrease the voltage signal V1 when the first control sub-signal is received, and to increase the voltage signal V1 when the second control sub-signal is received. The oscillation unit 40 is also configured to increase the frequency of the clock signal F1 when the voltage signal V1 increases, and to decrease the frequency of the clock signal F1 when the voltage signal V1 decreases. The specific implementation process may refer to the specific description of the above embodiment, which is within the scope of those skilled in the art and will not be repeated herein.
Referring to fig. 5 in conjunction with fig. 3, in one embodiment, the timing unit 10 includes a triggering subunit 11, an energy storage subunit 12, and a comparing subunit 13.
The triggering subunit 11 is connected to the oscillation unit 40 via a frequency dividing unit 50. The energy storage subunit 12 is connected to the triggering subunit 11. The comparison subunit 13 is connected to the energy storage subunit 12 and the logic unit 20, respectively.
Specifically, the trigger subunit 11 is configured to receive the frequency-divided signal F2, and output the trigger signal TR1 in response to the frequency-divided signal F2. In some embodiments, the trigger subunit 11 may start outputting the trigger signal TR1 every time the frequency-divided signal F2 is on a rising edge or a falling edge. In other embodiments, if the timing unit 10 is configured to receive the clock signal F1 as shown in fig. 1, the trigger subunit 11 is configured to receive the clock signal F1 and output the trigger signal TR1 in response to the clock signal F1.
The energy storage subunit 12 is configured to change the voltage when receiving the trigger signal TR1. For example, in some embodiments, energy storage subunit 12 is charged upon receipt of trigger signal TR1, and the voltage of energy storage subunit 12 increases. As another example, in other embodiments, energy storage subunit 12 discharges upon receipt of trigger signal TR1, and the voltage of energy storage subunit 12 decreases.
The comparing subunit 13 is configured to receive the first voltage V1 on the energy storage subunit 12 and receive the first reference voltage VREF. The first voltage V1 is the voltage across the energy storage subunit 12. The comparing subunit 13 is further configured to perform a timing operation when the first voltage V1 is not equal to the first reference voltage VERF, so as to output the timing signal T1. In some embodiments, the comparing subunit 13 performs the timing operation when the first voltage V1 is greater than the first reference voltage VREF. In other embodiments, the comparing subunit 13 performs the timing operation when the first voltage V1 is smaller than the first reference voltage VREF.
In another embodiment, as shown in FIG. 6, the timing unit 10 further includes a current mirror unit 14, a resistor subunit 15, and a reset subunit 16.
Wherein the current mirror unit 14 is connected to a first current source I1. The resistor subunit 15 is connected to the current mirror unit 14. The reset subunit 16 is connected to the comparing subunit 13 and the triggering subunit 11, respectively.
Specifically, the current mirror unit 14 is configured to output equal first and second currents based on the current of the first current source I1. Wherein the first current is used to change the voltage of the energy storage subunit 12 when the energy storage subunit 12 receives the trigger signal TR 1. For example, in some embodiments, the first current charges energy storage subunit 12 when energy storage subunit 12 receives trigger signal TR1 to change the voltage of energy storage subunit 12.
The resistor subunit 15 is configured to output the first reference voltage VREF based on the second current. By configuring the resistance value of the resistor subunit 13, the magnitude of the first reference voltage VREF can be configured.
The reset subunit 16 is configured to output a reset signal to the trigger subunit 11 when the comparing subunit 13 stops performing the timing operation, so that the trigger subunit 11 stops outputting the trigger signal TR1.
In some embodiments, the trigger subunit 11 is specifically configured to start outputting the trigger signal TR1 each time the frequency-divided signal F2 is on a rising edge. And, the first current is configured to charge the energy storage subunit 12.
In this embodiment, when the frequency-divided signal F2 is on the rising edge, the trigger subunit 11 starts outputting the trigger signal TR1. The first current begins to charge the energy storage subunit 12. And at this time, the voltage of the energy storage subunit 12 is zero and less than the first reference voltage VREF. The comparing subunit 13 starts to perform the timing operation, and outputs the timing signal T1. At the same time, the reset subunit 16 receives the timing signal T1, and the reset subunit 16 does not output a reset signal. In turn, as the first current output by the current mirror unit 14 charges the energy storage subunit 12, the voltage of the energy storage subunit 12 gradually increases. When the voltage of the energy storage subunit 12 increases to not less than the first reference voltage VREF, the comparing subunit 13 stops performing the timing operation and stops outputting the timing signal T1. At this time, the reset subunit 16 does not receive the timing signal T1, and the reset subunit 16 outputs the reset signal to the trigger subunit 11, so that the trigger subunit 11 stops outputting the trigger signal TR1. The energy storage subunit 12 stops being charged by the first current and rapidly discharges to zero voltage. The above process is re-executed until the rising edge of the next divided signal F2 comes again. In this embodiment, the time period between when the energy storage subunit 12 starts to be charged and when it stops to be charged corresponds to the first preset time period in the above embodiment.
Note that the same structure as that of the timer unit 10 shown in fig. 5 and 6 can be applied to the clock signal generation circuit 100 shown in fig. 1. The specific implementation process may refer to the detailed description of the above embodiments, and will not be repeated here.
Referring to fig. 7, one circuit configuration of the timing unit 10 is schematically shown in fig. 7.
In one embodiment, as shown in FIG. 7, the trigger subunit 11 includes a D-flip-flop U1.
The data input end of the D flip-flop U1 is connected to the first power supply VC1, and the inverted data output end of the D flip-flop U1 is connected to the energy storage subunit 12. When the trigger subunit 11 is connected with the oscillating unit 40, the clock input end of the D flip-flop U1 is connected with the oscillating unit 40, and the clock input end of the D flip-flop U1 inputs a clock signal F1 (not shown); when the trigger subunit 11 is connected to the frequency dividing unit 50, the clock input terminal of the D flip-flop U1 is connected to the frequency dividing unit 50, and the clock input terminal of the D flip-flop U1 inputs the frequency dividing signal F2 (as shown in fig. 7).
Specifically, the data output terminal of the D flip-flop U1 remains output at the high level until the rising edge of the frequency-divided signal F1 does not arrive, and the trigger signal TR1 is not output corresponding to the data output terminal of the D flip-flop U1 in this embodiment. When the rising edge of the frequency-divided signal F1 arrives, the data output terminal of the D flip-flop U1 outputs a level opposite to the first power supply VC1, that is, a low level, and in this embodiment, the data output terminal corresponding to the D flip-flop U1 outputs the trigger signal TR1, and the trigger signal TR1 is a low level signal.
In one embodiment, the energy storage subunit 12 includes a first switch Q1 and a first capacitor C1.
The first end of the first switching tube Q1 is connected to the trigger subunit 11, the second end of the first switching tube Q1 and the second end of the first capacitor C1 are both grounded GND, and the third end of the first switching tube Q1 is connected to the first end of the first capacitor C1 and the comparing subunit 13, respectively.
Specifically, when the data output terminal of the D flip-flop U1 does not output the trigger signal TR1, the voltage of the first terminal of the first switching tube Q1 is at a high level, the first switching tube Q1 remains on, and the first capacitor C1 is shorted. When the data output terminal of the D flip-flop U1 outputs the trigger signal TR1, the voltage at the first terminal of the first switching tube Q1 is at a low level, the first switching tube Q1 remains turned off, and the first capacitor C1 may start to be charged.
In this embodiment, the first switching transistor Q1 is taken as an NMOS transistor as an example. The grid electrode of the NMOS tube is a first end of the first switching tube Q1, the source electrode of the NMOS tube is a second end of the first switching tube Q1, and the drain electrode of the NMOS tube is a third end of the first switching tube Q1.
In addition, the first switching transistor Q1 may be any controllable switch, such as an Insulated Gate Bipolar Transistor (IGBT) device, an Integrated Gate Commutated Thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a Silicon Controlled Rectifier (SCR) device, a junction gate field effect transistor (JFET) device, a MOS Controlled Thyristor (MCT) device, or the like.
In one embodiment, the resistor subunit 15 includes a first resistor R1.
The first end of the first resistor R1 is connected to the comparing subunit 13, and the second end of the first resistor R1 is grounded GND.
Specifically, when the second current flows through the first resistor R1, a fixed voltage is generated across the first resistor R1. The fixed voltage is the product of the resistance value of the first resistor R1 and the second current.
In one embodiment, the current mirror unit 14 includes a second switching tube Q2, a third switching tube Q3, and a fourth switching tube Q4.
The first end of the second switching tube Q2 is connected to the third end of the second switching tube Q2, the first end of the third switching tube Q3, the first end of the fourth switching tube Q4 and the negative electrode of the first current source I1, the positive electrode of the first current source I1 is grounded GND, the second end of the second switching tube Q2, the second end of the third switching tube Q3 and the second end of the fourth switching tube Q4 are all connected to the second power supply VC2, the third end of the third switching tube Q3 is connected to the energy storage subunit 12 and the comparison subunit 13, and the third end of the fourth switching tube Q4 is connected to the resistor subunit 15 and the comparison subunit 13.
Specifically, the first current source I1 is configured to generate a current flowing through the second switching transistor Q2. Then, since the third switching tube Q3 and the fourth switching tube Q4 are mirror images of the second switching tube Q2, the current magnitude of the third switching tube Q3 and the fourth switching tube Q4 is the same as the current magnitude on the second switching tube Q2. The current on the third switching tube Q3 is a first current, and the first current is used to charge the first capacitor C1 when the first switching tube Q1 is turned off. The current on the fourth switching tube Q4 is a second current, and the second current flows through the first resistor R1 to generate the first reference voltage VREF.
It can be understood that in this embodiment, taking the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 as the same switching tube, that is, the equivalent internal resistances of the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are equal, the first current and the second current are equal to the current on the first current source I1. In other embodiments, if the equivalent internal resistances of the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are not equal, the current of the first current source I1, the ratio between the first current and the second current, and the ratio between the equivalent internal resistances of the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are in inverse proportion. For example, the ratio of the equivalent internal resistances of the second switching tube Q2 and the third switching tube Q3 is 1:2, the ratio of the current of the first current source I1 to the first current is 2:1, whereby a first current twice the current of the first current source I1 is obtained.
In this embodiment, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are exemplified as NMOS tubes. The grid electrode of the NMOS tube is the first end of the second switching tube Q2 (the third switching tube Q3 and the fourth switching tube Q4), the source electrode of the NMOS tube is the second end of the second switching tube Q2 (the third switching tube Q3 and the fourth switching tube Q4), and the drain electrode of the NMOS tube is the third end of the second switching tube Q2 (the third switching tube Q3 and the fourth switching tube Q4).
In addition, the second, third and fourth switching transistors Q2, Q3 and Q4 may be any controllable switch, such as an Insulated Gate Bipolar Transistor (IGBT) device, an Integrated Gate Commutated Thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a Silicon Controlled Rectifier (SCR) device, a junction gate field effect transistor (JFET) device, a MOS Controlled Thyristor (MCT) device, and the like.
In one embodiment, the comparing subunit 13 includes a comparator U2 and a schmitt trigger U3.
The first input end of the comparator U2 inputs the first reference voltage VREF, the second input end of the comparator U2 is connected with the energy storage subunit 12, the second input end of the comparator U2 is used for inputting the first voltage V1, the output end of the comparator U2 is connected with the input end of the schmitt trigger U3, and the output end of the schmitt trigger U4 is used for outputting the timing signal T1. The reset terminal of the comparator U2 is also connected to the trigger subunit 11. In this embodiment, the non-inverting input terminal of the comparator U2 is taken as a first terminal, and the inverting input terminal is taken as a second terminal as an example.
Specifically, when the first current starts to charge the first capacitor C1, the first voltage V1 is smaller than the first reference voltage VREF, the comparator U2 outputs a high level, and the schmitt trigger U3 also outputs a high level. At this time, the output of the timing signal T1 is started corresponding to the schmitt trigger U3. The schmitt trigger U3 keeps outputting the high level until the voltage of the first capacitor C1 is charged to be equal to the first reference voltage VREF, i.e., the schmitt trigger U3 keeps outputting the timing signal T1.
Until the voltage of the first capacitor C1 is charged to be equal to the first reference voltage VREF, that is, the first voltage V1 is equal to the first reference voltage VREF, the comparator U2 outputs a low level, and the schmitt trigger U3 also outputs a low level. At this time, the output of the timing signal T1 is stopped corresponding to the schmitt trigger U3.
In this embodiment, the hysteresis characteristic of the schmitt trigger U3 can be used to suppress the interference by providing the schmitt trigger U3. In other embodiments, the comparison subunit 13 may also comprise only the comparator U2.
In one embodiment, reset subunit 16 includes inverter U4, delay U5, and NAND gate U6.
The input end of the inverter U4 is connected to the comparing subunit 13 and the input end of the delay U5, the output end of the inverter U4 is connected to the first input end of the nand gate U6, the output end of the delay U5 is connected to the second input end of the nand gate U6, and the output end of the nand gate U6 is connected to the triggering subunit 11.
Specifically, when the schmitt trigger U3 outputs the timing signal T1, that is, the schmitt trigger U3 outputs a high level, the inverter U4 outputs a low level, and the nand gate U6 outputs a high level. The high level cannot reset D flip-flop U1. At this time, no reset signal is output corresponding to the reset subunit 16.
When the schmitt trigger U3 does not output the timing signal T1, i.e., the schmitt trigger U3 outputs a low level, the inverter U4 outputs a high level and the nand gate U6 outputs a low level. The low level cannot reset D flip-flop U1. At this time, no reset signal is output corresponding to the reset subunit 16.
Second, when the D flip-flop U1 is reset, the output terminal of the D flip-flop U1 outputs a high level again. On the one hand, the high level acts on the first switching tube Q1 to turn on the first switching tube Q1 and short-circuit the first capacitor C1, and the first capacitor C1 is also rapidly discharged through the internal resistance of the first switching tube Q1; on the other hand, the high level acts on the reset terminal of the comparator U2 to reset the comparator U2, thereby keeping the comparator U2 output low level. Until the arrival of the next rising edge of the divided signal F2.
The principle of the circuit configuration shown in fig. 7 will be explained again with reference to schematic diagrams of signals in the clock signal generation circuit 100 shown in fig. 8 and 9.
Referring to fig. 7 and 8 together, at time t21, the rising edge of the divided signal F2 arrives. The D flip-flop U1 outputs a trigger signal, i.e., a low level. The first switching transistor Q1 is turned off and the first capacitor C1 starts to be charged. The first voltage V1 gradually increases. At this time, since the first voltage V1 is smaller than the first reference voltage VREF, both the comparator U1 and the schmitt trigger U2 output high levels. The timing signal T1 is at a high level, corresponding to the schmitt trigger U2 starting to output the timing signal T1.
Until time t22, the first voltage V1 increases to be equal to the first reference voltage VREF. At this time, both the comparator U1 and the schmitt trigger U2 output low levels. Nand gate U6 also outputs a low level to reset D flip-flop U1. The D trigger U1 stops outputting the trigger signal, that is, the D trigger U1 outputs a high level, the first end of the first switching tube Q1 is a high level, the first switching tube Q1 is turned on, and the first capacitor C1 discharges through the first switching tube Q1. The first voltage V1 decreases to zero. At the same time, the reset terminal of the comparator U1 is also input with a high level, and the comparator U1 is reset. At this time, even if the first voltage V1 is smaller than the first reference voltage VREF, the comparator U1 keeps outputting a low level.
Until time t24, when the rising edge of the frequency-divided signal F2 arrives again, the D flip-flop U1 outputs the trigger signal again. And the above procedure is repeated.
The time period between the time t21 and the time t22 is the first preset time period in the embodiment of the present application. Specifically, the first reference voltage VREF is: vref=r1×ip2 (1), where R1 is the resistance value of the first resistor R1, and IP2 is the second current. The voltage across the first capacitor C1 (i.e., the first voltage V1) is:(2) Wherein IP1 is a first current, C1 is a capacitance value of the first capacitor C1, and T is a time period during which the first capacitor C1 is charged. When the first capacitor C1 is charged to the first voltage V1 equal to the first reference voltage VREF, v1=vref (3). The first preset time period at this time is obtained by combining the formulas (1) (2) (3): tset=r1×c1×ip2/IP1 (4). The first preset duration can be determined by the capacitance of the first capacitor C1, the resistance of the first resistor R1, the first current and the second current according to the formula (4). Therefore, when the first capacitor C1, the first resistor R1, the first current source I1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are all selected, the first preset duration is a fixed duration.
Meanwhile, in this embodiment, the time period in which the frequency-divided signal F2 is at the high level shown in fig. 8 is the period between the time t21 and the time t 23. The frequency divided signal F2 is at the high level for a period of time longer than the first preset period of time. The logic unit 20 should output the first control sub-signal to the voltage conversion unit 30, so that the voltage conversion unit 30 reduces the voltage signal V1, and further the oscillating unit 40 reduces the frequency of the clock signal F1. The duration of the frequency-divided signal F2 at the high level also decreases. The above adjustment process is repeated until the time period of the frequency division signal F2 at the high level is equal to the first preset time period.
Fig. 9 shows a case where the time period of the frequency-divided signal F2 at the high level is less than the first preset time period. As shown in fig. 9, the divided signal F2 is at the high level for a period of time between the time t31 and the time t 32. And the first preset time period is a time period between the time t31 and the time t 33. The time period during which the frequency-divided signal F2 is at the high level is smaller than the first preset time period. At this time, the logic unit 20 should output the second control sub-signal to the voltage conversion unit 30, so that the voltage conversion unit 30 increases the voltage signal V1, and further the oscillating unit 40 increases the frequency of the clock signal F1. The duration of the frequency-divided signal F2 at the high level increases as well. The above adjustment process is repeated until the time period of the frequency division signal F2 at the high level is equal to the first preset time period.
Through the above process, the adjusting process of the frequency of the clock signal F1 is realized, which is beneficial to keeping the clock signal F1 stable.
Next, when the voltage conversion unit in the embodiment of the present application employs a charge pump, a calculation formula of the charge amount of the charge pump is: q=i2×d/c2 (5), where Q is the charge amount of the charge pump, I2 is the charge current or discharge current of the pumping capacitor in the charge pump, D is the charge time or discharge time, and c2 is the capacitance of the pumping capacitor. The voltage on the pumping capacitor is the voltage signal V1.
In this embodiment, the above adjustment of the voltage signal V1 is achieved in practical applications by adjusting the charge pump charge-discharge time. As can be seen from the above embodiments, the above adjustment process for the voltage signal V1 corresponds to: when the charging current of the pumping capacitor is too large, the charging time is reduced; when the charging current is excessively small, the charging time is increased. Therefore, the charge pump is in a dynamic smooth state, and Q is kept unchanged, so that the matching requirement on a current mirror arranged in the charge pump is not high, and the influence caused by process deviation can be effectively coped with.
In addition, for the charge pump phase-locked loop circuit in the related art, the voltage-controlled oscillator in the charge pump phase-locked loop circuit provides a pole, the output of the charge pump has a pole, and the charge pump phase-locked loop circuit is a bipolar point system, so that a more complex compensation circuit needs to be provided. Also, since the charge pump phase locked loop is essentially a discrete sampling system, it is generally required that the loop bandwidth be less than 1/10 of the input frequency. Therefore, the lower the reference frequency input by the charge pump phase-locked loop is, the smaller the loop bandwidth is required, and the compensation capacitance in the compensation circuit is required to be increased as the reference frequency is reduced. In low power consumption systems, the system generally only provides a high-precision low-power consumption low-frequency clock, so that the use of the charge pump phase-locked loop has a great limitation. I.e. either the cost is increased to increase the high precision, high power consumption high frequency reference clock or a large compensation capacitor is required, which also increases the chip cost.
For the clock signal generating circuit provided by the application, since the clock frequency F1 is corrected in each period, there is no phase accumulation process, and thus the pole provided by the voltage-controlled oscillator can be eliminated. Therefore, the whole system is a single-pole system, the stability problem is avoided, an additional compensation circuit is not required to be arranged, the cost is reduced, unnecessary power consumption and loss are reduced, and the stability of a clock signal is improved.
The embodiment of the present application further provides a charge pump phase-locked loop circuit, which includes the clock signal generating circuit 100 in any embodiment of the present application.
The embodiment of the application also provides a chip which comprises the charge pump phase-locked loop circuit in any embodiment of the application.
The embodiment of the application also provides a terminal device, which comprises the chip in any embodiment of the application.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (15)

1. A clock signal generation circuit, comprising:
a timing unit for receiving the clock signal and performing at least one timing operation in response to the clock signal, wherein a duration of each timing operation is a first preset duration, and outputting a timing signal when the timing unit performs the timing operation;
the logic unit is connected with the timing unit and is used for receiving the clock signal and the timing signal, determining the first preset duration based on the timing signal and outputting a control signal based on the first duration of the clock signal at the first level and the first preset duration;
the logic unit is further configured to output the first control sub-signal when the first time period is longer than the first preset time period, and output the second control sub-signal when the first time period is shorter than the first preset time period;
a voltage conversion unit connected to the logic unit, the voltage conversion unit configured to receive the control signal to output a voltage signal, and to decrease the voltage signal when the first control sub-signal is received, and to increase the voltage signal when the second control sub-signal is received;
The oscillation unit is respectively connected with the timing unit, the logic unit and the voltage conversion unit, and is used for receiving the voltage signal to output the clock signal, increasing the frequency of the clock signal when the voltage signal increases, and decreasing the frequency of the clock signal when the voltage signal decreases.
2. The clock signal generation circuit of claim 1, wherein the timing unit is further configured to start timing each time the clock signal is at a first edge and stop timing when the first preset time period is counted to perform a timing operation.
3. The clock signal generation circuit of claim 1, wherein the timing unit comprises:
a trigger subunit connected to the oscillation unit, the trigger subunit being configured to receive the clock signal and output a trigger signal in response to the clock signal;
the energy storage subunit is connected with the trigger subunit and is used for changing voltage when receiving the trigger signal;
the comparison subunit is respectively connected with the energy storage subunit and the logic unit, and is used for receiving the first voltage on the energy storage subunit and the first reference voltage, and executing the timing operation when the first voltage is not equal to the first reference voltage so as to output the timing signal.
4. A clock signal generation circuit according to claim 3, wherein the timing unit further comprises:
a current mirror unit connected to a first current source for outputting equal first and second currents based on the current of the first current source, wherein the first current is used to change the voltage of the energy storage subunit when the energy storage subunit receives the trigger signal;
a resistive subunit connected to the current mirror unit, the resistive subunit for outputting the first reference voltage based on the second current;
the reset subunit is respectively connected with the comparison subunit and the trigger subunit, and is used for outputting a reset signal to the trigger subunit when the comparison subunit stops executing the timing operation, so that the trigger subunit stops outputting the trigger signal.
5. A clock signal generation circuit according to claim 3, wherein the trigger subunit comprises a D-flip-flop;
the clock input end of the D trigger is connected with the oscillating unit, the data input end of the D trigger is connected with the first power supply, and the inverted data output end of the D trigger is connected with the energy storage subunit.
6. The clock signal generation circuit of claim 3, wherein the energy storage subunit comprises a first switching tube and a first capacitor;
the first end of the first switch tube is connected with the trigger subunit, the second end of the first switch tube and the second end of the first capacitor are grounded, and the third end of the first switch tube is connected with the first end of the first capacitor and the comparison subunit respectively.
7. A clock signal generation circuit according to claim 3, wherein the comparison subunit comprises a comparator and a schmitt trigger;
the first reference voltage is input to the first input end of the comparator, the second input end of the comparator is connected with the energy storage subunit, the output end of the comparator is connected with the input end of the Schmitt trigger, and the output end of the Schmitt trigger is used for outputting the timing signal.
8. The clock signal generation circuit of claim 4, wherein the current mirror unit comprises a second switching tube, a third switching tube, and a fourth switching tube;
the first end of the second switching tube is respectively connected with the third end of the second switching tube, the first end of the third switching tube, the first end of the fourth switching tube and the negative electrode of the first current source, the positive electrode of the first current source is grounded, the second end of the second switching tube, the second end of the third switching tube and the second end of the fourth switching tube are respectively connected with a second power supply, the third end of the third switching tube is respectively connected with the energy storage subunit and the comparison subunit, and the third end of the fourth switching tube is respectively connected with the resistor subunit and the comparison subunit.
9. The clock signal generation circuit of claim 4, wherein the resistive subcell comprises a first resistor;
the first end of the first resistor is connected with the comparison subunit, and the second end of the first resistor is grounded.
10. The clock signal generation circuit of claim 4, wherein the reset subunit comprises an inverter, a delay, and a nand gate;
the input end of the inverter is respectively connected with the comparing subunit and the input end of the delayer, the output end of the inverter is connected with the first input end of the NAND gate, the output end of the delayer is connected with the second input end of the NAND gate, and the output end of the NAND gate is connected with the triggering subunit.
11. The clock signal generation circuit according to claim 1, wherein the clock signal generation circuit further comprises a frequency division unit;
the frequency dividing unit is connected between the timing unit and the oscillating unit, and is also connected between the logic unit and the oscillating unit;
the frequency dividing unit is used for dividing the frequency of the clock signal and outputting a frequency dividing signal, wherein the frequency dividing signal is respectively input to the timing unit and the logic unit, and the frequency of the frequency dividing signal is one-half of the frequency integer of the clock signal;
The timing unit is further configured to perform at least one timing operation in response to the divided signal;
the logic unit is further configured to output a control signal based on a duration of the frequency-divided signal at the first level and the first preset duration.
12. The clock signal generation circuit according to any one of claims 1 to 11, wherein the voltage conversion unit is a charge pump and/or the oscillation unit is a voltage controlled oscillator.
13. A charge pump phase locked loop circuit comprising a clock signal generation circuit as claimed in any one of claims 1 to 12.
14. A chip comprising the charge pump phase locked loop circuit of claim 13.
15. A terminal device comprising a chip as claimed in claim 14.
CN202310293209.0A 2023-03-24 2023-03-24 Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment Active CN116032253B (en)

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