CN113709935A - Dimming control circuit and dimming control chip thereof - Google Patents
Dimming control circuit and dimming control chip thereof Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/10—Controlling the intensity of the light
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
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- H05B45/10—Controlling the intensity of the light
- H05B45/14—Controlling the intensity of the light using electrical feedback from LEDs or from LED modules
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/36—Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI]
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Abstract
The application provides a dimming control circuit and a dimming control chip thereof, wherein the dimming control circuit comprises a starting point control unit, a period control unit and a control logic unit; the starting point control unit is used for receiving the load voltage, generating a timing starting signal according to a preset reference voltage and the load voltage and transmitting the timing starting signal to the period control unit; the period control unit is used for sending a switching period ending signal to the control logic unit after a first time length from a time point of receiving the timing starting signal; the control logic unit is used for generating a disconnection driving signal when the load voltage reaches a peak value, and the disconnection driving signal is used for controlling the power control device in the load circuit to be disconnected; and after the power control device is disconnected, generating a closing driving signal according to the received switching period ending signal, wherein the closing driving signal is used for controlling the power control device to be closed, so that the ripple wave is eliminated.
Description
Technical Field
The application relates to the technical field of dimming control, in particular to a dimming control circuit and a dimming control chip thereof.
Background
With the advent of an intelligent society, people have not satisfied common illumination of LEDs, and urgent needs are made for intelligent illumination, so that intelligent dimming of LEDs is generated.
When the current LED intelligent dimming control circuit adopts Discontinuous Conduction (mode) (dcm) mode to perform dimming, the dimming output current and the time length T are adjustedCRMAnd a time length TDCMIs linearly related, wherein the time length T in the conventional dimming control circuitCRMFor the time period from the switch closure to the load current falling from maximum to 0, the time length TDCMIn the time period from the last closing to the next closing of the switch, in the dimming mode, because the inductance current in the load circuit can generate oscillation when discharging to 0, the initial values of the load current are inconsistent when the switch is closed in the subsequent dimming process, and the time length T from the initial point to the maximum time of reducing the subsequent load current to 0 is ensuredCRMAnd the length of time T from the last closure of the switch to the next closureDCMAll the current values are inconsistent, so that the dimming output current shows nonlinear fluctuation change, and the current ripple phenomenon occurs.
Disclosure of Invention
An object of the embodiment of the present application is to provide a dimming control circuit and a dimming control chip thereof, so as to solve a ripple phenomenon existing in a current dimming manner.
In a first aspect, the present invention provides a dimming control circuit, comprising: a starting point control unit, a period control unit and a control logic unit; the starting point control unit is used for receiving load voltage, generating a timing starting signal according to preset reference voltage and the load voltage and transmitting the timing starting signal to the period control unit; the cycle control unit is used for sending a switching cycle ending signal to the control logic unit after a first time length from a time point of receiving a timing starting signal; the control logic unit is used for generating a disconnection driving signal when the load voltage reaches a peak value, and the disconnection driving signal is used for controlling a power control device in a load circuit to be disconnected; and after the power control device is switched off, generating a closing driving signal according to the received switching period ending signal, wherein the closing driving signal is used for controlling the power control device to be closed.
In the light modulation control circuit designed above, the period control unit sends a switching period end signal to the control logic unit after a first time length from a time point when the timing start signal transmitted by the start point control unit is received. The control logic unit disconnects a power control device of a load circuit when load voltage is a peak value, after the power control device is disconnected, the power control device is closed according to a switching period ending signal sent by a period control unit, and because a timing starting signal is generated by a starting point control unit according to the received load voltage and a preset reference voltage, and because the preset reference voltage is fixed, the voltage value of the load voltage reaching the preset reference voltage in each period is the same, the values of load current are the same when the timing starting signal is generated in each switching period, and therefore the timing starting points of each period are the same; meanwhile, the first time length is fixed, and the timing starting point is also fixed, so that the time period T of the first time length from the time point of the timing starting signalDCMIs also fixed; in addition, in each switching period, the load current is linearly increased when the power control device is closed, the load current is linearly decreased after the power control device is disconnected, and the peak value of the load current is fixed because the control logic unit disconnects the power control device of the load circuit when the load voltage is at the peak value, so that the time length T from the starting point of timing to the time when the load current is at the peak value and then to the time when the load current is reduced to 0 from the maximum valueCRMIs also fixed due to TCRMIs stationary, TDCMAnd is also fixed, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed and does not fluctuate, and the ripple is eliminated.
In an optional implementation manner of the first aspect, the starting point control unit is further configured to send an inverted level signal of the timing starting signal to the period control unit at a time when the load current decreases from a maximum value to 0; the period control unit is further configured to send the switching period end signal to the control logic unit after a second time length from a time point when the inverted level signal of the timing start signal is received, where the second time length is equal to a difference between the first time length and a time length from generation of the timing start signal to generation of the inverted level signal.
In an optional implementation manner of the first aspect, the dimming control circuit further includes a demagnetization detecting unit, and the demagnetization detecting unit is connected to the starting point control unit; the demagnetization detection unit is used for receiving the load current of the load circuit, generating a demagnetization finishing signal at the moment when the load current is reduced from the maximum value to 0, and transmitting the demagnetization finishing signal to the starting point control unit; and the starting point control unit is used for sending an inverted level signal of the timing starting signal to the period control unit according to the demagnetization finishing signal, the preset reference voltage and the load voltage.
In an optional implementation of the first aspect, the starting point control unit comprises: a timing comparator, a first NOR gate, a second NOR gate and a first inverter; the positive phase input end of the timing comparator is used for receiving the load voltage, the inverting input end of the timing comparator is used for receiving the preset reference voltage, the output end of the timing comparator is connected with the first input end of the first NOR gate, the output end of the first NOR gate is respectively connected with the input end of the first phase inverter and the first input end of the second NOR gate, the second input end of the second NOR gate is connected with the demagnetization detection unit, the output end of the second NOR gate is connected with the second input end of the first NOR gate, and the output end of the first phase inverter is connected with the period control unit.
In an optional implementation of the first aspect, the period control unit comprises a period control comparator and a logic circuit; the logic circuit is used for controlling the period control comparator to stop working when the timing starting signal is received; and driving the period control comparator to work when receiving the inverted level signal of the timing starting signal, so that the period control comparator sends the switching period ending signal to the control logic unit after the second time length.
In an optional implementation of the first aspect, the period control unit is further configured to receive a dimming signal; and the period control unit is used for adjusting the second time length according to the dimming signal so as to adjust the switching period length of the power control device and further adjust the brightness of the load circuit.
In an optional implementation manner of the first aspect, the period control unit further includes a pulse generation circuit, a period control comparator, a switching circuit, a first charge and discharge circuit, and a second charge and discharge circuit; the output end of the starting point control unit is respectively connected with the input ends of the pulse generation circuit and the logic circuit, the output end of the logic circuit is respectively connected with the enabling end of the period control comparator and the switch circuit, the first end of the switch circuit is used for being connected with a reference signal source, the second end of the switch circuit is respectively connected with the inverting input end of the period control comparator and the first charging and discharging circuit, the non-inverting input end of the period control comparator is connected with the second charging and discharging circuit and receives the dimming signal, the output end of the period control comparator is connected with the control logic unit, and the output end of the pulse generation circuit is respectively connected with the first charging and discharging circuit and the second charging and discharging circuit; the pulse generating circuit is used for sending pulse signals to the first charging and discharging circuit and the second charging and discharging circuit according to the timing starting signal; the first charging and discharging circuit is used for discharging when the pulse signal is received so as to reset the voltage of the inverting input end of the period control comparator connected with the first charging and discharging circuit; and the second charging and discharging circuit is used for discharging when the pulse is received and charging according to the received dimming signal after discharging so as to increase the voltage of the positive phase input end of the period control comparator connected with the second charging and discharging circuit.
In an optional implementation of the first aspect, the logic circuit comprises a second inverter; the input end of the second phase inverter is connected with the output end of the starting point control unit, and the output end of the second phase inverter is respectively connected with the enabling end of the period control comparator and the switch circuit.
Preferably, the switching circuit includes a third controllable switching tube, a control end of the third controllable switching tube is connected to an output end of the second phase inverter, a first end of the third controllable switching tube is connected to the external power supply, and a second end of the third controllable switching tube is connected to the inverting input end of the period control comparator and the first charging and discharging circuit.
Preferably, the first charge-discharge circuit includes a first controllable switch tube and a first capacitor, a second end of the third controllable switch tube is connected to the first end of the first capacitor and the first end of the first controllable switch tube, respectively, a second end of the first capacitor and the second end of the first controllable switch tube are grounded after being connected, and a control end of the first controllable switch tube is connected to the pulse generating circuit.
Preferably, the second charging and discharging circuit includes a second controllable switch tube and a second capacitor, the dimming signal is respectively connected to the positive input terminal of the period control comparator, the first terminal of the second capacitor, and the first terminal of the second controllable switch tube, the second terminal of the second controllable switch tube is connected to the second terminal of the second capacitor and then grounded, and the control terminal of the second controllable switch tube is connected to the pulse generating circuit.
In an optional implementation manner of the first aspect, the dimming control circuit further includes a load peak control unit, an input terminal of the load peak control unit is configured to receive the load voltage, and an output terminal of the load peak control unit is connected to the control logic unit; the load peak control unit is used for sending a load peak signal to the control logic unit when the load voltage reaches a peak value, so that the control logic unit generates the disconnection driving signal according to the load peak signal; and when the load voltage is not a peak value, sending an opposite level signal of the load peak value signal to the control logic unit so that the control logic unit generates the closing driving signal according to the opposite level signal of the load peak value signal and the switching period ending signal.
In an optional implementation manner of the first aspect, the control logic unit includes a control logic circuit and a driving circuit, a first input terminal of the control logic circuit is connected to the output terminal of the period control unit, and a second input terminal of the control logic circuit is connected to the output terminal of the load peak control unit; and the output end of the control logic circuit is connected with the control end of the power control device through the driving circuit.
In an alternative implementation of the first aspect, the control logic circuit includes a third inverter, a fourth inverter, a fifth inverter, a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, and an and gate; the output end of the load peak control unit is respectively connected with the second input end of the second NAND gate and the first input end of the third NAND gate; a second input end of the third nand gate is connected with an output end of the fourth nand gate, an output end of the third nand gate is respectively connected with a first input end of the fourth nand gate and an input end of a fifth inverter, and an output end of the fifth inverter is connected with a second input end of the and gate; the first input end of the second NAND gate is connected with the output end of the first NAND gate, the output end of the second NAND gate is respectively connected with the second input end of the first NAND gate and the input end of the fourth inverter, the first input end of the first NAND gate is connected with the output end of the third inverter, the input end of the third inverter is connected with the output end of the period control unit, the output end of the fourth inverter is connected with the first input end of the AND gate, and the output end of the AND gate is connected with the input end of the driving circuit.
In a second aspect, the present invention provides a dimming control chip, which includes the dimming control circuit described in any one of the foregoing embodiments. According to the dimming control chip with the design, the dimming control chip comprises the dimming control circuit in any optional implementation mode of the first aspect, so that the designed dimming control chip can solve the ripple phenomenon generated by dimming in the current DCM mode, and the LED dimming effect is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a first structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 2 is a second structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 3 is a third structural diagram of a dimming control circuit according to an embodiment of the present application;
FIG. 4 is a schematic timing diagram of signals provided by an embodiment of the present application;
fig. 5 is a fourth structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 6 is a fifth structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 7 is a sixth structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 8 is a seventh structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 9 is an eighth structural diagram of a dimming control circuit according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a dimming control chip according to an embodiment of the present application.
Icon: 1-a dimming control chip; 10-a starting point control unit; 20-a period control unit; 2021-logic circuitry; 2022-pulse generation circuitry; 2023-a switching circuit; 2024-first charge and discharge circuit; 2025-second charge and discharge circuit; 30-a control logic unit; 301-control logic; 302-a driver circuit; 40-a demagnetization detection unit; 50-load peak control unit; 60-a signal conversion unit; 4-a load circuit; 41-load working circuit; 42-a power control device; 43-a load detection circuit; l1-timing comparator; l2-period control comparator; l3-load peak comparator; o1 — first nor gate; o2 — second nor gate; f1 — first inverter; f2 — second inverter; f3 — third inverter; f4 — fourth inverter; f5 — fifth inverter; f6 — sixth inverter; M0-MOS tube; m1-first controllable switch tube; m2-second controllable switch tube; m3-third controllable switch tube; c-capacitance; c1 — first capacitance; c2 — second capacitance; a1 — first nand gate; a2 — second nand gate; a 3-third nand gate; a 4-fourth nand gate; A5-AND gate; g1-inductance; q1-diode; iref-reference signal source.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
First embodiment
The present application provides a dimming control circuit, the dimming control circuit is used for dimming controlling a load in a load circuit, as shown in fig. 1, the load circuit 4 includes a load working circuit 41, a power control device 42 and a load detection circuit 43, which are connected in sequence, specifically, the load working circuit 41 may be an LED lamp, an inductor G1, a capacitor C and a diode Q1 as shown in fig. 1, the power control device 42 may be a MOS transistor M0 as shown in fig. 1, the load detection circuit 43 may be a resistor R1 as shown in fig. 1, an anode of the LED lamp is connected to a cathode of the diode Q1, a first end of the capacitor C and a power supply respectively, a cathode of the LED lamp is connected to a second end of the capacitor C and a first end of the inductor G1 respectively, a second end of the inductor G1 is connected to an anode of the diode Q1, an anode of the diode Q1 is also connected to a drain of the MOS transistor M0, a source of the MOS transistor M0 is grounded through the resistor R1, on the basis of the load circuit 4 of the circuit topology, the dimming control circuit designed by the application performs dimming on the LED lamp in the load working circuit 41. It should be noted that the above-described load circuit 4 is only one specific implementation structure of the present load circuit, and the dimming control circuit of the present application can dim any load circuit currently operating in DCM mode.
As shown in fig. 1, the dimming control circuit of the present application includes a starting point control unit 10, a period control unit 20, and a control logic unit 30, wherein an input terminal of the starting point control unit 10 is configured to receive a load voltage, an output terminal of the starting point control unit 10 is connected to an input terminal of the period control unit 20, an output terminal of the period control unit 20 is connected to an input terminal of the control logic unit 30, and an output terminal of the control logic unit 30 is connected to a control terminal of a power control device 42, that is, the control logic unit 30 is connected to a gate of a MOS transistor M0.
The above description to the starting point control unit 10 is for receiving a load voltage, and specifically, as shown in fig. 1, on the basis of the above load circuit 4, an input terminal of the starting point control unit 10 may be connected to a connection terminal of the load detection circuit 43 and the power control device 42, so as to sample a voltage of the connection terminal of the load detection circuit 43 and the power control device 42 to obtain a load voltage Vcs.
After receiving the load voltage Vcs, the start point control unit 10 generates a timing start signal Star according to the load voltage Vcs and a preset reference voltage Vref, and transmits the timing start signal Star to the period control unit 20. As a possible embodiment, the starting point control unit 10 sends a timing start signal Star to the period control unit 20 when the load voltage Vcs is greater than the preset reference voltage Vref; as another possible embodiment, the starting point control unit 10 sends the timing start signal Star to the cycle control unit in a case where the load voltage Vcs is less than the preset reference voltage Vref.
The cycle control unit 20 receives the timer start signal Star, and then transmits a switching cycle end signal to the control logic unit 30 after a first time period from a time point at which the timer start signal Star is received.
The control logic unit 30 generates a switch-off drive signal when the load voltage Vcs reaches a peak value, which is transmitted to the power control device 42, so that the power control device 42 is switched off; the control logic unit 30 generates a close driving signal according to the received switching cycle end signal after the power control device 42 is opened, and the close driving signal is transmitted to the power control device 42, so that the power control device 42 is switched from being opened to being closed.
Because the dimming control circuit designed by the application is directed to the discontinuous conduction mode, in the discontinuous conduction mode, the power control device 42 is turned on and off, when the power control device 42 is turned on, because the load working circuit 41 is internally provided with the inductor G1 and the capacitor C, the load current Ics is gradually increased from the turning-on of the power control device 42 until the turning-off of the power control device 42, after the turning-off of the power control device 42, the load current Ics is gradually decreased from the maximum, and because the load working circuit 41 is internally provided with the inductor G1 and the capacitor C, the load current Ics oscillates after being decreased to 0.
In the dimming control circuit designed as described above, assuming that in the initial state, the power control device 42 is closed, and the load current Ics is gradually increased, so that the load voltage Vcs is gradually increased, taking a scenario that the load voltage Vcs is greater than the preset reference voltage Vref and then the timing start signal is output as an example, in the process that the load voltage Vcs is gradually increased, when the load voltage Vcs is greater than the preset reference voltage Vref, the start point control unit 10 generates the timing start signal and sends the timing start signal to the period control unit 20, and the period control unit 20 starts timing from a time point when the timing start signal is received.
Since the power control device 42 is closed, the load current Ics is continuously increased, the load voltage Vcs is also continuously increased, and the control logic unit 30 controls the power control device 42 to be opened when the load voltage Vcs is at a peak value.
After the power control device 42 is turned off, the load current Ics gradually decreases, and the load voltage Vcs jumps to 0, the period control unit 20 starts timing from a time point when the timing start signal is received, and sends a switching period end signal to the control logic unit 30 after a first time length after the timing starts, so that the control logic unit 30 converts the turned-off power control device 42 into a closed state according to the switching period end signal, thereby re-closing the power control device 42 and entering a next period.
After the power control device 42 enters the next cycle, the load current Ics and the load voltage Vcs continuously increase, and when the load voltage Vcs is greater than the preset reference voltage Vref, the starting point control unit 10 generates a timing starting signal again and sends the timing starting signal to the cycle control unit 20 to start timing, so that the above processes are repeated.
In the above process, the timing is started from the time point when the period control unit 20 receives the timing start signal, that is, the timing start point is the time point when the period control unit 20 receives the timing start signal.
The timing start signal is generated according to the load voltage and the preset reference voltage, and in each switching period, the load voltage linearly increases when the power control device 42 is closed, and decreases to 0 from the maximum after the power control device 42 is disconnected, so that the voltage value at which the load voltage reaches the preset reference voltage in each period is the same, and the load current value at the time point generated by the timing start signal in each period is the same.
Since the timing start points of each period are the same, the period control unit 20 sends a switch period end signal after the first time length from the time point of receiving the timing start signal, so that the control logic unit 30 controls the power control device 42 to be turned off, and since the first time length is fixed and the timing start point is also fixed, according to the present embodiment, the time length T from the timing start point to the time when the next period of the power control device 42 is turned on is setDCMAnd is also fixed.
Since the control logic unit 30 controls the power control device 42 to turn off when the load voltage reaches the peak value in the present scheme, the load current Ics linearly increases to reach the fixed peak value after the power control device 42 is closed in each switching period, and then the power control device 42 turns off, and the load current Ics decreases from the fixed peak value to 0 and then oscillates.
Since the load current values at the timing start point of each cycle are all the same, the peak value of the load current Ics is also fixed, and the load current Ics is linearly varied before decreasing from the maximum to 0, the time length T from the timing start point to the time point at which the load current Ics decreases from the maximum to 0CRMIs stationary.
On the basis of the above, due to TCRMIs stationary, TDCMAlso fixed, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed without fluctuating, i.e. the ripple is eliminated.
In the dimming control circuit designed as described above, in this embodiment, the period control unit 20 sends a switching period end signal to the control logic unit 30 after receiving a first time length from a time point of the timing start signal Star transmitted by the start point control unit 10. The control logic unit 30 turns off the power control device 42 of the load circuit 4 when the load voltage is a peak value, after the power control device 42 is turned off, the power control device 42 is turned on according to the switching cycle end signal sent by the cycle control unit 20, since the timing start signal Star is generated by the start point control unit 10 according to the received load voltage and the preset reference voltage, and since the preset reference voltage Vref is fixed, the voltage value of the load voltage Vcs reaching the preset reference voltage Vref in each cycle is the same, so that the value of the load current Ics is the same when the timing start signal Star is generated in each switching cycle, and thus the timing start point of each cycle is the same; at the same time, since the first time length is fixed and the timing start point is also fixed, the time period T of the first time length from the time point of the timing start signal Star is setDCMIs also fixed; in addition, in each switching cycle, the load current Ics is linearly increased when the power control device 42 is closed, the load current Ics is linearly decreased after the power control device 42 is turned off, and since the control logic unit 30 turns off the power control device 42 of the load circuit 4 when the load voltage is at a peak, the peak value of the load current Ics is fixed, so that the time length T from the start of timing to when the load current Ics is at a peak to when the load current Ics is decreased from a maximum to 0CRMIs also fixed due to TCRMIs stationary, TDCMAnd is also fixed, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed and does not fluctuate, and the ripple is eliminated.
In an alternative embodiment of this embodiment, the starting point control unit 10 is further configured to send an inverted level signal of the timing start signal to the period control unit 20 at a time when the load current decreases from the maximum value to 0, for example, if the timing start signal is a high level signal, the inverted level signal is a low level signal; assuming that the timing start signal is a low level signal, the inverted level signal is a high level signal.
The cycle control unit 20 sends the switching cycle end signal to the control logic unit 30 after a second time period from the time point of receiving the inverted level signal, and since the inverted level signal is generated at the time point of the load current Ics decreasing from the maximum to 0, the time period from the generation of the timing start signal to the generation of the inverted level signal is the aforementioned TCRMI.e. the second time length T is equal to the first time length TDCM-TCRM。
As a possible embodiment, as shown in fig. 2, the dimming control circuit further includes a demagnetization detecting unit 40, the demagnetization detecting unit 40 is connected to the starting point control unit 10, and is configured to send a demagnetization completion signal to the starting point control unit 10 at a time when the load current Ics is decreased from the maximum to 0, and the starting point control unit 10 sends an inverted level signal of the timing start signal Star to the period control unit 20 according to the demagnetization completion signal.
As a possible embodiment, the starting point control unit 10 may be designed as a structure as shown in fig. 3 to implement the aforementioned functions.
The start point control unit 10 includes a timing comparator L1, a first nor gate O1, a second nor gate O2, and a first inverter F1.
A non-inverting input terminal of the timing comparator L1 is configured to receive the load voltage Vcs, an inverting input terminal of the timing comparator L1 is configured to receive the preset reference voltage Vref, an output terminal of the timing comparator L1 is connected to a first input terminal of the first nor gate O1, an output terminal of the first nor gate O1 is connected to an input terminal of the first inverter F1 and a first input terminal of the second nor gate O2, a second input terminal of the second nor gate O2 is connected to the demagnetization detecting unit 40, an output terminal of the second nor gate O2 is connected to a second input terminal of the first nor gate O1, and an output terminal of the first inverter F1 is connected to the period control unit 20.
The start point control unit 10 with the above structure, as shown in the timing diagram of fig. 4, takes the timing start signal as an example of a high level signal, and assumes that the timing start signal is generated when the load voltage Vcs is greater than the preset reference voltage Vref, the non-inverting input terminal of the timing comparator L1 receives the load voltage Vcs, and when the load voltage Vcs at the non-inverting input terminal is greater than the preset reference voltage Vref at the inverting input terminal, the timing comparator L1 sends a high level signal to the first input terminal of the first nor gate O1. After the first nor gate O1 receives the high signal, the first nor gate O1 outputs a low signal to the first inverter F1, and the low signal is inverted by the first inverter F1 to generate a high signal, thereby generating the timing start signal.
When the load current Ics decreases from the maximum to 0, the second input terminal of the second nor gate O2 receives a demagnetization completion signal, which changes from a low level to a high level signal at the time when the load current Ics decreases from the maximum to 0, the second nor gate O2 outputs a low level signal to the second input terminal of the first nor gate O1, and when the load current is 0, the load voltage Vcs is also 0, which is smaller than the preset reference voltage Vref, at this time, the timing comparator L1 outputs a low level signal, the first input terminal and the second input terminal of the first nor gate O1 both input a low level signal, and then the first nor gate O1 outputs a high level signal to the first inverter F1, and the first inverter F1 inverts the high level signal to output a low level signal, thereby generating an inverted level signal of the timing start signal.
In an alternative embodiment of the present embodiment, the period control unit 20 may further receive a dimming signal, and the period control unit 20 may adjust the second time length T according to the dimming signal, so as to adjust the switching period length of the power control device 42, so as to adjust the brightness of the load circuit 4.
As a possible embodiment, the cycle control unit 20 may be designed in a structure as shown in fig. 5 to implement the aforementioned functions.
As shown in fig. 5, the period control unit 20 includes a logic circuit 2021, a pulse generating circuit 2022, a switching circuit 2023, a first charging/discharging circuit 2024, a second charging/discharging circuit 2025, and a period control comparator L2.
The output terminal of the initial point control unit 10 is connected to the pulse generating circuit 2022 and the input terminal of the logic circuit 2021, the output terminal of the logic circuit 2021 is connected to the enable terminal of the period control comparator L2 and the switch circuit 2023, the reference signal source Iref is connected to the inverting input terminal of the period control comparator L2 and the first charging and discharging circuit 2024 through the switch circuit 2023, the non-inverting input terminal of the period control comparator L2 and the second charging and discharging circuit 2025 are connected, the non-inverting input terminal of the period control comparator L2 receives the dimming signal, the output terminal of the period control comparator L2 is connected to the control logic unit 30, and the output terminal of the pulse generating circuit 2022 is connected to the first charging and discharging circuit 2024 and the second charging and discharging circuit 2025.
In the cycle control unit 20 having the above-described configuration, for example, the timing start signal is a high-level signal, and as shown in the timing chart of fig. 4, the timing start signal is transmitted to the pulse generating circuit 2022, so that the pulse generating circuit 2022 transmits the pulse signal Rset for a short time to the first charging and discharging circuit 2024 and the second charging and discharging circuit 2025, and the first charging and discharging circuit 2024 and the second charging and discharging circuit 2025 discharge according to the pulse signal Rset for a short time, where the discharge time is the same as the pulse duration.
As a possible implementation manner, as shown in fig. 6, the first charging and discharging circuit 2024 may include a first capacitor C1 and a first controllable switch M1, the second charging and discharging circuit 2025 may include a second capacitor C2 and a second controllable switch M2, and control terminals of the first controllable switch M1 and the second controllable switch M2 are both connected to the pulse generating circuit 2022, so that the first controllable switch M1 and the second controllable switch M2 are closed when receiving the short-time pulse signal Rset, thereby discharging the first capacitor C1 and the second capacitor C2.
After the first charging/discharging circuit 2024 discharges, the logic circuit 2021 controls the switch circuit 2023 and the reference signal source Iref to charge the first charging/discharging circuit 2024 according to the timing start signal.
As a possible implementation, as shown in fig. 6, the logic circuit 2021 may be a second inverter F2, the control switch circuit 2023 may be a third controllable switch tube M3, an input terminal of the second inverter F2 is connected to an output terminal of the starting point control unit 10, an output terminal of the second inverter F2 is connected to a control terminal of the third controllable switch tube M3, and the reference signal source Iref is connected to the first capacitor C1 through the third controllable switch tube M3, so that when the timing start signal is received, the second inverter F2 drives the third controllable switch tube M3 to close, so that the reference signal source Iref charges the first capacitor C1; specifically, in the case that the timing start signal is a high level signal, the first controllable switch transistor M1 and the second controllable switch transistor M2 may be NMOS transistors as shown in fig. 6, and the third controllable switch transistor M3 is a PMOS transistor; when the timing starting signal is a low level signal, the model of the controllable switch tube can be adaptively adjusted.
After the second charging/discharging circuit 2025 is discharged, the second charging/discharging circuit 2025 may be charged according to a received dimming signal, which is an external input.
As a possible implementation manner, as shown In fig. 5, 6, 8 and 9, the dimming control circuit may further include a signal conversion unit 60, where the signal conversion unit 60 is configured to receive the dimming signal and convert the dimming signal into a corresponding current signal In to charge the second charging and discharging circuit 2025.
According to the connection relationship, the first end of the second capacitor C2 can be connected to the signal conversion unit 60 to receive the current signal In corresponding to the dimming signal, so as to charge the second capacitor C2 according to the current signal In corresponding to the dimming signal.
The output terminal of the second inverter F2 is further connected to the enable terminal of the period control comparator L2, and the second inverter F2 controls the period control comparator L2 to be disabled according to the timing start signal when receiving the timing start signal, so that the period control comparator L2 sends the inverted level signal of the switching period end signal to the control logic unit 30.
When the inverted signal of the timing start signal Star is received by the second inverter F2, the second inverter F2 controls the period control comparator L2 to start operating and controls the third controllable switch M3 to open, so that the reference signal source Iref stops charging the first capacitor C1, and thus the voltage in the first capacitor C1, that is, the voltage at the inverted input terminal of the period control comparator L2, is fixed.
Since the period control comparator L2 outputs a high level signal when the voltage at the non-inverting input terminal is greater than or equal to the voltage at the inverting input terminal, the period control comparator L2 outputs a switching period end signal when the voltage of the second capacitor charged by the dimming signal is equal to or greater than the voltage at the inverting input terminal.
In the above-designed period control unit, since the period control comparator L2 starts to operate only when the inverted level signal of the timing start signal is generated, the time length from the start of operation to the time when the voltages of the positive phase input terminal and the negative phase input terminal are equal is the second time length T, and the time length when the voltages of the positive phase input terminal and the negative phase input terminal are equal depends on the time length when the voltage charged by the dimming signal to the second charging and discharging circuit 2025 reaches the voltage of the negative phase input terminal, the second time length T can be changed by changing the dimming signal, so as to adjust the switching period length of the power control device, thereby controlling the load current of the power control device at the next closing time, and thus adjusting the brightness of the load circuit.
As a possible implementation manner, as shown in fig. 7, the designed dimming control circuit further includes a load peak value control unit 50, an input terminal of the load peak value control unit 50 is used for receiving the load voltage, and an output terminal of the load peak value control unit 50 is connected to the control logic unit 30.
The load peak control unit 50 sends a load peak signal to the control logic unit 50 when the load voltage is a peak value, and sends an opposite level signal of the load peak signal to the control logic unit 50 when the load voltage is not a peak value, for example, when the load peak signal is a high level signal, the opposite level signal of the load peak signal is a low level signal; when the load peak signal is a low level signal, the opposite level signal of the load peak signal is a high level signal.
As a possible implementation manner, as shown in fig. 8 and 9, the load peak value control unit 50 may be a load peak value comparator L3, an inverting input terminal of the load peak value comparator L3 may receive the load voltage Vcs, and a non-inverting input terminal of the load peak value comparator L3 may receive the first dimming signal, so that the peak value of the load current may be adjusted by adjusting the first dimming signal, thereby adjusting the brightness of the LED lamp.
Specifically, as shown in fig. 8 and 9, the first dimming signal may be sent to the signal conversion unit 60, and the signal conversion unit 60 converts the first dimming signal into the corresponding voltage signal Vn, so as to transmit the voltage signal Vn corresponding to the first dimming signal to the non-inverting input terminal of the load peak comparator L3, so as to adjust the peak value of the load current. The first dimming signal may be the same as the dimming signal or different from the dimming signal.
In an alternative embodiment of this embodiment, as shown in fig. 8, the control logic unit 30 includes a control logic circuit 301 and a driving circuit 302, a first input terminal of the control logic circuit 301 is connected to the output terminal of the period control unit 20, a second input terminal of the control logic circuit 301 is connected to the output terminal of the load peak control unit 50, an output terminal of the control logic circuit 301 is connected to the driving circuit 302, and an output terminal of the driving circuit 302 is connected to the control terminal of the power control device 42.
When the control logic circuit 301 receives a load peak signal, the control logic circuit controls the driving circuit 302 to drive the power control device 42 to be switched off according to the load peak signal; when receiving the switching period end signal and the opposite level signal of the load peak signal, the driving circuit 302 is controlled to drive the power control device 42 to close according to the switching period end signal and the opposite level signal of the load peak signal.
As a possible implementation, as shown in fig. 9, the control logic circuit 301 includes a third inverter F3, a fourth inverter F4, a fifth inverter F5, a first nand gate a1, a second nand gate a2, a third nand gate A3, a fourth nand gate a4, and an and gate a 5;
the output end of the load peak control unit 50 is connected with the second input end of the second nand gate a2 and the first input end of the third nand gate A3, respectively, the second input end of the third nand gate A3 is connected with the output end of the fourth nand gate a4, the output end of the third nand gate A3 is connected with the first input end of the fourth nand gate a4 and the input end of the fifth inverter F5, and the output end of the fifth inverter F5 is connected with the second input end of the and gate a 5;
the first input end of the second nand gate a2 is connected with the output end of the first nand gate a1, the output end of the second nand gate a2 is connected with the second input end of the first nand gate a1 and the input end of the fourth inverter F4, the first input end of the first nand gate a1 is connected with the output end of the third inverter F3, the input end of the third inverter F3 is connected with the output end of the period control unit 20, and the output end of the fourth inverter F4 is connected with the first input end of the and gate a 5.
In the control logic circuit 301 designed as above, taking the example that the switch cycle end signal is a high level signal and the load peak signal is a low level signal in the timing diagram of fig. 4, when the load voltage Vcs gradually increases to generate the timing start signal, the third inverter F3 does not receive the switch cycle end signal, that is, the third inverter F3 receives the inverted level signal of the switch cycle end signal, which is a low level signal, the third inverter F3 converts the low level signal into a high level signal and transmits the high level signal to the first input terminal of the first nand gate a1, the second input terminal of the first nand gate a1 is preset with a low level signal, so that the first nand gate a1 outputs a high level signal to the first input terminal of the second nand gate a2, and the load voltage is not 0 because the power control device 42 is closed at this time, the second input terminal of the second nand gate a2 receives the inverted level signal of the load peak signal transmitted by the load peak control unit 50, the nand gate a2 outputs a low signal to the fourth inverter F4 because both input terminals of the nand gate a2 receive the high signal, and the low signal is converted into a high signal by the fourth inverter F4 and transmitted to the first terminal of the and gate a 5.
The first end of the third nand gate A3 receives the opposite level signal of the load peak signal, which is a high level signal, and the second end of the third nand gate A3 is preset with a high level signal, so that the third nand gate A3 outputs a low level signal to the fifth inverter F5, and the low level signal is converted into a high level signal by the fifth inverter and transmitted to the second end of the and gate a 5.
The first terminal and the second terminal of the and gate a5 both receive the high level signal, so that the and gate outputs the high level signal, and the driving circuit 302 drives the power control device to be continuously turned on.
In the process that the load current gradually increases and does not reach the maximum, the load voltage Vcs does not reach the peak value, so the load peak value control unit 50 outputs the opposite level signal of the load peak value signal, and since the timing does not reach the first time length, the period control unit 20 outputs the inverted signal of the switching period end signal, so that the control logic unit 30 continuously controls the power control device 42 to be turned on in the process that the load current gradually increases to reach the maximum.
When the load current Ics reaches the maximum, that is, the load voltage Vcs reaches the maximum, the load peak control unit 50 outputs a load peak signal, which is a low level signal, the low level signal is transmitted to the first end of the third nand gate A3, and since the second end of the third nand gate A3 inputs a high level signal, the third nand gate A3 outputs a high level signal to the fifth inverter F5, and the high level signal is converted by the fifth inverter F5 to output a low level signal to the second end of the and gate a 5.
The load peak signal is transmitted to the second end of the second nand gate a2, and the first end of the second nand gate a2 receives the high level signal, so that the second nand gate a2 outputs the high level signal to the fourth inverter F4, and the high level signal is converted by the fourth inverter F4 and outputs the low level signal to the first end of the and gate a 5.
Since the low level signal is input to both ends of the and gate a5, the and gate a5 outputs a low level signal to the driving circuit 302, thereby controlling the power control device 42 to be turned off.
After the power control device 42 is turned off, the load current Ics is gradually decreased, the demagnetization detecting unit 40 collects and detects the load current Ics, and when it is detected that the load current is changed from the maximum to 0, a demagnetization completion signal of a high level is sent to the second nor gate O2 in the starting point control unit 10, so that the starting point control unit 10 sends an inverted signal of the timing starting signal to the period control unit 20, so that the period control comparator L2 in the period control unit 20 starts to operate, and sends a switching period end signal to the control logic circuit 301 after the second time length T.
The high-level switching cycle end signal is inverted to a low level by the third inverter F3 and then transmitted to the first end of the first nand gate a1, the second end of the first nand gate a1 is a high-level signal in the last state, so that the first nand gate a1 outputs a high-level signal, the high-level signal is transmitted to the second end of the second nand gate a2, since the load voltage is 0 at this time, the load peak control unit 50 inputs an opposite level signal of the high-level load peak signal to the first end of the second nand gate a2, so that the second nand gate a2 outputs a low-level signal, and the low-level signal is inverted by the fourth inverter F4 and then transmits the high-level signal to the first end of the and gate a 5.
The opposite level signal of the high load peak signal is also transmitted to the first end of the third nand gate A3, the output end of the third nand gate A3 is a high level signal in the last state, the high level signal is transmitted to the first end of the fourth nand gate a4, the second end of the fourth nand gate a4 inputs a low level signal when the load current is 0, so that the fourth nand gate a4 inputs a high level signal to the second end of the third nand gate A3, so that the two ends of the third nand gate A3 receive the high level signal to output a low level signal, and the low level signal is inverted by the fifth inverter F5 to output the high level signal to the second end of the and gate a 5. As a possible implementation, as shown in fig. 9, a second terminal of the fourth nand gate a4 may be connected to the demagnetization detecting unit 40 through a sixth inverter F6, so as to receive a low level signal when the load current is 0 and receive a high level signal when the load current is not 0.
Since both ends of the and gate a5 input a high signal, the and gate a5 sends a high signal to the power control device 42 to control the power control device 42 to be turned back on from off.
In the above-mentioned settingIn the dimming control circuit of the meter, in the present embodiment, the period control unit 20 sends a switching period end signal to the control logic unit 30 after receiving a first time length from a time point of the timing start signal Star transmitted by the start point control unit 10. The control logic unit 30 turns off the power control device 42 of the load circuit 4 when the load voltage is a peak value, after the power control device 42 is turned off, the power control device 42 is turned on according to the switching cycle end signal sent by the cycle control unit 20, since the timing start signal Star is generated by the start point control unit 10 according to the received load voltage and the preset reference voltage, and since the preset reference voltage Vref is fixed, the voltage value of the load voltage Vcs reaching the preset reference voltage Vref in each cycle is the same, so that the value of the load current Ics is the same when the timing start signal Star is generated in each switching cycle, and thus the timing start point of each cycle is the same; at the same time, since the first time length is fixed and the timing start point is also fixed, the time period T of the first time length from the time point of the timing start signal Star is setDCMIs also fixed; in addition, in each switching cycle, the load current Ics is linearly increased when the power control device 42 is closed, the load current Ics is linearly decreased after the power control device 42 is turned off, and since the control logic unit 30 turns off the power control device 42 of the load circuit 4 when the load voltage is at a peak, the peak value of the load current Ics is fixed, so that the time length T from the start of timing to when the load current Ics is at a peak to when the load current Ics is decreased from a maximum to 0CRMIs also fixed due to TCRMIs stationary, TDCMAnd is also fixed, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed and does not fluctuate, and the ripple is eliminated.
Second embodiment
As shown in fig. 10, the present application provides a dimming control chip 1, where the dimming control chip 1 includes the dimming control circuit described in any optional embodiment of the first embodiment, and since the dimming control chip 1 is designed to have the dimming control circuit in the first embodiment, the dimming control chip 1 can solve the ripple phenomenon generated by dimming in the DCM mode, so as to improve the LED dimming effect.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Claims (10)
1. A dimming control circuit, comprising: a starting point control unit (10), a period control unit (20) and a control logic unit (30);
the starting point control unit (10) is used for receiving a load voltage, generating a timing starting signal according to a preset reference voltage and the load voltage and transmitting the timing starting signal to the period control unit (20);
the period control unit (20) is used for sending a switching period ending signal to the control logic unit (30) after a first time length from a time point of receiving a timing starting signal;
the control logic unit (30) is used for generating a disconnection driving signal when the load voltage reaches a peak value, and the disconnection driving signal is used for controlling a power control device in a load circuit to be disconnected; and after the power control device is switched off, generating a closing driving signal according to the received switching period ending signal, wherein the closing driving signal is used for controlling the power control device to be closed.
2. The dimming control circuit according to claim 1, wherein the starting point control unit (10) is further configured to send an inverted level signal of the timing start signal to the period control unit (20) at a time when the load current decreases from a maximum value to 0;
the period control unit (20) is further configured to send the switching period end signal to the control logic unit (30) after a second time length from a time point when the inverted level signal of the timing start signal is received, wherein the second time length is equal to a difference between the first time length and a time length from generation of the timing start signal to generation of the inverted level signal.
3. The dimming control circuit according to claim 2, further comprising a demagnetization detecting unit (40), wherein the demagnetization detecting unit (40) is connected to the starting point control unit (10);
the demagnetization detection unit (40) is used for receiving the load current of the load circuit, generating a demagnetization finishing signal at the moment when the load current is reduced from the maximum value to 0, and transmitting the demagnetization finishing signal to the starting point control unit (10);
and the starting point control unit (10) is used for sending an inverted level signal of the timing starting signal to the period control unit (20) according to the demagnetization finishing signal, the preset reference voltage and the load voltage.
4. The dimming control circuit according to claim 3, wherein the starting point control unit (10) comprises: a clocked comparator (L1), a first NOR gate (O1), a second NOR gate (O2), and a first inverter (F1);
the normal phase input end of timing comparator (L1) is used for receiving the load voltage, the inverting input end of timing comparator (L1) is used for receiving preset reference voltage, the output end of timing comparator (L1) with the first input end of first NOR gate (O1) is connected, the output end of first NOR gate (O1) respectively with the input end of first inverter (F1) and the first input end of second NOR gate (O2) are connected, the second input end of second NOR gate (O2) with demagnetization detection unit (40) is connected, the output end of second NOR gate (O2) with the second input end of first NOR gate (O1) is connected, the output end of first inverter (F1) with cycle control unit (20) is connected.
5. The dimming control circuit according to claim 2, wherein the period control unit (20) comprises a period control comparator (L2) and a logic circuit (2021);
the logic circuit (2021) is used for controlling the period control comparator (L2) to be out of operation when the timing starting signal is received; and driving the period control comparator (L2) to work when receiving the inverted level signal of the timing starting signal, so that the period control comparator (L2) sends the switching period ending signal to the control logic unit after the second time length.
6. Dimming control circuit according to claim 5, wherein the period control unit (20) is further configured to receive a dimming signal;
the period control unit (20) is used for adjusting the second time length according to the dimming signal so as to adjust the switching period length of the power control device and further adjust the brightness of the load circuit.
7. The dimming control circuit according to claim 6, wherein the period control unit (20) further comprises a pulse generating circuit (2022), a switching circuit (2023), a first charging and discharging circuit (2024), and a second charging and discharging circuit (2025);
the output end of the starting point control unit (10) is respectively connected with the input ends of the pulse generating circuit (2022) and the logic circuit (2021), the output end of the logic circuit (2021) is respectively connected with the enabling end of the period control comparator (L2) and the switch circuit (2023), the first end of the switch circuit (2023) is used for being connected with a reference signal source, the second end of the switch circuit (2023) is respectively connected with the inverting input end of the period control comparator (L2) and the first charging and discharging circuit (2024), the non-inverting input terminal of the period control comparator (L2) is connected with the second charging and discharging circuit (2025) and is used for receiving the dimming signal, the output of the period control comparator (L2) is connected to the control logic unit (30), the output end of the pulse generating circuit (2022) is respectively connected with the first charging and discharging circuit (2024) and the second charging and discharging circuit (2025);
the pulse generating circuit (2022) is used for generating a pulse signal according to the timing starting signal;
the first charging and discharging circuit (2024) is used for discharging when receiving the pulse signal so as to reset the voltage of the inverting input end of a period control comparator (L2) connected with the first charging and discharging circuit (2024);
the second charging and discharging circuit (2025) is used for performing discharging reset when the pulse is received, and performing charging according to the received dimming signal after the discharging reset, so that the voltage of the non-inverting input end of the period control comparator (L2) connected with the second charging and discharging circuit (2025) is increased.
8. Dimming control circuit according to claim 7, wherein the logic circuit (2021) comprises a second inverter (F2);
an input terminal of the second inverter (F2) is connected to an output terminal of the start point control unit (10), and an output terminal of the second inverter (F2) is connected to an enable terminal of the period control comparator (L2) and the switch circuit (2023), respectively;
preferably, the switch circuit (2023) includes a third controllable switch tube (M3), a control terminal of the third controllable switch tube (M3) is connected to the output terminal of the second inverter (F2), a first terminal of the third controllable switch tube (M3) is connected to the external power supply, and a second terminal of the third controllable switch tube (M3) is connected to the inverting input terminal of the period control comparator (L2) and the first charge and discharge circuit (2024), respectively;
preferably, the first charging and discharging circuit (2024) includes a first controllable switch tube (M1) and a first capacitor (C1), a second end of the third controllable switch tube (M3) is respectively connected to a first end of the first capacitor (C1) and a first end of the first controllable switch tube (M1), a second end of the first capacitor (C1) and a second end of the first controllable switch tube (M1) are connected to ground, and a control end of the first controllable switch tube (M1) is connected to the pulse generating circuit (2022);
preferably, the second charging and discharging circuit (2025) includes a second controllable switch tube (M2) and a second capacitor (C2), the dimming signal is respectively connected to the non-inverting input terminal of the period control comparator (L2), the first terminal of the second capacitor (C2) and the first terminal of the second controllable switch tube (M2), the second terminal of the second controllable switch tube (M2) is connected to the second terminal of the second capacitor (C2) and then grounded, and the control terminal of the second controllable switch tube (M2) is connected to the pulse generating circuit (2022).
9. The dimming control circuit according to claim 1, further comprising a load peak control unit (50), wherein an input of the load peak control unit (50) is configured to receive the load voltage, and an output of the load peak control unit (50) is connected to the control logic unit (30);
the load peak control unit (50) is used for sending a load peak signal to the control logic unit (30) when the load voltage reaches a peak value, so that the control logic unit (30) generates the disconnection driving signal according to the load peak signal; sending an inverted level signal of the load peak signal to the control logic unit (30) when the load voltage is not a peak value, so that the control logic unit (30) generates the closing driving signal according to the inverted level signal of the load peak signal and the switching period ending signal;
preferably, the control logic unit (30) comprises a control logic circuit (301) and a driving circuit (302), a first input terminal of the control logic circuit (301) is connected with an output terminal of the period control unit (20), and a second input terminal of the control logic circuit (302) is connected with an output terminal of the load peak value control unit (50);
the output end of the control logic circuit (301) is connected with the control end of the power control device through the drive circuit (302);
preferably, the control logic circuit (301) comprises a third inverter (F3), a fourth inverter (F4), a fifth inverter (F5), a first nand gate (a1), a second nand gate (a2), a third nand gate (A3), a fourth nand gate (a4), and an and gate (a 5);
the output end of the load peak control unit (50) is respectively connected with the second input end of the second NAND gate (A2) and the first input end of a third NAND gate (A3);
a second input end of the third nand gate (A3) is connected with an output end of the fourth nand gate (a4), an output end of the third nand gate (A3) is respectively connected with a first input end of the fourth nand gate (a4) and an input end of a fifth inverter (F5), and an output end of the fifth inverter (F5) is connected with a second input end of the and gate (a 5);
a first input end of the second nand gate (a2) is connected with an output end of the first nand gate (a1), an output end of the second nand gate (a2) is respectively connected with a second input end of the first nand gate (a1) and an input end of the fourth inverter (F4), a first input end of the first nand gate (a1) is connected with an output end of the third inverter (F3), an input end of the third inverter (F3) is connected with an output end of the period control unit (20), and an output end of the fourth inverter (F4) is connected with a first input end of the and gate (a 5);
the output end of the AND gate (A5) is connected with the input end of the drive circuit (302).
10. A dimming control chip, wherein the dimming control chip comprises the dimming control circuit of any one of claims 1-9.
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| CN202111171654.7A CN113709935A (en) | 2021-10-08 | 2021-10-08 | Dimming control circuit and dimming control chip thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN116032253A (en) * | 2023-03-24 | 2023-04-28 | 深圳市思远半导体有限公司 | Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment |
| CN116032253B (en) * | 2023-03-24 | 2023-07-21 | 深圳市思远半导体有限公司 | Clock signal generating circuit, charge pump phase-locked loop circuit, chip and terminal equipment |
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