JP3446425B2 - Frequency synchronization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synchronization circuit, and more particularly to a circuit suitable for speeding up the time required to switch from one frequency to another frequency, so-called lock-up time.

[0002]

2. Description of the Related Art Conventionally, in the field of communication and the like, there has been a strong demand for shortening the lockup time of a frequency synchronizing circuit. For example, in a frequency synchronization circuit used in a wireless device, it is necessary to frequently switch the output frequency for transmission and the output frequency for reception alternately and output, so that it is necessary to lock up each output frequency at high speed. .

Therefore, a method has been proposed in which the level of the output current gain of the charge pump used in the frequency synchronization circuit is raised to lock up at high speed.
This device has a new problem that power consumption increases and the influence of noise and the like becomes great.

A frequency synchronizing circuit designed for low power consumption and low noise is disclosed, for example, in "PLL Frequency Synthesizer Circuit Design Method" by Toshiyuki Ozawa (Sogo Denshi Publishing Co., Ltd.). FIG. 11 shows, for example, a frequency synchronization circuit suggested from the above-mentioned document, in which a charge pump A and a charge pump B are provided, and normally only the charge pump A operates to set the output current gain to a low level. Every time the frequency is switched, the charge pump B for high-speed lockup operates at the same time as the charge pump A, and high-speed lockup is achieved by switching the output current gain to a high level, and low power consumption and low noise are also achieved. It is a thing.

[0005]

However, in the frequency lockup circuit for high speed lockup shown in FIG. 11, it is necessary to provide the charge pump in proportion to the level of the output gain to be switched, and the circuit scale increases. It had a drawback. In addition, it is necessary to send data from the outside every time the gain level is switched, which makes the system complicated.

An object of the present invention is to solve the above-mentioned problems, and enables switching of the output current gain level without changing the number of charge pumps to enable high-speed lockup, and The purpose is to obtain a frequency synchronization circuit that achieves low power consumption and low noise.

Still another object of the present invention is to obtain the output current gain level of a large number of charge pumps without increasing the number of charge pumps, for example, to adjust the gain levels stepwise to achieve a smooth high-speed lock. The purpose of the present invention is to obtain a frequency synchronization circuit capable of achieving lockup at a higher speed by achieving lockup or by setting a very large level of output current gain during frequency switching.

Still another object of the present invention is that the output current gain level of the charge pump does not have to be sent externally every time the level is switched, and the switching can be performed automatically, and the system has a simple structure. A frequency synchronizing circuit is obtained.

[0009]

The frequency synchronizing circuit of the present invention includes a voltage controlled oscillator, a control voltage generating means, a basic operation section for performing a source operation or a sink operation from a single output node, and a basic operation section. A current control unit having a control unit that changes a current value by a gain control signal is provided.

Further, in a frequency synchronizing circuit which outputs an output signal having a frequency selected from a plurality of frequencies in synchronization with a reference frequency signal, a voltage controlled oscillator, a control voltage generating means and a single output node are used. A current having a basic operation unit that performs a source operation or a sink operation, and a control unit that changes the current value in the basic operation unit with a gain control signal for changing the gain for a predetermined period when changing the frequency of the output signal. A control means is provided.

Further, a voltage controlled oscillator, a variable frequency divider,
A phase comparator and a phase comparison output from this phase comparator and a gain control signal are received, and the output current is controlled to a value corresponding to the input gain control signal, and the above-mentioned based on the input phase comparison output. A current control unit that outputs an output current from a single output node or draws an output current from the single output node, and an input node is connected to the single output node of the current control unit. Control voltage generating means for supplying the voltage controlled oscillator with a voltage that changes according to the output current flowing out from the output node or the output current drawn from the single output node. is there.

[0012]

[0013]

Further, a gain control signal generating means for generating a gain control signal is further provided, and the gain control signal generating means receives the reference frequency signal and the switching timing signal, and outputs the gain control signal among two values by the switching timing signal. The frequency of the signal based on the reference frequency signal is counted as one value, and when the count number reaches a predetermined value, the gain control signal is set to the other of the two values.

Further, there is further provided a gain control signal generating means for generating a gain control signal, wherein the gain control signal generating means is inputted with serial data indicating a frequency division value and outputs as parallel data, and this shift register. A division value is determined by a latch circuit that latches parallel data of a register and data indicating the division value latched by the latch circuit, and the clock signal is divided based on the determined division value. A variable frequency divider for outputting and a count for counting a predetermined number of cycles of the output signal from the variable frequency divider by the switching timing signal and outputting a gain control signal which is one of two values of the count period. Means and are provided.

[0016]

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 to 3 show Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 in FIG. 1 compares the phases of a reference frequency signal fr input from an input terminal 6 and a controlled frequency signal fp, and In the phase comparator which outputs the phase comparison output based on the comparison result, in the first embodiment, the controlled frequency signal fp is advanced in phase with respect to the reference frequency signal fr (the controlled frequency signal). fp has a frequency higher than that of the reference frequency signal fr) and a pulse (for example, H level potential) having a width corresponding to the advance of the phase for each cycle of the reference frequency signal fr (for example, in FIG. The first phase comparison output shown in d) is output to the first phase comparison output line 9, and the controlled frequency signal fp is delayed in phase with respect to the reference frequency signal fr (the controlled frequency signal fp). Is above For example, in FIG. 4C, a pulse having a width (for example, an H level potential) having a width corresponding to the delay of the phase is provided for each cycle of the reference frequency signal fr). Second phase comparison shown
The output is output to the second phase comparison output line 8.

Reference numeral 2 receives the first and second phase comparison outputs from the phase comparator 1 and the gain control signal CL1 and is controlled to an output current having a value according to the input gain control signal CL1. First and second entered
Based on the phase comparison output of the above, the current control means is composed of a charge pump that causes the output current to flow from the output node 2c or draws from the output node 2c. Basic operation unit 2 that performs sink operation to draw current
a and a control unit 2b that changes the current value in the source operation and the sink operation in the basic operation unit 2a by the gain control signal CL1. Specifically, it has the configuration shown in FIG.

In FIG. 2, T1 is the output node 2c.
One main electrode (drain electrode) is connected, the control electrode (gate electrode) is connected via the inverter Inv to the second phase comparison signal line 8 and the second phase comparison from the phase comparator 1 in A signal corresponding to the output, that is, a signal obtained by inverting the second phase comparison output by the inverter Inv is received by the control electrode, and the second phase comparison output is turned on during the pulse period and is turned off during the other period. P type M
A first transistor T2, which is an OS transistor, is a PNP connected between the other main electrode (source electrode) of the first transistor T1 and a power supply potential node Vcc.
The second transistor is a bipolar transistor.

At T3, one main electrode (drain electrode) is connected to the output node 2c, and a control electrode (gate electrode) is provided.
There receiving a first signal corresponding to the phase comparison output, i.e. the control electrode of the same signal as the first phase comparison output from the phase comparator 1 is connected to the first phase comparison signal line 9, the first The third transistor T4, which is an N-type MOS transistor that is in a conductive state during the pulse comparison output of 1 and is in a non-conductive state during the other period, is the other main electrode (source electrode) of the third transistor T3. A fourth transistor, which is an NPN bipolar transistor connected between the ground potential node GND and the first to third transistors T1, T2, T3, constitutes an output circuit.

One main electrode (collector electrode) and control electrode (base electrode) of T5 are commonly connected to the control electrode of the second transistor T2, and the other main electrode (emitter electrode) of T5 is connected. The fifth transistor, which is a PNP bipolar transistor connected to the power supply potential node Vcc, forms a current mirror circuit with the second transistor T2. In the first embodiment, the transistor size is the same and the second transistor The current (collector current) I1 flowing through the transistor T2 is set to the same value as the current (collector current) I3 flowing through the fifth transistor T5.

T6 is a sixth PNP bipolar transistor whose other main electrode (emitter electrode) is connected to the power supply potential node Vcc and whose control electrode (base electrode) is connected to the control electrode of the fifth transistor T5.
In the first embodiment, a current mirror circuit is formed with the fifth transistor T5, and in the first embodiment, the same transistor size is used and a current (collector current) having the same value as the current I3 flowing through the fifth transistor T5. ) I2 is washed away.

T7 has one main electrode (collector electrode) connected to the other main electrode (collector electrode) of the sixth transistor T6 and is commonly connected to the control electrode (base electrode), and the other main electrode. An NPN whose (emitter electrode) is connected to the ground potential node and whose control electrode (base electrode) is connected to the control electrode of the fourth transistor T4.
The seventh transistor, which is a bipolar transistor, forms a current mirror circuit together with the fourth transistor T4. In the first embodiment, the transistor size is the same and the current (collector current) flowing through the fourth transistor T4 is the same. ) I1 is connected to this seventh transistor T
It is set to the same value as the current I2 flowing through the sixth transistor T6 which becomes the current (collector current) I2 flowing through 7.

The first to seventh transistors T1 to T7 and the inverter Inv constitute a basic operation section of the current control means 2.

[0025] T8 is one main electrode (collector electrode) and the control electrode (base electrode) is commonly connected to a constant current source I in contact <br/> connection is Rutotomoni other main electrode (emitter electrode) is the power supply potential An eighth transistor, which is a PNP bipolar transistor connected to the node Vcc, includes the constant current source I
The constant current I0 defined by

T9 is a ninth PNP bipolar transistor whose other main electrode (emitter electrode) is connected to the power supply potential node Vcc and whose control electrode (base electrode) is connected to the control electrode of the eighth transistor T8. The transistor forms a current mirror circuit with the eighth transistor T8, and forms a constant current circuit for flowing a constant current. In the first embodiment, the transistor size is the same as that of the eighth transistor T8. Then, a current (collector current) I4 having the same value as the current (collector current) I0 flowing through the eighth transistor T8 is passed.

T10 is a tenth PNP bipolar transistor whose other main electrode (emitter electrode) is connected to the power supply potential node Vcc and whose control electrode (base electrode) is connected to the control electrode of the eighth transistor T8. A transistor forms a current mirror circuit together with the eighth transistor T8 to form a constant current circuit for flowing a constant current. In the first embodiment, the transistor size is the same as that of the eighth transistor T8. And then the 8th
A current (collector current) I5 having the same value as the current I0 flowing in the transistor T8 of the above is passed.

D1 is a first diode whose anode electrode is connected to one main electrode (collector electrode) of the ninth transistor T9, and D2 is the tenth transistor T.
An anode electrode is connected to one main electrode (collector electrode) of 10 and a cathode electrode is a second diode whose cathode electrode is connected to the cathode electrode of the first diode D1.

T11 has one main electrode (collector electrode) and control electrode (base electrode) connected in common and is connected to the cathode electrodes of the first and second diodes D1 and D2, and the other main electrode (emitter electrode). ) Is an NPN bipolar transistor connected to the ground potential node, and T12 has one main electrode (collector electrode) connected to one main electrode of the fifth transistor T5 and the other main electrode. A twelfth transistor, which is an NPN bipolar transistor whose (emitter electrode) is connected to the ground potential node and whose control electrode (base electrode) is connected to the control electrode of the eleventh transistor T11, is the same as the eleventh transistor T11 . In the first embodiment, the current mirror circuit is constituted by The same current (collector current) I6 flowing in the eleventh transistor T11 and the same value (collector current) I3 are caused to flow, and the fifth transistor T5 is caused to flow the same current I3. .

T13 is the tenth transistor T10 described above.
A thirteenth transistor, which is an N-type MOS transistor connected between one of the main electrodes and the ground node and receives the gain control signal CL1 at the control electrode (gate electrode),
When the gain control signal CL1 means a gain change, the gain control signal CL1 becomes non-conductive, and the current I5 flowing through the tenth transistor T10 is caused to flow to one electrode of the eleventh transistor T11 via the second diode D2. when it is intended to flow a current I5 flowing through the transistor T10 of the 10 rendered conductive to the ground potential node, of the ninth and tenth transistors T 9 and T 10, which each constitute a constant current circuit A predetermined transistor is selected by the gain control signal CL1, a total value of constant currents flowing in the selected transistor is generated, and this total value is supplied to the basic operation unit 2a to perform the source operation and the sink in the basic operation unit 2a. The eleventh and twelfth transistors T11 and T are provided with a selection circuit that regulates a current value in operation. Those that are constituted by two.

[0031] Note that the constant current source I, transistors T8～T 13 of the eighth to 13th, the first and second diodes D1 and D2, the second and fourth output circuit in the basic operation unit 2a The control section 2b for controlling the current I1 flowing through each of the transistors T2 and T4 of FIG.

[0032] Returning to FIG. 1, 3 input nodes 3a to the output node 2c of the current control means 2 is connected, in accordance with the state of the output node 2c of the current control means 2, i.e., it flows from the output node 2 c Is a control voltage generating means including a low-pass filter that outputs from the output node 3b as a control voltage a voltage that changes according to the output current I1 or the output current I1 drawn from the output node 2c. In the first embodiment, for example, It has the circuit configuration shown in FIG.

In FIG. 3, R1 is a resistor having one end connected to the input node 3a and the other end connected to the capacitor C1. The capacitor C1 has one end connected to R1 and the other end connected to the ground potential node GND. However, it discharges or charges the electric charge accumulated in the capacitor C1 according to the state of the output node 2c of the current control means 2 to output a voltage as a control voltage from the output node 3b.
R2 is a resistor having one end connected to the input node 3a, the other end connected to the output node 3b, and the capacitor C2 has one end connected to the output node 3b and the other end connected to the ground potential node GND. A filter for removing high frequency components of the output voltage is formed.

Returning to FIG. 1 again, 4 is a voltage controlled oscillator VCO which receives the control voltage from the control voltage generating means 3 and outputs an output signal fo having a frequency corresponding to the control voltage to the output terminal 7, Receives the output signal fo from the voltage controlled oscillator 4 and also receives the frequency division value setting signal input from the frequency division value input terminal 16, and outputs the frequency division value (1 / N, where N is an arbitrary value, is a variable frequency divider that divides the output signal fo from the voltage controlled oscillator 4 and outputs it as the controlled frequency signal fp to the phase comparator 1. .

When the frequency of the output signal fo from the voltage controlled oscillator 4 is changed, a gain control signal CL1 means a gain change for a predetermined period (for example, L level) when changing the frequency of the output signal fo, as shown in FIG. 4 (e). And a gain control signal generating means for generating the gain control signal CL1 to the current control means 2 in the first embodiment.
The switching timing signal input from the clock signal CL and the control signal input terminal 11 is received, the gain control signal CL1 is set to one of two values, for example, the L level by the switching timing signal, and the input clock signal The number of cycles is counted, and when the counted number reaches a predetermined value, the gain control signal CL1 is set to the other of the two values, for example, the H level.

Next, the operation of the frequency synchronizing circuit configured as described above will be described mainly based on the timing chart shown in FIG. First, when the output signal fo from the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr, that is, the controlled frequency signal fp having a frequency of 1 / N of the output signal fo (the output signal fo is divided by 1 Signal divided by the variable frequency divider 5 of / N) is the reference frequency signal fr
And the frequency is the same and the phase is the same, that is, the periods T0, T2, and T4 shown in FIG. 4 will be described.

Controlled frequency signal fp and reference frequency signal f
Since r has the same frequency and the same phase, the phase comparator 1 recognizes a phase difference of 0 and outputs the first and second phase comparison outputs as shown in (d) and (c) of FIG. And output to the first and second phase comparison output lines 9 and 8 as L level. The current control means 2 which has received the L-level first and second phase comparison outputs via the first and second phase comparison output lines 9 and 8 has its output node 2c electrically floating (floating state). ) That is, the high impedance state is set. That is, the third transistor T3 that forms the output circuit of the basic operation unit 2a in the current control unit 2
L to its control electrode via the first phase comparison output line 9.
Since it receives the first phase comparison output of the level, it becomes non-conductive, and the first transistor T1 is at the L level via the second phase comparison output line 8 to its control electrode and further at the H level by the inverter Inv. Since it receives the second phase comparison output of, the state becomes non-conductive. As a result, the output node 2c becomes a floating state.

When the output node 2c of the current control means 2 is in a floating state, no current flows from the output node 2c to the input node 3a of the control voltage generation means 3 connected to this output node 2c, and the output node 2c Since the current does not flow into 2c, the control voltage generating means 3 continues to maintain the predetermined voltage at its output node 3b. The voltage controlled oscillator 4 which receives the control voltage composed of the predetermined voltage,
Since the control voltage continues to be maintained at the same value , the output signal in the same state, that is, the signal synchronized with the reference frequency signal fr will continue to be output.

On the other hand, in such a state, that is, when the frequency of the output signal fo from the voltage controlled oscillator 4 is N times the frequency of the reference frequency signal fr, the period T0 shown in FIG.
At T2 and T4, due to some cause, for example, a change in the load state of the load connected to the output terminal 7,
A case where the output signal fo from the voltage controlled oscillator 4 is out of synchronization will be described.

Now, the output signal fo from the voltage controlled oscillator 4 is
If the phase of is advanced with respect to the reference frequency signal fr,
The controlled frequency signal fp obtained by dividing the output signal fo by the variable frequency divider 5 also advances with respect to the reference frequency signal fr. Then, the phase comparator 1 recognizes the phase difference and outputs a pulse (for example, an H level pulse) having a width corresponding to the phase advance of the controlled frequency signal fp for each cycle of the reference frequency signal fr . Specifically, when the controlled frequency signal fp falls (changes from H level to L level), it rises (changes from L level to H level) when the reference frequency signal fr is at H level, and rises of the reference frequency signal fr. The first phase comparison output that falls and falls is output to the first phase comparison output line 9, and the L level second phase comparison output is output to the second phase comparison output line 8.

The current control means 2 which has received the first and second phase comparison outputs as described above receives the pulse period of the first phase comparison output during the period from the input node 3a to the output node 2c of the control voltage generation means 3. A sink operation is performed to draw out a current having a current value I1 (= I0). That is, the third transistor T3 that forms the output circuit of the basic operation unit 2a of the current control unit 2 that has received the first phase comparison output at the control electrode.
Is a conductive state during the pulse period of the first phase comparison output, and constitutes the output circuit of the basic operation unit 2a in the current control means 2 which receives the inverted signal of the second phase comparison output at the control electrode. Transistor T1 continues to be non-conductive.

As a result, during the pulse period of the first phase comparison output, the output node 2c and the ground potential node become conductive via the third and fourth transistors T3 and T4, and the fourth transistor T4. an input node 3 of the control voltage generating means 3 a constant current value I1 becomes the current defined by
It is pulled out from a to the ground potential node through the output node 2c and the third and fourth transistors T3 and T4.

At this time, since the frequency of the output signal fo is not changed (switched), the gain control signal CL1
Is at H level, and the thirteenth transistor T13 is in a conductive state. Therefore, the eighth transistor T
8 and a current I5 flowing through a tenth transistor T10 that forms a current mirror circuit (current value is the same as I0)
Flows to the ground potential node via the thirteenth transistor T13. Therefore, the current I6 flowing through the eleventh transistor T11 is the current I4 flowing through the ninth transistor T9.
(Which constitutes a current mirror circuit with the eighth transistor T8, and the current value thereof is the same as I0)
The current value of the current I3 that flows through the twelfth transistor T12 that forms a current mirror circuit with the first transistor T11 is I0 (the same as the current value of the current I6.
4 and the current value I0). That is, the current value for controlling the basic operation unit 2a by the control unit 2b becomes I0.

A current value I0 is applied to the twelfth transistor T12.
The current I3 flows to the fifth transistor T5 as well. Then, the current I2 having the current value I0 flows through the sixth transistor T6 forming a current mirror circuit with the fifth transistor T5, and the current I2 flows through the seventh transistor T7. The current value of the current I1 flowing through the fourth transistor T4 that forms a current mirror circuit with the seventh transistor T7 becomes the same as the current value of the current I2 flowing through the seventh transistor T7, which is I0.

Therefore, during the pulse period of the first phase comparison output, the control voltage generating means 3 outputs the current having the current value I0 from the input node 3a of the control voltage generating means 3 via the output node 2c. The voltage drops and the voltage controlled oscillator 4 is operated to delay the phase of its output signal fo. As a result, the output signal fo of the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr. Further, if the phase of the output signal fo from the voltage controlled oscillator 4 is delayed with respect to the reference frequency signal fr, the controlled frequency signal fp obtained by dividing the output signal fo by the variable frequency divider 5 also becomes the reference frequency signal fr. You will be late for it.

Then, the phase comparator 1 recognizes the phase difference and outputs a pulse (for example, an H level pulse) having a width corresponding to the delay of the phase of the controlled frequency signal fp for each cycle of the reference frequency signal fr. Having, specifically, the reference frequency signal f
When the controlled frequency signal fp is at the H level when r falls (changes from the H level to the L level), it rises (L
(Change from level to H level), and outputs the second phase comparison output that falls in response to the fall of the controlled frequency signal fp to the second phase comparison output line 8 to output the L phase first phase comparison output. It is output to the second phase comparison output line 8.

The current control means 2 which has received the first and second phase comparison outputs as described above outputs a current value from the output node 2c to the input node 3a of the control voltage generation means 3 during the pulse period of the second phase comparison output. A source operation for giving a current of I1 (= I0) is performed. That is, the first transistor T1 forming the output circuit of the basic operation unit 2a in the current control unit 2 which receives the inverted signal of the second phase comparison output at the control electrode.
Is in a conductive state during the pulse period of the second phase comparison output, and receives the first phase comparison output at the control electrode, and forms a third transistor T3 constituting the output circuit of the basic operation unit 2a in the current control means 2. Keep non-conducting state.

As a result, during the pulse period of the second phase comparison output, the output node 2c and the power supply potential node become conductive via the first and second transistors T1 and T2, and the second transistor T2. The current having the constant current value I1 defined by is from the power supply potential node to the second and first currents.
Is supplied to the input node 3a of the control voltage generating means 3 via the transistors T2 and T1 and the output node 2c. At this time, since the frequency of the output signal fo is not changed (switched), the gain control signal CL1 is at the H level and the thirteenth transistor T13 is in the conductive state. Therefore, the eighth transistor T8
The current I5 (current value is the same as I0) flowing through the tenth transistor T10 that forms the current mirror circuit flows through the thirteenth transistor T13 to the ground potential node.

Therefore, the current I6 flowing through the eleventh transistor T11 is the current I6 flowing through the ninth transistor T9.
4 (which constitutes a current mirror circuit together with the eighth transistor T8 and its current value is the same as I0), and flows into the twelfth transistor T12 which constitutes a current mirror circuit together with the eleventh transistor T11. Current I3
Is I0 (the same as the current value of the current I6 and the same as the current value I0 of the current I4). That is, the control unit 2b
The current value for controlling the basic operation unit 2a is I0
Becomes

A current value I0 is applied to the twelfth transistor T12.
The current I3 flows to the fifth transistor T5 as well. Then, a current I1 having a current value I0 flows through the second transistor T2 that forms a current mirror circuit with the fifth transistor T5.
Therefore, during the pulse period of the second phase comparison output, the current of the current value I0 flows into the input node 3a of the control voltage generating means 3 via the output node 2c, and the control voltage output from the control voltage generating means 3 is reached. Will rise and the voltage controlled oscillator 4 will be operated to advance the phase of its output signal fo. As a result, the output signal fo of the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr.

As described above, in the state where the output signal fo from the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr, even if the output signal fo is out of synchronization with the reference frequency signal fr, the current control is performed. The sync operation or the source operation of the means 2 enables quick synchronization. Moreover, since the output current in the sink operation or the source operation of the current control means 2 is a low current of the current value I0, the power consumption is small and the influence of noise or the like can be suppressed as much as possible.

Next, the output signal f from the voltage controlled oscillator 4
In the state where o is synchronized with the reference frequency signal fr,
A case where the frequency of the output signal fo from the voltage controlled oscillator 4 is changed will be described. First, when the frequency of the output signal fo from the voltage controlled oscillator 4 is lowered, that is, in order to lower the frequency of the output signal fo described in the period T1 shown in FIG. 2, the frequency division value of the variable frequency divider 5 is changed. It is done by lowering. If the dividing value of the variable frequency divider 5 is lowered,
The controlled frequency signal fp from the variable frequency divider 5 temporarily becomes higher than the frequency of the reference frequency signal fr. This is equivalent to a state in which the controlled frequency signal fp is advanced in phase with respect to the reference frequency signal fr.

Therefore, the phase comparator 1 recognizes the phase difference between the controlled frequency signal fp and the reference frequency signal fr due to the increased frequency of the controlled frequency signal fp,
The controlled frequency signal fp for each cycle of the reference frequency signal fr
Has a pulse (for example, an H level pulse) having a width corresponding to the phase advance (corresponding to the frequency shift) of,
If the reference frequency signal fr is at the H level when the controlled frequency signal fp falls (changes from the H level to the L level), rises (changes from the L level to the H level) and falls after receiving the fall of the reference frequency signal fr. The first phase comparison output is output to the first phase comparison output line 9, and the L-level second phase comparison output is output to the second phase comparison output line 8.

The current control means 2 which has received the first and second phase comparison outputs as described above receives the control signal from the input node 3a of the control voltage generation means 3 through the output node 2c during the pulse period of the first phase comparison output. A sink operation is performed to draw out a current having a current value I1 (= 2 × I0). That is, the first
Receiving the phase comparison output of the third transistor T constituting the output circuit of the basic operation unit 2a of the current control unit 2.
Reference numeral 3 constitutes an output circuit of the basic operation unit 2a in the current control means 2, which is in a conductive state during the pulse period of the first phase comparison output and receives the inverted signal of the second phase comparison output at the control electrode. The transistor T1 of 1 continues to maintain the non-conducting state.

As a result, during the pulse period of the first phase comparison output, the output node 2c and the ground potential node become conductive via the third and fourth transistors T3 and T4, and the fourth transistor T4. an input node 3 of the control voltage generating means 3 a constant current value I1 becomes the current defined by
It is pulled out from a to the ground potential node through the output node 2c and the third and fourth transistors T3 and T4. At this time, the frequency of the output signal fo is changed (switched). Therefore, the switching timing signal input from the control signal input terminal 11 means that the gain is changed for a predetermined period (L level) as shown in (e) of FIG. Since the gain control signal CL1 is generated, the thirteenth transistor T13 is turned off.

[0056] Accordingly, constitute a current I5 flowing through the tenth transistor T10 of constituting the transistor T8 and the current mirror circuit of the eighth (current value the same as I0), a transistor T8 and the current mirror circuit of the eighth The current I4 (current value is the same as I0) flowing through the ninth transistor T9, which is operating
It flows to 11. The current value of the current I6 flowing through the eleventh transistor T11 is 2 × I0 (current values I0 and I5 of I5
4), and the current value of the current I3 flowing through the twelfth transistor T12 that forms a current mirror circuit with the eleventh transistor T11 is 2 × I0 (the current value of the current I6). The same as 2 × I0).
That is, the current value for controlling the basic operation unit 2a by the control unit 2b is 2 × I0.

A current value of 2 × is applied to the twelfth transistor T12.
When the current I3 of I0 flows, the current I3 also flows through the fifth transistor T5. Then, a current I2 having a current value of 2 × I0 flows through the sixth transistor T6 that forms a current mirror circuit with the fifth transistor T5, and a current value I 2 flows through the seventh transistor T7.
The current value of the current I1 flowing through the fourth transistor T4 that forms a current mirror circuit with the seventh transistor T7 is the same as the current value of the current I2 flowing through the seventh transistor T7, which is 2 × I0. . Therefore, FIG.
As shown in ( f ) of (1), during the pulse period of the first phase comparison output, a current having a current value of 2 × I0 is extracted from the input node 3a of the control voltage generating means 3 via the output node 2c (-in FIG. 4). It is displayed). Therefore, during the pulse period of the first phase comparison output, the current of the current value 2 × I0 is extracted from the input node 3a of the control voltage generating means 3 via the output node 2c, and the control voltage output from the control voltage generating means 3 is output. Will drop considerably and the voltage controlled oscillator 4 will be operated so that the frequency of its output signal fo is lowered.

While the gain control signal CL1 is at L level,
The current control means 2 performs a sink operation based on the current value 2 × I0, the frequency of the output signal fo of the voltage controlled oscillator 4 is lowered at high speed, and the frequency of the controlled frequency signal fp from the variable frequency divider 5 is also reduced. The frequency is lowered at a high speed and approaches the frequency of the reference frequency signal fr, and the phase difference of the controlled frequency signal fp with respect to the reference frequency signal fr also becomes small.
The pulse period of the phase comparison output of is also shortened.

The gain control signal CL1 changes from L level to H level.
When the voltage rises to the level, the thirteenth transistor T13 is turned on, the current value for controlling the basic operation unit 2a by the control unit 2b becomes I0, and the frequency of the controlled frequency signal fp is still the frequency of the reference frequency signal fr. 4 (f), the current control means 2 performs a sink operation based on the current value I0, and the frequency of the output signal fo of the voltage controlled oscillator 4 is set to be low. adjust. In this way, when the frequency of the controlled frequency signal fp matches the frequency of the reference frequency signal fr and synchronization is achieved, the output signal fo of the voltage controlled oscillator 4 has its frequency lowered and the reference frequency signal fr It will be output in a state synchronized with. (Period T in FIG. 4
2)

The output signal f from the voltage controlled oscillator 4
When the frequency of o is increased, that is, the period T3 shown in FIG.
Will be described. The frequency of the output signal fo is increased by increasing the frequency division value of the variable frequency divider 5. When the frequency division value of the variable frequency divider 5 is increased, the controlled frequency signal fp from the variable frequency divider 5 temporarily becomes lower than the frequency of the reference frequency signal fr. This is equivalent to a state in which the controlled frequency signal fp is delayed in phase with respect to the reference frequency signal fr.

Therefore, the phase comparator 1 recognizes the phase difference between the controlled frequency signal fp and the reference frequency signal fr because the frequency of the controlled frequency signal fp becomes low,
The controlled frequency signal fp for each cycle of the reference frequency signal fr
Has a pulse (for example, an H level pulse) having a width corresponding to the phase delay (corresponding to the frequency shift) of the reference frequency signal fr.
When the controlled frequency signal fp is at the H level during the level change), the second phase comparison output that rises (changes from the L level to the H level) and falls in response to the fall of the controlled frequency signal fp Output to the phase comparison output line 8,
The L-level first phase comparison output is output to the first phase comparison output line 9.

The current control means 2 which has received the first and second phase comparison outputs as described above receives the current value from the output node 2c to the input node 3a of the control voltage generation means 3 during the pulse period of the second phase comparison output. A source operation for giving a current of I1 (= 2 × I0) is performed. That is, the first transistor T1 forming the output circuit of the basic operation unit 2a of the current control means 2 which has received the inverted signal of the second phase comparison output at the control electrode is operated by the first transistor T1 in the pulse period of the second phase comparison output, The third transistor T3, which is in the conductive state and receives the first phase comparison output at the control electrode, and which constitutes the output circuit of the basic operation unit 2a in the current control means 2, continues to maintain the non-conductive state.

As a result, during the pulse period of the second phase comparison output, the output node 2c and the power supply potential node become conductive via the first and second transistors T1 and T2, and the second transistor T2. The current having the constant current value I1 defined by is from the power supply potential node to the second and first currents.
Is supplied to the input node 3a of the control voltage generating means 3 via the transistors T2 and T1 and the output node 2c. At this time, the frequency of the output signal fo is changed (switched). Therefore, the switching timing signal input from the control signal input terminal 11 means that the gain is changed for a predetermined period (L level) as shown in (e) of FIG. Since the gain control signal CL1 is generated, the thirteenth transistor T13 is turned off.

[0064] Accordingly, constitute a current I5 flowing through the tenth transistor T10 of constituting the transistor T8 and the current mirror circuit of the eighth (current value the same as I0), a transistor T8 and the current mirror circuit of the eighth The current I4 (current value is the same as I0) flowing through the ninth transistor T9, which is operating
It flows to 11. The current value of the current I6 flowing through the eleventh transistor T11 is 2 × I0 (current values I0 and I5 of I5
4 is the sum of the current values I0), and the first transistor T11 and the first mirror T11 constitute a current mirror circuit.
The current value of the current I3 flowing through the second transistor T12 is 2
× I0 (the same as the current value 2 × I0 of the current I6). That is, the current value for controlling the basic operation unit 2a by the control unit 2b is 2 × I0.

A current value of 2 × is applied to the twelfth transistor T12.
When the current I3 of I0 flows, the current I3 also flows through the fifth transistor T5. Then, a current I1 having a current value of 2 × I0 flows through the second transistor T2 that forms a current mirror circuit with the fifth transistor T5. Therefore, the second pulse duration of the phase comparison output as shown in (f) of FIG. 4, that flow into the current of the current value 2 × I0 via the output node 2c to the input node 3a of the control voltage generating means 3 Therefore, the control voltage output from the control voltage generating means 3 rises considerably, and the voltage controlled oscillator 4 is operated so that the frequency of its output signal fo is increased.

While the gain control signal CL1 is at L level,
The current control means 2 performs the source operation based on the current value 2 × I0, the frequency of the output signal fo of the voltage controlled oscillator 4 is increased at high speed, and the frequency of the controlled frequency signal fp from the variable frequency divider 5 is also increased. The frequency is raised at a high speed and approaches the frequency of the reference frequency signal fr, and the phase difference of the controlled frequency signal fp with respect to the reference frequency signal fr also decreases.
The pulse period of the phase comparison output of is also shortened. When the gain control signal CL1 rises from the L level to the H level, the first
The transistor T13 of No. 3 is turned on, and the control unit 2b
The current value for controlling the basic operation unit 2a is I0
When the frequency of the controlled frequency signal fp does not match the frequency of the reference frequency signal fr, the current control means 2 performs the source operation based on the current value I0 as shown in (f) of FIG. , The output signal f of the voltage controlled oscillator 4
The frequency of o is finely adjusted to be high.

In this way, when the frequency of the controlled frequency signal fp coincides with the frequency of the reference frequency signal fr and is synchronized, the output signal fo of the voltage controlled oscillator 4 has its frequency raised and the reference frequency The signal is output in synchronization with the frequency signal fr. (Period T4 shown in FIG. 4) As described above, when the frequency of the output signal fo from the voltage controlled oscillator 4 is changed, the output current in the sink operation or the source operation of the current control unit 2 is doubled,
The frequency of the output signal fo can be changed at high speed.

Therefore, at normal times, low power consumption, noise resistance, and high-speed frequency conversion are possible. Above all, it has a very large effect. Although the reference frequency signal fr is directly input to the phase comparator 1 in the above-described first embodiment, the reference frequency signal fr is divided by the variable frequency divider (for example, frequency division value 1 / R). After going around, phase comparator 1
It may be the one entered in. In this case, the frequency of the output signal fo from the voltage controlled oscillator 4 is N / R times the frequency of the reference frequency signal fr. However, N
And R are values based on the frequency division values 1 / N and 1 / R of the variable frequency divider 5 for the output signal fo and the variable frequency divider for the reference frequency signal fr, respectively.

Embodiment 2. FIG. 5 shows the second embodiment of the present invention, in which the clock signal input to the gain control signal generating means 10 of the first embodiment is used as the reference frequency signal fr input to the phase comparator 1. The other points are the same as those in the first embodiment. Even in the frequency synchronization circuit configured in this way,
In addition to the effect similar to that of the first embodiment described above, the setting of the predetermined period, which means a gain change in the gain control signal CL1 from the gain control signal generating means 10, is a stable and accurate reference frequency obtained from a crystal oscillator or the like. Signal fr
Since it is performed on the basis of the above, the stable and accurate gain control signal CL1 is obtained, and the gain switching operation is also stabilized.

Embodiment 3. FIG. 6 shows a third embodiment of the present invention, in which the gain control signal generating means 10 of the above-described first embodiment is at a L level for a predetermined period based on a clock signal CL and a switching timing signal. In contrast to the one that generates the signal CL1, the third embodiment uses a gain control signal generating means that can arbitrarily set a predetermined period during which the gain control signal CL1 is at the L level. However, the other points are the same as those in the first embodiment. Therefore, the gain control signal generating means 10 used in the third embodiment will be described below with reference to FIG.

In FIG. 6, 12 is serial data indicating the frequency division value input from the frequency division value input terminal 11b in synchronization with the clock signal input from the clock signal input terminal 11a, and the frequency division value is indicated. Shows parallel data Sr1
˜Srn output shift register, 13 latches the parallel data Sr1 to Srn of this shift register by a latch signal input from the latch input terminal 11c, and latches it. Parallel data indicating the values Dr1 to Dr
The frequency division value is determined by n, and the reference signal (for example, the reference frequency signal fr as shown in the second embodiment may be used) formed of the input clock signal is set to the determined frequency division value (1 / M). It is a variable frequency divider that divides the frequency based on the output.

A count number 15 is set by the counter value input from the counter value input terminal 11e, and the variable frequency divider 14 is set by the reset signal (switching timing signal) input from the reset signal input terminal 11d.
The count number (predetermined number) of the period of the output signal from is counted, and the gain control signal CL1 which is one of the two values of the count period (L level in the third embodiment) is output. It is a counting means including a pulse counter.

Next, the operation of the gain control signal generating means 10 thus constructed will be described. First, the frequency division value is set in the variable frequency divider 14 and the count number is set in the counting means 15. The frequency division value is set in the variable frequency divider 14 as follows. That is, the clock signal is input to the clock signal input terminal 11a and the divided value input terminal 11a
When serial data indicating the frequency division value is input to b, the shift register 12 loads the serial data in synchronization with the input clock signal. When all the serial data indicating the frequency division value is captured by the shift register 12, the latch signal is input to the latch input terminal 11c. Assuming that this latch signal is generated based on the clock signal input to the clock signal input terminal 11a, the latch circuit 13 fetches the parallel data Sr1 to Srn stored in the shift register 12 and indicating the frequency division value. be able to.

The parallel data Dr1 to Drn indicating the frequency division values latched by the latch circuit 13 are variable frequency divider 14
Then, the variable frequency divider 14 sets the frequency division value based on the serial data input to the frequency division value input terminal 11b. In this way, the frequency dividing value is set in the variable frequency divider 14 and the count number is set in the counting means 15, and then used as a frequency synchronizing circuit in the same manner as in the first embodiment.

Since the frequency synchronizing circuit operates in the same manner as in the first embodiment, the gain control signal generating means 1
Only the way of generating the gain control signal CL1 by 0 is shown in FIG.
This will be described below using the timing chart of.

When the reset signal is not input to the reset signal input terminal 11d, the counting means 15 outputs the H level gain control signal CL1. Now, when the frequency of the output signal fo from the voltage controlled oscillator 4 is changed, a reset signal (L level pulse in (a) of FIG. 7) is input to the reset input terminal 11d as shown in (a) of FIG. To be done. Receiving the reset signal, the counting means 15 is reset, the gain control signal CL1 which is the output thereof is changed from the H level to the L level which means a gain change, and the variable frequency divider 14 outputs the gain control signal CL1 to the L level shown in FIG.
Begin counting the periodic number of the signal shown in (c) in the dividing value 1 / M which is set a reference signal obtained by dividing 7 of shown.

The counting means 15 outputs the gain control signal CL1 at the L level as shown in FIG. 7D until the counting number in the counting means 15 reaches the predetermined number, and when the counting number reaches the predetermined number. The L level is changed to the H level, the H level gain control signal CL1 is output, and the gain changing period is ended. The gain change period T at this time is expressed by the following equation (1). T = (1 / fref) × M × Q (1) where fref is the frequency of the reference signal CL input to the variable frequency divider 14, M is the frequency division number of the variable frequency divider 14, and Q is the counting means 15. Is the count number of. As is clear from this equation (1), the gain change period T is fref, M, Q.
The value can be set in a wide range, and when the frequency synchronizing circuit incorporating the gain control signal generating means 10 is integrated into an IC, the same IC can easily be applied to various systems. It goes without saying that it also has the same effects as those of the first embodiment described above.

Fourth Embodiment 8 to 10 show Embodiment 4 of the present invention, in which the above-mentioned Embodiment 1 can change the output current in the sink operation and the source operation in the current control means 2 into two types. On the other hand, the fourth embodiment is different in that the output current in the sink operation and the source operation in the current control means 2 can be changed to three or more kinds, and other points are the same as described above. This is the same as the first embodiment.

In FIG. 8, reference numeral 2 denotes the first and second phase comparison outputs from the phase comparator 1 and a plurality of gain control signals CL1 to CLn, and the input gain control signal C
The output current having a value corresponding to L1 to CLn, that is, the output current is selected and controlled based on the gain control signals CL1 to CLn among the plurality of output currents, and the input first and second input currents are input.
The output current selected based on the phase comparison output of the output node 2c, or the output node 2c
It is a current control means consisting of a charge pump drawn from
A basic operation unit 2a that performs a source operation that gives a current from the output node 2c and a sink operation that draws a current through the output node 2c, and a current value in the source operation and the sink operation in the basic operation unit 2a are set to a plurality of gain It has a control unit 2b which is changed by the control signals CL1 to CLn, and specifically has the configuration shown in FIG.

In FIG. 9, the basic operating section 2a of the current control means 2 constituted by the first to seventh transistors T1 to T7 and the inverter Inv has the same structure as that of the first embodiment. Cage, control unit 2b
Has the following configuration. In FIG. 9, the same reference numerals as those shown in FIG. 2 indicate the same or corresponding parts.

In T10 (1) to T10 (n), the other main electrode (emitter electrode) is connected to the power supply potential node Vcc, and the control electrode (base electrode) is connected to the control electrode of the eighth transistor T8. A tenth transistor, which is a PNP bipolar transistor, forms a current mirror circuit with the eighth transistor T8, and forms a constant current circuit for flowing a constant current. In the fourth embodiment, The transistor size is the same as that of the eighth transistor T8, and currents (collector currents) I5 (1) to I5 (n) having the same value as the current I0 flowing through the eighth transistor T8 are passed.

D2 (1) to D2 (n) are corresponding tenth transistors T10 (1) to T10, respectively.
The anode electrode is connected to one main electrode (collector electrode) of (n), and the cathode electrode is the first diode D1.
Is a second diode connected to the cathode electrode of.

T13 (1) to T13 (n) are corresponding tenth transistors T10 (1) to T10, respectively.
(N) A thirteenth transistor, which is an N-type MOS transistor connected between one main electrode and the ground potential node and configured to receive gain control signals CL1 to CLn corresponding to control electrodes (gate electrodes), each of which is When the corresponding gain control signals CL1 to CLn mean a gain change, the gain control signals CL1 to CLn are turned off, and the corresponding tenth transistor T10
Currents I5 (1) to I5 flowing through (1) to T10 (n)
Second diodes D2 (1) to D2 corresponding to (n)
The current I5 (1) flowing through the corresponding tenth transistor T10 (1) to T10 (n) is caused to flow through one electrode of the eleventh transistor T11 via (n) and is turned on at other times. ) To I5 (n) are made to flow to the ground potential node, each of which is a predetermined one of a ninth transistor T9 and a plurality of tenth transistors T10 (1) to T10 (n) which form a constant current circuit. Is selected by a plurality of gain control signals CL1 to CLn, a total value of constant currents flowing through the selected transistors is generated, and the total value is supplied to the basic operation unit 2a to perform the source operation in the basic operation unit 2a. The selection circuit for defining the current value in the sink operation is provided with the eleventh and first
It is composed of two transistors T11 and T12.

[0084] Returning to FIG. 8, 10 when changing the frequency of the output signal f0 from the voltage-controlled oscillator 4, a plurality of gain control signals, respectively, which means for a predetermined period gain change (e.g. L level) CL1 A gain control signal generating means for generating CLn and giving the plurality of gain control signals CL1 to CLn to the current control means 2, specifically, FIG.
It looks like 0. In FIG. 10, the same reference numerals as those shown in FIG. 6 indicate the same or corresponding parts.

In FIG. 10, 15 (1) to 15 (n)
Are respectively set to different count numbers by different counter values input from the counter value input terminals 11e (only one is shown in FIG. 10, there are n, and they are connected by n wires). , The frequency of the output signal from the variable frequency divider 14 is counted by a reset signal (switching timing signal) input from the reset signal input terminal 11d, and the count value (predetermined number) is set to a binary value during this count period. One of the gain control signals CL1 to CL1 (L level in the fourth embodiment)
It is a counting means including a pulse counter that outputs CLn.

Next, the operation of the frequency synchronizing circuit configured as described above will be described. First, the frequency dividing value is set in the variable frequency divider 14 in the gain control signal generating means 10, and the count number is set in the plurality of counting means 15 (1) to 15 (n). The frequency division value is set in the variable frequency divider 14 in the same manner as in the third embodiment described above, and the counter value input terminals 1 are respectively provided for the plurality of counting means.
Set separate counts input from 1e. In this way, the frequency division value is set in the variable frequency divider 14 and the count number is set in each of the plurality of counting means 15 (1) to 15 (n), and then used as a frequency synchronizing circuit.

When the output signal f0 from the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr, the first and second phase comparison outputs are at L level, so that the current control means 2 has its output node 2c. Is in an electrically floating state (floating state), that is, a high impedance state, so that an output signal in the same state as in the first embodiment, that is, a signal synchronized with the reference frequency signal fr continues to be output. .

Further, even if the output signal f0 from the voltage controlled oscillator 4 is out of synchronization for some reason in such a state, all of the plurality of gain control signals CL1 to CLn from the gain control signal generating means 10 are generated. Is at the H level and a plurality of thirteenth transistors 13
Since all of (1) to 13 (n) are in the conductive state, the first
The current I6 flowing through the first transistor T11 is only the current I4 (current value is I0) flowing through the ninth transistor T9, and the phase of the output signal f0 from the voltage controlled oscillator 4 is the same as in the first embodiment. In the case of advancing with respect to the frequency signal fr, the sink operation for extracting the current of the current value I1 (= I0) from the input node 3a of the control voltage generating means 3 via the output node 2c during the pulse period of the first phase comparison output is performed. If the phase of the output signal f0 from the voltage controlled oscillator 4 is delayed with respect to the reference frequency signal fr, the pulse period of the second phase comparison output is applied to the input node 3a of the control voltage generating means 3 from the output node 2c to the current. The source operation for giving the current of the value I1 (= I0) is performed, and the output signal f0 of the voltage controlled oscillator 4 is synchronized with the reference frequency signal fr.

On the other hand, the output signal f from the voltage controlled oscillator 4
In the state where 0 is synchronized with the reference frequency signal fr,
When the frequency of the output signal f0 from the voltage controlled oscillator 4 is lowered, the phase comparator 1 raises the frequency of the controlled frequency signal fp, so that the phase difference between the controlled frequency signal fp and the reference frequency signal fr is reduced. Recognize and reference frequency signal f
The first phase comparison output having a pulse (for example, an H level pulse) having a width corresponding to the phase advance (corresponding to the frequency shift) of the controlled frequency signal fp for each cycle of r It outputs to the output line 9 and outputs the L-level second phase comparison output to the second phase comparison output line 8.

The current control means 2 which has received the first and second phase comparison outputs as described above passes through the output node 2c from the input node 3a of the control voltage generation means 3 during the pulse period of the first phase comparison output. Current value I1 (current value (n + 1) × I0 to 2 × I0 changes stepwise with the passage of time)
Performs sink operation to draw the current of. That is, the third transistor T3 that forms the output circuit of the basic operation unit 2a of the current control unit 2 that has received the first phase comparison output at the control electrode is in the conductive state during the pulse period of the first phase comparison output. Therefore, the first transistor T1 forming the output circuit of the basic operation unit 2a in the current control unit 2 which has received the inverted signal of the second phase comparison output at the control electrode continues to maintain the non-conduction state.

As a result, during the pulse period of the first phase comparison output, the output node 2c and the ground potential node become conductive via the third and fourth transistors T3 and T4, and the fourth transistor T4. an input node 3 of the control voltage generating means 3 a constant current value I1 becomes the current defined by
It is pulled out from a to the ground potential node through the output node 2c and the third and fourth transistors T3 and T4.

At this time, since the frequency of the output signal f0 is changed (switched), the reset signal is input to the reset input terminal 11d, and the plurality of counting means 15 (1) to 15 (n) which have received the reset signal. ) Are reset and their outputs are gain control signals CL1 to CLn.
Is changed from H level to L level, which means a gain change, and the frequency of the signal from the variable frequency divider 14 is started to be counted.

The L-level gain control signals CL1 to CLn are output until the count number reaches the predetermined number set by each of the plurality of counting means 15, and when the count number reaches the predetermined number set, the L level is changed to the H level. The level is changed to the H level, and the gain control signals CL1 to CLn of the H level are output, and the respective gain changing periods are ended. At this time, the gain changing periods are all different because the set count numbers are different.

A plurality of thirteenth transistors T13 (1)
To T13 (n) are corresponding gain control signals C
During the gain change period of L1 to CLn, the non-conduction state is set.
Therefore, the plurality of tenth transistors T10 forming a current mirror circuit together with the eighth transistor T8.
Currents I5 (1) to I5 flowing through (1) to T10 (n)
(N) (each current value is the same as I0) is the ninth transistor which forms a current mirror circuit with the eighth transistor T8.
Of the current I4 (current value is the same as I0) flowing through the transistor T9, and flows through the eleventh transistor T11. That is, (n + 1) × I0, n × I0, ..., 3 × I
The current of 0, 2 × I0 gradually changes to the eleventh transistor T
It flows to 11. A twelfth transistor T11 forming a current mirror circuit with the eleventh transistor T11.
Similarly, the current value of the current I3 flowing through 12 also becomes stepwise,
The current values for controlling the basic operation unit 2a by the control unit 2b are (n + 1) × I0, n × I0, ..., 3 × I0, 2
× I0 becomes stepwise.

Since the stepwise current I3 of the current value flows through the twelfth transistor T12, the stepwise current I3 of the current value also flows through the fifth transistor T5.
(N + 1) × I0, n × I in the sixth transistor T6 forming a current mirror circuit with the transistor T5 of
Current I of 0, ..., 3 × I0, 2 × I0 in stepwise current value
2 flows, and a similar current flows through the seventh transistor T7. The current value of the current I1 flowing through the fourth transistor T4 forming a current mirror circuit together with the seventh transistor T7 is the current I flowing through the seventh transistor T7.
It becomes the same as the current value of 2, and (n + 1) × I0, n × I
The stepwise current value becomes 0, ..., 3 × I0, 2 × I0.

Therefore, during the pulse period of the first phase comparison output, the current I1 is extracted from the input node 3a of the control voltage generating means 3 via the output node 2c, and the current value of the extracted current I1 elapses with time. With (n +
1) × I0, n × I0, ..., 3 × I0, 2 × I0. Therefore, the control voltage output from the control voltage generating means 3 current I1 is drawn through the output node 2c from the input node 3a is considerably larger have you to the initial <br/>, and stepwise decreased, the voltage control The oscillator 4 is operated so that the frequency of its output signal f0 is lowered. As a result, the output signal f0 of the voltage controlled oscillator 4 avoids the linking and the frequency can be lowered at a high speed.

When all of the plurality of gain control signals CL1 to CLn rise from L level to H level, all of the plurality of thirteenth transistors T13 (1) to T13 (n) are rendered conductive, and the control section 2b controls the basic state. Working part 2a
The current value for controlling the current becomes I0, and the current control means 2
Will be operated based on the current value I0. In this way, when the frequency of the controlled frequency signal fp matches the frequency of the reference frequency signal fr and is synchronized, the output signal f0 of the voltage controlled oscillator 4 has its frequency lowered and the reference frequency signal fr. It will be output in a state synchronized with.

The output signal f from the voltage controlled oscillator 4
When the frequency of 0 is increased, the phase comparator 1 uses the second phase composed of a pulse having a width corresponding to the phase delay (corresponding to the frequency shift) of the controlled frequency signal fp for each cycle of the reference frequency signal fr. The comparison output is output to the second phase comparison output line 8, and the L-level first phase comparison output is output to the first phase comparison output line 9.

The current control means 2 which has received the first and second phase comparison outputs as described above outputs a current value from the output node 2c to the input node 3a of the control voltage generation means 3 during the pulse period of the second phase comparison output. A source operation for giving a current of I1 (current value (n + 1) × I0 to 2 × I0 changes stepwise with the passage of time) is performed.

That is, the first transistor T1 constituting the output circuit of the basic operation section 2a of the current control means 2 which receives the inverted signal of the second phase comparison output at the control electrode.
Is in a conductive state during the pulse period of the second phase comparison output, and receives the first phase comparison output at the control electrode, and forms a third transistor T3 constituting the output circuit of the basic operation unit 2a in the current control means 2. Keep non-conducting state.

As a result, during the pulse period of the second phase comparison output, the output node 2c and the power supply potential node become conductive via the first and second transistors T1 and T2, and the second transistor T2. The current having the constant current value I1 defined by is from the power supply potential node to the second and first currents.
Is supplied to the input node 3a of the control voltage generating means 3 via the transistors T2 and T1 and the output node 2c.

At this time, since the frequency of the output signal f0 is changed (switched), the reset signal is input to the reset input terminal 11d, and the plurality of counting means 15 (1) to 15 (n) receiving the reset signal are received. ) Are reset and their outputs are gain control signals CL1 to CLn.
Is changed from H level to L level, which means a gain change, and the frequency of the signal from the variable frequency divider 14 is started to be counted.

The L-level gain control signals CL1 to CLn are output until the count number reaches the set number by each of the plurality of counting means 15, and when the count number reaches the set number, the L level is changed to the H level. The gain control signal changes to the level, the H level gain control signals CL1 to CLn are output, and the respective gain changing periods are ended. At this time, the gain changing periods are all different because the set count numbers are different.

A plurality of thirteenth transistors T13 (1)
To T13 (n) are corresponding gain control signals C
During the gain change period of L1 to CLn, the non-conduction state is set.
Therefore, the plurality of tenth transistors T10 forming a current mirror circuit together with the eighth transistor T8.
Currents I5 (1) to I5 flowing through (1) to T10 (n)
(N) (each current value is the same as I0) is the ninth transistor which forms a current mirror circuit with the eighth transistor T8.
Of the current I4 (current value is the same as I0) flowing through the transistor T9, and flows through the eleventh transistor T11. That is, (n + 1) × I0, n × I0, ..., 3 × I
The current of 0, 2 × I0 gradually changes to the eleventh transistor T
It flows to 11. A twelfth transistor T11 forming a current mirror circuit with the eleventh transistor T11.
Similarly, the current value of the current I3 flowing through 12 also becomes stepwise,
The current values for controlling the basic operation unit 2a by the control unit 2b are (n + 1) × I0, n × I0, ..., 3 × I0, 2
× I0 becomes stepwise.

Since the stepwise current I3 of the current value flows through the twelfth transistor T12, the stepwise current I3 of the current value also flows through the fifth transistor T5.
(N + 1) × I0, n × I in the second transistor T 2 forming a current mirror circuit with the transistor T5 of
Current I of 0, ..., 3 × I0, 2 × I0 in stepwise current value
1 flows. Therefore, during the pulse period of the second phase comparison output, the current I1 flows into the input node 3a of the control voltage generating means 3 via the output node 2c, and the current value of the flowing current I1 is (n + 1) × with the passage of time. I
0, n × I0, ..., 3 × I0, 2 × I0. Therefore, the control voltage output from the control voltage generating means 3 in which the current I1 flows into the input node 3a via the output node 2c is considerably large in the initial stage, and gradually increases, and the voltage controlled oscillator 4 outputs the output signal f0 of the output signal f0. The frequency will be increased. As a result, the frequency of the output signal f0 of the voltage controlled oscillator 4 can be increased at a high speed by avoiding its linking.

When all of the plurality of gain control signals CL1 to CLn rise from L level to H level, all of the plurality of thirteenth transistors T13 (1) to T13 (n) are rendered conductive, and the control section 2b controls the basic state. Working part 2a
The current value for controlling the current becomes I0, and the current control means 2
Will be operated based on the current value I0. In this way, when the frequency of the controlled frequency signal fp matches the frequency of the reference frequency signal fr and is synchronized, the output signal f0 of the voltage controlled oscillator 4 has its frequency increased and the reference frequency signal fr It will be output in a state synchronized with.

In this way, when the frequency of the output signal f0 from the voltage controlled oscillator 4 is changed, the output current in the sink operation or the source operation of the current control means 2 is (n +
1) × I0, n × I0, ..., 3 × I0, 2 × I0 are changed stepwise, so that the frequency of the output signal f0 can be changed at high speed while avoiding linking.
Therefore, in normal times, it has low power consumption and is resistant to noise,
Moreover, since frequency conversion can be performed at high speed while avoiding linking, when applied to a frequency synchronization circuit for both transmission / reception and reception in a radio device capable of transmission / reception, it has a very large practical effect. Moreover, the output current in the sink operation or the source operation of the current control means 2 is (n + 1) × I0, n × I0, ..., 3 × I0, 2 × I0.
Even if the configuration is changed stepwise as described above, it suffices to add a constant current circuit (transistor) for flowing a constant current and a switching element (transistor) controlled by a gain control signal, and increase the occupied area. Can be suppressed. Although the thirteenth transistors T13 (1) to T13 (n) are MOS transistors in the above embodiment, they may be bipolar transistors.

[0108]

Since the present invention is constructed as described above, it has the following effects.

Since the charge pump is composed of the basic operation section and the control section, it is possible to obtain the frequency synchronizing circuit capable of switching the gain of the output current and locking up at high speed without increasing the number of charge pumps. Moreover, since it is not necessary to send data from the outside every time the gain is switched and the gain can be switched automatically, a frequency synchronization circuit having a simple system configuration can be obtained.

Further, by obtaining the signal for gain switching by counting the reference frequency signal,
Stable gain switching is possible.

Further, as the gain control signal generating means,
By configuring with a variable frequency divider and a pulse counter, a large set value for gain switching can be obtained.

Further, since the value of the gain to be switched is controlled by the constant current circuit and the switching means, there is an effect that the area of the charge pump can be small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a current control unit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a control voltage generating means according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a timing chart of input / output waveforms of the phase comparator and the current control means according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a frequency synchronization circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a gain control signal generating means according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a timing chart in the gain control signal generating means according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a frequency synchronization circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a current control unit according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a gain control signal generating means according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a conventional frequency synchronization circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 phase comparator 2 current control means 2a basic operation part of current control means 2b gain control part 3 of current control means 3 control voltage generation means 4 voltage controlled oscillators 5 and 14 variable frequency divider 10 gain control signal generation means 11 control signal input Terminal 11a Clock signal input terminal 11b Serial data signal input terminal 11c Latch signal input terminal 12 Shift register 13 Latch circuit 15 Pulse counter fr Reference frequency signal fp Controlled frequency signal f0 Output frequency signal 1 / N, 1 / M Variable frequency divider Number of frequency divisions Dr1 to Drn Latch circuit output signals Sr1 to Srn Shift register output signals CL1 to CLn Gain control signal I0 Reference constant current I1 to In constant current

Claims (6)

(57) [Claims] 1. A frequency synchronizing circuit for outputting an output signal synchronized with a reference frequency signal, comprising a voltage controlled oscillator for outputting a signal having a frequency according to a control voltage as the output signal, and a control voltage for the voltage controlled oscillator. A control voltage generating means for supplying the control voltage generating means, a source operation for supplying a current to the control voltage generating means from a single output node in order to change the control voltage from the control voltage generating means, Current control means having a basic operation part for performing a sink operation for drawing out a current through the output node of, and a control part for changing a current value in the source operation and the sink operation in the basic operation part by a gain control signal, and a reference frequency. Signal and switching timing signal,
The gain control signal is changed to binary by the switching timing signal.
One of these values is used and based on the reference frequency signal
The number of cycles of the
Then, the gain control signal is set to the other value of the two values.
Gain control signal generating means for generating an in-control signal, and a frequency synchronizing circuit. 2. A frequency synchronizing circuit that outputs an output signal having a selected frequency among a plurality of frequencies in synchronization with a reference frequency signal, and outputs a signal having a frequency according to a control voltage as the output signal. A voltage controlled oscillator, a control voltage generating means for applying a control voltage to the voltage controlled oscillator, and a current from a single output node to the control voltage generating means for changing the control voltage from the control voltage generating means. The source operation to be applied and the basic operation section that performs the sink operation to draw the current from the control voltage generating means through the single output node, and the current value in the source operation and the sink operation in the basic operation section are when changing the frequency, the current control means having a control unit for changing the gain control signal for changing the predetermined time gain, group Receives quasi-frequency signals and switching timing signals,
The gain control signal is changed to binary by the switching timing signal.
One of these values is used and based on the reference frequency signal
The number of cycles of the
Then, the gain control signal is set to the other value of the two values.
Gain control signal generating means for generating an in-control signal, and a frequency synchronizing circuit. 3. A voltage controlled oscillator which receives a control voltage and outputs a signal having a frequency according to the control voltage, and which receives an output signal from the voltage controlled oscillator,
A variable that receives the frequency division value setting signal, divides the input output signal from the voltage controlled oscillator by the frequency division value based on the input frequency division value setting signal, and outputs it as a controlled frequency signal. A frequency divider, which receives the controlled frequency signal and the reference frequency signal from this variable frequency divider, compares the phases of the input controlled frequency signal and the reference frequency signal, and outputs a phase comparison output based on the comparison result. The phase comparator that outputs the phase comparator output and the gain control signal from this phase comparator, and the output current is controlled to a value according to the input gain control signal, and based on the input phase comparison output. Current control means for causing the output current to flow from a single output node or to be drawn from the single output node by an input node connected to the single output node of the current control means. Single output currents Dasa flows from the output node or the single output current drawn from the output node, providing to the voltage controlled oscillator a voltage that varies as a control voltage according to the control voltage generating means, the means,
And the reference frequency signal and the switching timing signal
Gain control signal by receiving and switching timing signal
One of the two values, and the reference frequency signal
Count the number of periods of the signal based on the
Value, the gain control signal is set to the other of the two values.
To generate a gain control signal.
A frequency synchronization circuit including a stage . 4. An output signal synchronized with a reference frequency signal is output.
In the frequency synchronizing circuit that applies a signal having a frequency according to the control voltage to the output signal
Output voltage control oscillator, control voltage to give control voltage to this voltage control oscillator
Generating means, for changing the control voltage from this control voltage generating means
Current to the control voltage generator from a single output node.
Source operation and the single output from the control voltage generator.
Basic to perform sink operation to draw current through force node
The operation part and the source operation and system operation in this basic operation part
Change the current value in the link operation by the gain control signal
Indicating the current control means, and the division value having a control unit which
Input serial data and output as parallel data
Shift register and parallel of this shift register
A latch circuit that latches data and this latch circuit
The divided value is determined by the data showing the divided value
The clock signal based on this determined divider value
Variable frequency divider that outputs by dividing the frequency and switching timing signal
Signal determines the number of periods of the output signal from this variable frequency divider.
Count a few, one of two values in this count period
And a counting means for outputting a gain control signal
The gain control signal generator that generates the gain control signal.
A frequency synchronizing circuit characterized in that stages are provided. 5. A plurality of frequencies synchronized with a reference frequency signal
The frequency that outputs the output signal with the selected frequency of
In the wave number synchronizing circuit, a signal having a frequency according to the control voltage is used as the output signal.
Output voltage control oscillator, control voltage to give control voltage to this voltage control oscillator
Generating means, for changing the control voltage from this control voltage generating means
Current to the control voltage generator from a single output node.
Source operation and the single output from the control voltage generator.
Basic to perform sink operation to draw current through force node
The operation part and the source operation and system operation in this basic operation part
Change the current value during
Gain control to change the gain for a predetermined period when changing
A current control unit having a control unit that changes according to a control signal,
And serial data indicating the frequency division value are input, and parallel
The shift register that outputs as data and this shift register
A latch circuit that latches the parallel data of the
The data indicating the above division value latched in the latch circuit of
The frequency division value was determined by this, and the clock signal was determined by this
A variable divider that divides and outputs based on the division value
The output signal from this variable frequency divider
A predetermined number of cycles of the number is counted, and this count period is binary.
A cow that outputs a gain control signal that is one of the values
And a gain control for generating a gain control signal.
Frequency synchronization characterized by providing control signal generating means
circuit. 6. A control voltage is received, and the control voltage is received.
A voltage controlled oscillator that outputs a signal having a frequency, while receiving an output signal from this voltage controlled oscillator,
Receives the frequency division value setting signal, and based on the input frequency division value setting signal
From the above voltage controlled oscillator input with the divided value based on
The output signal of is divided and output as a controlled frequency signal.
A variable frequency divider, the controlled frequency signal and the reference frequency signal from the variable frequency divider.
Signal and the input controlled frequency signal and reference frequency
The phase with the signal is compared and the phase ratio based on the comparison result
The phase comparator that outputs the comparison output, the phase comparison output from this phase comparator and the gain control signal.
Signal output according to the input gain control signal
The current is controlled and the input phase comparison output
Based on the above, the output current flows from a single output node.
Or current control drawn from the single output node above
Means, the input node is connected to a single output node of this current control means.
Current from the single output node of the current control means.
Output current, or drawn from the single output node above.
Control voltage is a voltage that changes according to the output current
Control voltage generating means for giving the voltage controlled oscillator as
And serial data indicating the frequency division value is input,
Shift register that outputs as
A latch circuit that latches parallel data of a register,
Data indicating the frequency division value latched by this latch circuit
The frequency division value is determined by the clock signal
A variable divider that divides the frequency based on the
Output from this variable frequency divider by switching timing signal
A predetermined number of signal cycles are counted, and this counting period 2
A gain control signal that outputs one of the values
And a gain for generating a gain control signal.
A frequency synchronizing circuit including a control signal generating means.