JP3006540B2 - PLL frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer, and more particularly, to a PLL that switches the switching characteristics of a charge pump circuit between a phase lock and a lock.
It relates to an L frequency synthesizer.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a configuration example of a conventional PLL frequency synthesizer.

In this conventional example, as shown in FIG. 5, a voltage controlled oscillator (hereinafter, referred to as VCO) 105 for generating and outputting a frequency signal fout having a predetermined frequency, and a VCO 1
The frequency divider 105 generates a signal signal fsig by dividing the frequency signal fout output from the programmable frequency divider 105, and outputs a reference signal fref input from the outside and a signal output from the programmable frequency divider 101. The phase comparator 10 generates a phase difference signal by comparing the phase with the signal fsig and outputs the signal.
2, a charge pump circuit 103 that outputs a current corresponding to the phase difference signal output from the phase comparator 102, and integrates the current output from the charge pump circuit 103 and removes noise components to convert the voltage into a voltage. And a loop filter 104.
The frequency of the frequency signal output from the VCO 105 is controlled based on the voltage converted in.

The charge pump circuit 103 includes a constant current source 131 for supplying a current to the output A, a constant current source 132 for extracting a current from the output A, and an UP of the phase comparator 102.
The switching transistor 130 includes a switching transistor 130 having a gate connected to the output terminal, and a switching transistor 133 having a gate connected to the DOWN output terminal of the phase comparator 102.

By configuring the PLL loop in this way, an arbitrary frequency signal satisfying fout = fref × N can be obtained by setting the frequency division number N.

The operation of the phase comparator 102 and the charge pump circuit 103 in the PLL frequency synthesizer configured as described above will be described below.

FIG. 6 is a timing chart for explaining the operation of the phase comparator 102 and the charge pump circuit 103 shown in FIG.

[0008] As shown in FIG.
When an “L” level signal is output to the P output terminal and the DOWN output terminal, the switching transistor 130
Is turned on, the switching transistor 133 is turned off, and the output A is supplied to the constant current source 132.
(Ip (source)).

When an "H" level signal is output to the UP output terminal and the DOWN output terminal of the phase comparator 102, the switching transistor 130 is turned off and the switching transistor 133 is turned off.
In the N state, the constant current Ip determined by the constant current source 133 is extracted from the output A (Ip (sink)).

When the "H" level signal is output to the UP output terminal of the phase comparator 102 and the "L" level signal is output to the DOWN output terminal, both the switching transistor 130 and the switching transistor 133 are turned off. Therefore, at the output A, neither current flowing nor extracting is performed.

When the "L" level signal is output to the UP output terminal of the phase comparator 102 and the "H" level signal is output to the DOWN output terminal, both the switching transistor 130 and the switching transistor 133 are turned on. Therefore, if Ip (source) = Ip (sink), no current is output from the output A.

In general, a PLL frequency synthesizer used for wireless communication requires a high C / N. Therefore, a reset signal delay circuit and an anti-backlash circuit are provided in a phase comparator (refer to “PLL frequency synthesizer.
Circuit Design Method, by Toshiyuki Ozawa, published on July 10, 1994 by Sogo Denshi Publishing Co., Ltd., p. 135, 136).

However, the provision of the delay circuit and the like prevents the error signal from being output even when there is a phase difference. However, even when the signal signal and the reference signal are completely input in the same phase, A state occurs in which the UP output signal of the phase comparator 102 (the switching transistor 130 is turned on) and the DOWN output signal (the switching transistor 133 is turned on) are output.

[0014]

As described above, in the conventional PLL frequency synthesizer, in order to realize a high C / N ratio, the phase comparator is provided with a delay circuit for avoiding a dead zone. .

However, due to the phase difference signal generated by the phase comparator, the switching operation of the charge pump circuit causes a current fluctuation in the output, and the C / N
Are deteriorated, and the reference leak is increased.

The condition where the C / N is high and the reference leak is small is given by the following equation.

[0017]

(Equation 1)

Therefore, in the switching transistor in the charge pump circuit, the gate / diffusion layer coupling capacitance is made as small as possible, thereby reducing the high-speed switching operation and the switching noise (the constant current source is not affected by the switching operation). ).

[0019] However, reducing the size of the switching transistor, the on-resistance is large Ri Na, switch
Voltage drop in the switching transistor increases,
The variable output voltage range of the charge pump circuit (the output voltage range in which the charge pump output current Ip can be obtained at a constant value), which is the voltage range that can be obtained at point A in FIG. In particular, a HIGH channel (hereinafter, referred to as Hch) (HCO) (VCO) that is separated from the center frequency of the VCO (VCO control voltage = oscillation frequency at VCC / 2)
Channel with high output frequency = channel with high VCO control voltage) or LOW channel (hereinafter, Lch
(Referred to as channel with low output frequency of VCO = V
This causes a problem that the settling time to the channel having a low CO control voltage becomes long.

The present invention has been made in view of the above-mentioned problems of the prior art, and has a high C / N ratio without delaying the settling time at all channel frequencies. An object of the present invention is to provide a PLL frequency synthesizer that can realize a spectral characteristic with little reference leak.

[0021]

In order to achieve the above object, the present invention provides a voltage controlled oscillator that generates and outputs a frequency signal having a predetermined frequency, and separates the frequency signal output from the voltage controlled oscillator. A programmable frequency divider, a phase comparator that compares the phases of a reference signal input from the outside and a frequency signal divided by the programmable frequency divider, and outputs a comparison result as a phase difference signal; A constant current source for determining an output current;
A plurality of switching elements provided on a power supply line, and the switching elements are turned on / off according to a phase difference signal output from the phase comparator.
A charge pump circuit that outputs a current determined by the constant current source ; and a loop filter that integrates the current output from the charge pump circuit and removes a noise component to convert the voltage into a voltage. In the PLL frequency synthesizer in which the frequency of the frequency signal output from the voltage controlled oscillator is controlled based on the voltage converted in the above, the charge pump circuit includes a first transistor having a large size and a small on-resistance; A second transistor connected in parallel with the first transistor and having reduced gate / diffusion layer capacitance and reduced switching noise as the switching element; At the time, the output current is controlled by the first transistor and the second transistor, After phase pull-completion stops the operation of said first transistor, controlled only by the output current the second transistor, the switching element,
The switching characteristic is variable.

[0022]

[0023]

[0024] Further, there is provided a programmable counter for counting a reference signal inputted from the outside and outputting a signal based on the count value, and the switch control of the switching element is performed based on the signal output from the programmable counter. It is characterized by being performed.

(Operation) In the present invention configured as described above, the charge pump circuit operates so that the output variable voltage range becomes wide at the time of phase pull-in and the switching noise generated after the phase pull-in is completed. So
The C / N characteristic and the reference leak characteristic are improved while maintaining a stable settling time at all set channel frequencies.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a frequency PLL synthesizer according to the present invention.

In this embodiment, as shown in FIG. 1, a voltage-controlled oscillator (hereinafter referred to as VCO) 5 for generating and outputting a frequency signal fout having a predetermined frequency and a frequency signal fout output from the VCO 5 are separated. The frequency divider generates and outputs a signal signal fsig, a reference signal fref input from the outside, and a signal signal f output from the programmable frequency divider 1.
a phase comparator 2 that generates and outputs a phase difference signal by comparing the phase with the sig, and a charge pump circuit 3 that outputs a current corresponding to the phase difference signal output from the phase comparator 2. A loop filter 4 that integrates the current output from the charge pump circuit 3 and removes noise components to convert it into a voltage; and a programmable filter that counts an externally input reference signal fref and outputs a signal based on the count value. And a counter 6. The frequency of the frequency signal output from the VCO 5 is controlled based on the voltage converted by the loop filter 4. The signal output from the programmable counter 6 is Are input to the charge pump circuit 3 together with the phase difference signal output from.

The charge pump circuit 3 includes a constant current source 31 for supplying a current to the output A, a constant current source 32 for extracting a current from the output A, and a switching device having a gate connected to the output terminal UPa of the phase comparator 2. Transistor 30a
And an inverter 20 having an input terminal connected to the output terminal UPa of the phase comparator 2, and a signal output from the programmable counter 6 and a signal output from the inverter 20, and the logical product of both signals is inverted. A NAND gate 21 for outputting a signal and an output terminal DOW of the phase comparator 2
A signal output from the Na and a signal output from the programmable counter 6 are input, and an AND gate 22 that outputs a logical product of the signals, and an output terminal DOW of the phase comparator 2
Switching transistor 3 whose gate is connected to Na
3a, a switching transistor 30b connected in parallel with the switching transistor 30a and having a gate connected to the output terminal UPb of the NAND gate 21, and a switching transistor 33a connected in parallel with the switching transistor 33a and a gate connected to the output terminal DOWNb of the AND gate 22. And a switching transistor 33b.
The switching transistors 30b and 33b serving as the first transistors have a gate size (W (gate width)).
/ L (gate length)), the on-resistance is small, and the switching transistors 30a and 33a, which are the second transistors, have a small gate-diffusion layer coupling capacitance, and have high-speed switching operation and low switching. Noise can be realized. The switching transistors 30b and 33b need to be designed in consideration of the fact that the output variable voltage range of the charge pump circuit 3 is determined by the on-resistance (size) of the switching transistors 30b and 33b. At 30a and 33a, the constant current sources 31,
Care must be taken to design the minimum size that allows the output current Ip determined by 32 to flow.

Here, the programmable counter 6 counts the reference signal fref input from the outside, and outputs an "H" level signal until the count value reaches a preset count value. When the count value reaches the set value, an “L” level signal is output. The preset count value of the programmable counter 6 is equal to the count time (fref
(The number of times of counting) is almost equal to the time when the phase pull-in operation is completed.

Hereinafter, control of the charge pump circuit 3 in the PLL frequency synthesizer configured as described above will be described.

First, at the time of phase pull-in, since the count value of the programmable counter 6 has not reached the preset count value, the programmable counter 6 outputs an "H" level signal.
Therefore, the logic of the signal output to the output terminal UPa of the phase comparator 2 and the signal output to the output terminal UPb of the NAND gate 21 and the signal output to the output terminal DOWNNa of the phase comparator 2 The logic of the signal output to the output terminal DOWNb of the AND gate 22 matches the logic of the signal output to the output terminal DOWNb.

The switching transistor 30a is controlled by the signal output to the output terminal UPa of the phase comparator 2, and the output terminal UPb of the NAND gate 21
The switching transistor 30b is controlled by the signal output to the constant current source 31 and the current Ip (so
urce) to the output A is determined. At this time,
A signal output to the output terminal UPa of the phase comparator 2,
That is, the signal applied to the gate of the switching transistor 30a and the output terminal UPb of the NAND gate 21
, Ie, the logic of the signal applied to the gate of the switching transistor 30b matches each other, the switching transistors 30a, 3
0b is simultaneously turned ON or OFF.

The output terminal DOWNa of the phase comparator 2
The output of the current Ip (sink) determined by the constant current source 32 is controlled by the switching transistor 33a controlled by the signal output to the output terminal DOWNb of the AND gate 22. A withdrawal from A is determined. At this time, the signal output to the output terminal DOWNa of the phase comparator 2, that is, the signal applied to the gate of the switching transistor 33a and the AND gate 22
Of the signal output to the output terminal DOWNb, that is, the signal applied to the gate of the switching transistor 33b also coincides with each other.
The state becomes the FF state. Here, the switching transistor 3
0a is the on-resistance of the switching transistor 30
Assuming that the on-resistance of Rb is Rb, two transistors
The ON resistance in the N state is (Ra × Rb)
/ (Ra + Rb), and the resultant resistance is Ra> Rb
, The switching transistor 30b is in the ON state
(During the phase pull-in operation)
You.

With the above configuration, the PL
During the phase pull-in operation in the L frequency synthesizer,
Switching transistor 30 of charge pump circuit
b, 33b have low on-resistance, and the switching
As a result, the voltage drop generated in the transistor is reduced, and the voltage range that can be taken at point A in FIG.
Variable output voltage range becomes wide that. Therefore, even if the frequency of the frequency signal output from the VCO 5 is set to any channel frequency (oscillation frequency), the phase pull-in operation can be realized at a stable speed (settling time) without causing overdamping.

Thereafter, when the phase pull-in is almost completed,
The count value of the programmable counter 6 reaches a preset value, and the programmable counter 6 outputs an “L” level signal.

Then, the output terminal U of the NAND gate 21
Pb becomes “H” level, whereby the switching operation of the switching transistor 30b is stopped.

The output terminal DOW of the AND gate 22
Nb goes to the “L” level, whereby the switching operation of the switching transistor 33b is stopped.

That is, only the switching transistor 30 a having a small gate-diffusion layer coupling capacitance is controlled by the signal output to the output terminal UPa of the phase comparator 2, and the output of the current Ip (source) determined by the constant current source 31 is controlled. A is determined, and the signal output to the output terminal DOWNb of the phase comparator 2 causes the switching transistor 3 having a small gate-diffusion layer coupling capacitance to be output.
3a is controlled, and the current Ip (si
nk) from output A is determined.

With such a configuration, the PLL
When the phase pull-in operation of the frequency synthesizer is almost completed, the switching transistors 30b and 33b having a small on-resistance used during the phase pull-in are set to the OFF state, and the current flowing (Ip (source)) as the switching operation of the charge pump circuit 3 is performed. ) And current extraction (Ip (sink)) are determined only by the switching transistors 30a and 33a having a small gate-diffusion layer coupling capacitance, so that switching control can be performed at high speed and with low switching noise. The fluctuation of the output voltage caused by the above can be suppressed, and the fluctuation of the VCO oscillation frequency (directly proportional to the fluctuation of the output voltage) and the reference leak can be reduced. Note that the count value of the programmable counter 6 is set to an optimum value such that the switching transistor switching operation of the charge pump circuit 3 does not affect the settling time.

In the present embodiment configured as described above, the characteristics of the switching transistors in the charge pump circuit 3 are set so that the on-resistance is reduced during the phase pull-in operation. The output variable voltage range is widened so that the settling time does not depend on the set channel frequency, and when the phase pull-in is almost completed, the switching noise is reduced to reduce the fluctuation of the charge pump output voltage. And, it is controlled to suppress the reference leak.

The result of computer simulation of the above-mentioned PLL frequency synthesizer will be described below.

FIGS. 2 and 3 are diagrams showing VCO control voltage characteristics in the PLL frequency synthesizer.
Is the VC in the PLL frequency synthesizer shown in FIG.
FIG. 1B is a diagram showing O control voltage characteristics, and FIG.
FIG. 4 is a diagram illustrating VCO control voltage characteristics in a frequency synthesizer.

In the PLL frequency synthesizer shown in FIG. 1, the gate size of each switching transistor in the charge pump circuit 3 (gate width (μm) /
Gate length (μm))
a = 100/1, switching transistor 30b = 4
00/1, switching transistor 33a = 100 /
1, the switching transistor 33b is set to 400/1, and in the PLL frequency synthesizer shown in FIG. 5, the gate size of each switching transistor in the charge pump circuit 103 is set as follows: switching transistor 130 = 500/1, switching transistor 33 = 500/1.

In FIG. 2, time is plotted on the horizontal axis, and VCO control voltage is plotted on the vertical axis.
The result of comparing the time (settling time) for convergence from ch (0.5 V) to Hch (2.0 V) between the present invention and the conventional example is shown. In FIG. 3, the VCO control voltage is sufficient. The waveform at the time (3.5 μs to 4 μs) converged to (1) is enlarged and displayed (1.99 V to 2.01 V). In FIG. 3, the peak value of the waveform appearing in a cycle of 10 ns indicates the reference leak amount (this simulation is performed at a reference signal of 100 MHz), and the fluctuation of the entire waveform with respect to the VCO setting control voltage 2 V indicates C / N. It is safe to think that it will be decided.

As can be seen from the simulation results shown in FIGS. 2 and 3, the present invention can improve the reference leak and the C / N characteristics with the same settling time as the conventional example.

(Other Embodiment) FIG. 4 is a diagram showing another embodiment of the frequency PLL synthesizer of the present invention.

In this embodiment, as shown in FIG. 4, a programmable counter 6 is not provided as compared with the one shown in FIG. 1, and a lock input from the outside to control the switching transistor in the charge pump circuit 3 is provided. Detection signal (L
D signal), and the other configuration is the same.

The operation of the charge pump circuit 3 in this embodiment is exactly the same as that shown in FIG. 1. However, in this embodiment, since the programmable counter 6 is not required, the switching transistor can be easily implemented with a small circuit scale. Switching control can be performed.

[0050]

As described above, in the present invention,
Because the charge pump circuit operates so that the output variable voltage range becomes wider during phase pull-in and the switching noise that occurs after phase pull-in is completed,
C / N characteristics and reference leak characteristics can be improved stably at all set channel frequencies while maintaining the settling time.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a frequency PLL synthesizer of the present invention.

2A and 2B are diagrams showing VCO control voltage characteristics in a PLL frequency synthesizer, and FIG. 2A shows the PLL shown in FIG.
FIG. 2B is a diagram illustrating a VCO control voltage characteristic in the frequency synthesizer, and FIG. 2B is a diagram illustrating a VCO control voltage characteristic in the PLL frequency synthesizer illustrated in FIG.

3A and 3B are diagrams showing VCO control voltage characteristics in a PLL frequency synthesizer, and FIG. 3A shows the PLL shown in FIG.
FIG. 2B is a diagram illustrating a VCO control voltage characteristic in the frequency synthesizer, and FIG. 2B is a diagram illustrating a VCO control voltage characteristic in the PLL frequency synthesizer illustrated in FIG.

FIG. 4 is a diagram showing another embodiment of the frequency PLL synthesizer of the present invention.

FIG. 5 is a diagram illustrating a configuration example of a conventional PLL frequency synthesizer.

FIG. 6 is a timing chart for explaining operations of the phase comparator and the charge pump circuit shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Programmable frequency divider 2 Phase comparator 3 Charge pump circuit 4 Loop filter 5 Voltage controlled oscillator (VCO) 6 Programmable counter 20 Inverter 21 NAND gate 22 AND gate 30a, 30b, 33a, 33b Switching transistor 31, 32 Constant current source

Claims (2)

(57) [Claims] 1. A voltage-controlled oscillator for generating and outputting a frequency signal having a predetermined frequency, a programmable frequency divider for dividing a frequency signal output from the voltage-controlled oscillator, and a reference signal input from the outside And a phase comparator that compares the phase of the frequency signal divided by the programmable frequency divider and outputs the comparison result as a phase difference signal; a constant current source that determines an output current; Electric
And a plurality of switching elements provided to the source line, depending on the phase difference signal outputted from said phase comparator
When the switching element is turned on / off,
A charge pump circuit that outputs a current determined by the constant current source ; and a loop filter that integrates the current output from the charge pump circuit and removes a noise component to convert the voltage into a voltage. Based on the converted voltage,
In a PLL frequency synthesizer in which the frequency of a frequency signal output from the voltage controlled oscillator is controlled, the charge pump circuit includes: a first transistor having a large size and a small on-resistance; and a parallel connection with the first transistor. A second transistor in which the gate / diffusion layer capacitance is reduced and switching noise is suppressed as the switching element, an output variable voltage range is variable, and the first transistor and the An output current is controlled by a second transistor, and after the phase pull-in is completed, the operation of the first transistor is stopped, an output current is controlled only by the second transistor, and the switching element has a variable switching characteristic. A PLL frequency synthesizer, comprising: 2. The PLL frequency synthesizer according to claim 1 , further comprising: a programmable counter that counts a reference signal input from the outside and outputs a signal based on the count value, and a signal output from the programmable counter. Wherein the switching control of the switching element is performed based on the following.