JP2003289248A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To offer a PLL circuit in which the S/N ratio for the output signal is high, the maximum lock up time is short, and the cost is low. <P>SOLUTION: A crystal voltage controlled oscillator 1 is used in order to get a high S/N ratio of the output signal. An M phase-phase shift circuit 4 creates M phase signals of nearly the same frequency to a reference signal SREF, a selector 5 selects one of the M phase signals which provides a minimum phase difference to the reference signal SREF, and outputs it as a comparison signal SCOM. As a result, since a phase difference between the comparison signal SCOM and the reference signal SREF becomes small, the maximum lock up time can be shortened. The crystal voltage controlled oscillator used is only one and therefore, the cost can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lock) which operates to synchronize an output signal with a reference signal in phase.
ed Loop) circuit.

[0002]

2. Description of the Related Art A general configuration of a conventional PLL circuit is shown in FIG.
Shown in. The PLL circuit of FIG. 9 includes a voltage controlled oscillator 1 ′,
It is composed of a 1 / N frequency divider 2, a phase comparator 6 ′, and a low-pass filter 7. The voltage controlled oscillator 1 ′ oscillates an oscillation signal S _OUT having a frequency according to the control voltage V _CON output from the low pass filter 7. 1 / N frequency divider 2
Is an oscillation signal S _OUT output from the voltage controlled oscillator 1 ′.
_{Is divided} by 1 / N to generate a comparison signal S _COM having the same frequency as the reference signal S _REF, and the comparison signal S _COM is _supplied to the phase comparator 6 ′.
Send to. The phase comparator 6 ′ compares the phase of the comparison signal S _{COM with} the phase of the reference signal S _REF to generate a phase error signal Pd corresponding to the phase difference between the comparison signal S _COM and the reference signal S _REF, and The phase error signal Pd is sent to the low pass filter 7. Low pass filter 7 removes high frequency components and generates a control voltage V _CON from the phase error signal Pd, and sends the control voltage V _CON to the voltage controlled oscillator 1 '.

When the phase of the reference signal S _REF coincides with the phase of the comparison signal S _COM , the frequency of the oscillation signal S _OUT is equal to the frequency of the reference signal S _{REF and} the frequency division ratio N of the 1 / N frequency divider 2 is N.
(N is a natural number of 2 or more). Also,
Reference signal S when the comparison signal S _COM phase relative to the phase of the _REF is delayed, the comparison signal S _COM phase reference signal S _REF
The control voltage V _CON increases by ΔV as compared with when the phase coincides with the phase A, and the frequency of the oscillation signal S _OUT increases by ΔF as the control voltage V _CON increases. Meanwhile, when the advanced comparison signal S _COM phase relative phase of the reference signal S _REF is the control voltage V _CON than when the comparison signal S _COM phase matches the phase of the reference signal S _REF [Delta] V And the frequency of the oscillation signal S _OUT decreases by ΔF in accordance with the decrease in the control voltage V _CON .

By operating as described above, the phase of the oscillation signal S _OUT , which is the output signal of the PLL circuit, will be changed to the phase of the output signal of the PLL circuit after a while even when the power is turned on or the phase synchronization is lost (hereinafter, referred to as the power is turned on). The phase of the reference signal S _REF is synchronized. The time from when the power is turned on to when the synchronization is restored again is called the lockup time. The lockup time will be described below.

When the phase of the oscillation signal S _{OUT and} the phase of the reference signal S _REF do not match, the frequency of the oscillation signal is higher than when the phase of the oscillation signal S _{OUT and} the phase of the reference signal S _REF match. Is shifted by ΔF, so when the phase of the oscillation signal S _OUT does not match the phase of the reference signal S _REF , the comparison signal S
The frequency difference between _COM and the reference signal S _REF is ΔF / N [Hz]
Becomes Therefore, even if the comparison signal S _COM is phase-shifted by 360 degrees with respect to the reference signal S _REF , N / ΔF [sec]
It takes. In a normal PLL circuit, control is divided depending on _whether the phase difference between the comparison signal S _COM and the reference signal S _REF is advanced or delayed, and in this case, the worst phase shift is 180 degrees. Therefore, the maximum lockup time T'is represented by the equation (1). T ′ = 1/2 × N / ΔF [second] ... (1)

An LC oscillator is generally used as the voltage controlled oscillator 1 ', and ΔF is large. Therefore, the lockup time did not become too long.

[0007]

On the other hand, when a signal with small jitter and high S / N is required as the output signal, the crystal voltage controlled oscillator 1 as shown in FIG. 10 is used instead of the voltage controlled oscillator 1 '. . In addition, in FIG.
The same parts as those in FIG.

However, the crystal voltage controlled oscillator 1 has a problem that the maximum lockup time becomes too long because the value of ΔF is very small. As is clear from the equation (1), the maximum lockup time was too long especially when the frequency division ratio N of the 1 / N frequency divider 2 was large.

For example, a crystal oscillator of 20 [MHz], 5
In the case of the reference signal of [kHz], the value of the frequency division ratio N of the 1 / N frequency divider 2 is 4000, and the value of ΔF is generally 200 [H
z], the maximum lockup time is about 10 seconds from the above formula (1).

As a PLL circuit capable of solving such a problem, a PLL circuit as shown in FIG. 11 has been proposed. The PLL circuit of FIG. 11 is configured by configuring the PLL circuit of FIG. 10 in two stages. The PLL circuit shown in FIG.
Dividing ratio of the PLL circuit 100 in the first stage the total division ratio N N ₁
(N ₁ is a natural number of 2 or more) and the second-stage PLL circuit 200
The frequency division ratio N ₂ (N ₂ is a natural number of 2 or more) is divided into two to reduce the absolute value of the frequency division ratios N ₁ and N ₂ , thereby increasing the maximum lockup time T ″ (= 1. / 2 x (N ₁ + N ₂ ) / Δ
F) was shortened. However, such a two-stage configuration requires two crystal resonators, which causes a problem of high cost.

In view of the above problems, it is an object of the present invention to provide a PLL circuit that has a high S / N of an output signal, a short maximum lockup time and a low cost.

[0012]

In order to achieve the above object, in a PLL circuit according to the present invention, a crystal voltage controlled oscillator having a crystal oscillator, and an oscillation signal of the crystal voltage controlled oscillator are divided and phased. A signal generating unit that shifts to generate a plurality of signals having substantially the same frequency as a reference signal supplied from the outside and having different phases in synchronization with the oscillation signal of the crystal voltage controlled oscillator; Selection means for selecting one of the signals and outputting it as a comparison signal, and a phase for comparing the phases of the comparison signal and the reference signal and outputting a phase error signal and a control signal according to the phase difference. A comparator and a filter for generating a control voltage according to the phase error signal, wherein the selection means performs a selection operation according to the control signal, and the crystal voltage controlled oscillator Configured to as to output an oscillation signal corresponding to the control voltage.

The plurality of signals may be signals whose phases are shifted by an interval obtained by dividing one cycle of the reference signal by a predetermined natural number of 2 or more.

The signal generating means divides the oscillation signal of the crystal voltage controlled oscillator by 1 / N, and the output signal of the 1 / N divider by 1 / M. 1 /
An M-frequency divider and an M-bit shift register that uses the output signal of the 1 / M frequency divider as a data signal and the output signal of the 1 / N frequency divider as a clock signal may be provided.

Further, it is preferable that the selecting means selects a signal having a minimum phase difference from the reference signal from the plurality of signals.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of a PLL circuit according to the present invention. The same parts as those in FIG. 10 are designated by the same reference numerals.

The PLL circuit of FIG. 1 comprises a crystal voltage controlled oscillator 1, a 1 / N frequency divider 2, and a 1 / M frequency divider phase comparator 3.
, M phase shift circuit 4, selector 5, phase comparator 6, and low-pass filter 7. Note that N and M are natural numbers of 2 or more.

The crystal voltage controlled oscillator 1 oscillates an oscillation signal S _OUT having a frequency corresponding to the control voltage V _CON output from the low pass filter 7. The 1 / N frequency divider 2 frequency-divides the oscillation signal S _OUT output from the crystal voltage controlled oscillator 1 by 1 / N, and the frequency-divided signal S _DIV1 generated as a result is divided into 1 / M frequency dividers 3 and M. It is sent to the phase shift circuit 4. The 1 / M frequency divider 3 outputs the frequency division signal S _DIV1 output from the 1 / N frequency divider 2.
Is divided by 1 / N, and the divided signal S _DIV2 generated as a result is sent to the M-phase phase shift circuit 4.

The M-phase phase shift circuit 4 uses the _divided signal S _DIV2
To generate an M-phase signal. The selector 5 uses the control signal Ph
A signal having the smallest phase difference from the reference signal S _REF is selected from among the M-phase signals based on the above, and the selected signal is output as the comparison signal S _COM . The phase comparator 6 compares the phase of the comparison signal S _{COM with} the phase of the reference signal S _REF to generate a phase error signal Pd and a control signal Ph according to the phase difference between the comparison signal S _COM and the reference signal S _REF. , The phase error signal Pd is sent to the low-pass filter 7, and the control signal Ph is sent to the selector 5. Low pass filter 7 generates a control voltage V _CON by removing high frequency components from the phase error signal Pd, and sends the control voltage V _CON to a crystal voltage controlled oscillator 1.

In this embodiment, the crystal voltage controlled oscillator 1 uses a crystal voltage controlled oscillator having a positive correlation between the control voltage V _CON and the oscillation frequency. An example of the configuration of such a crystal voltage controlled oscillator 1 is shown in FIG.

One end of the crystal unit 10 is the inverter circuit 1
1 input side, one end of the resistor R1, and one end of the capacitor C1. The output side of the inverter circuit 11 and the resistor R
The other end of 1 is connected to the output terminal 12. Capacitor C
The other end of 1 is connected to the cathode of the variable capacitance diode D1. The anode of the variable capacitance diode D1 is grounded. Then, the capacitor C1 and the variable capacitance diode D1
One end of the resistor R2 is connected to the connection node with
The other end of is connected to the control voltage input terminal 13.

The other end of the crystal oscillator 10 is connected to the cathode of the variable capacitance diode D2 via the inductor L1. One end of the resistor R3 is connected to the connection node between the inductor L1 and the variable capacitance diode D2, and the other end of the resistor R3 is connected to the control voltage input terminal 13. The anode of the variable capacitance diode D2 is connected to one end of the capacitor C2 and the resistor R4.
Connected to one end of. The other end of the resistor R4 is grounded. The other end of the capacitor C2 is connected to one end of the resistor R5 and one end of the capacitor C3. The other end of the resistor R5 is connected to the output terminal 12. The other end of the capacitor C3 is connected to one end of the capacitor C4 and one end of the inductor L2. The other end of the capacitor C4 and the other end of the inductor L2 are grounded.

The crystal voltage controlled oscillator 1 is controlled as described above.
Control voltage V_CONHas a positive correlation between
Then, the phase comparator 6 and the loop filter 7 are connected to the reference signal S
_REFComparison signal S for the phase of_COMWhen the phase of
If the oscillation frequency of the crystal voltage controlled oscillator 1 is reduced,
Comparison signal S_COMPhase and reference signal S_REFMatch the phase of
To control voltage V_CONTo reduce the reference signal S_REFPlace of
Comparison signal S for phase _COMWhen the phase of is delayed, water
Increase the oscillation frequency of the crystal voltage controlled oscillator 1
S_COMPhase and reference signal S_REFTo match the phase of
Control voltage V_{CO N}To increase.

Of the phase comparator 6 which operates as described above.
One configuration example is shown in FIG. Comparison signal S _COMIs supplied at the end
The child 14 is the second input terminal of the OR circuit 15 and the AND circuit 1
7 to the first input terminal. Output terminal of OR circuit 15
Is connected to the first input terminal of the NAND circuit 18,
The output terminal of the D circuit 16 is the first input terminal of the NOR circuit 19.
And the output terminal of the AND circuit 17 is connected to the NOR circuit 1
9 is connected to the second input terminal.

The output terminal of the NAND circuit 18 is connected to the input terminal of the inverter circuit 20 and the P-channel MOSFET (Me
tal Oxide semiconductor Field Effect Transistor)
Connected to 32 gates. The output terminal of the NOR circuit 19 is the input terminal of the inverter circuit 21 and the NAND circuit 18
Is connected to the second input terminal of.

The output terminal of the inverter circuit 20 is the first input terminal of the exclusive OR circuit 35, and the OR circuit 1
5 is connected to the first input terminal of the AND circuit 16, and the first input terminal of the AND circuit 24. The output terminal of the inverter circuit 21 is connected to the second input terminal of the AND circuit 17.

The terminal 22 to which the reference signal S _REF is supplied is O
It is connected to the first input terminal of the R circuit 25 and the second input terminal of the AND circuit 23. The output terminal of the OR circuit 25 is NAN
The AND circuit 23 is connected to the second input terminal of the D circuit 27.
Is connected to the first input terminal of the NOR circuit 26, and the output terminal of the AND circuit 24 is connected to the second input terminal of the NOR circuit 26.
Connected to the input terminal.

The output terminal of the NAND circuit 27 is connected to the input terminal of the inverter circuit 29. The output terminal of the NOR circuit 26 is connected to the input terminal of the inverter circuit 28 and the first input terminal of the NAND circuit 27.

The output terminal of the inverter circuit 29 is the gate of the N-channel type MOSFET 33, which is exclusive.
It is connected to the second input terminal of the OR circuit 35, the second input terminal of the OR circuit 25, the second input terminal of the AND circuit 24, and the second input terminal of the AND circuit 16. Inverter circuit 28
Is connected to the first input terminal of the AND circuit 23.

The output terminal of the exclusive OR circuit 35 is connected to the terminal 36. Control signal Ph from terminal 36
Is output.

A terminal 31 to which the power supply voltage V _CC is supplied, and M
The charge pump 30 is configured by the OSFET 32 and the MOSFET 33. Terminal 31 is MOSFET3
2 sources. The drain of the MOSFET 32 is connected to the drain of the MOSFET 33. MOSF
The source of ET33 is grounded. And MOSFET
A terminal 34 is connected to a connection node between 32 and the MOSFET 33. The phase error signal Pd is output from the terminal 34.

Next, a time chart of signal waveforms in the phase comparator 6 is shown in FIG. The comparison signal S _COM and the reference signal S _REF are pulse signals whose High level and Low level are inverted every 180 degrees.

For example, when the phase of the comparison signal S _COM is delayed by 135 degrees with respect to the phase of the reference signal S _REF when the power is started, the signal waveform shown in FIG. 4A is obtained. The phase error signal Pd is V _CC (Hi when the reference signal S _REF is at the high level and the comparison signal S _COM is at the low level.
gh level), and is in a high impedance (open drain) state in other periods (dotted line portion). Further, the control signal Ph becomes zero (Low level) when the reference signal S _REF is at High level and the comparison signal S _COM is at Low level, and is V at other periods.
It becomes _CC (High level).

On the other hand, the reference signal S_REFPlace of
Comparison signal S for phase_COMThe phase of was advanced 135 degrees
In this case, the signal waveform shown in FIG. Phase error signal
Pd is the reference signal S_REFIs low level and
Comparison signal S_COMIs High (Low
Level), and high in other periods (dotted line)
It becomes a pedance (open drain) state. In addition,
The control signal Ph is the reference signal S _REFIs low level
Furthermore, the comparison signal S_COMIs high when is high level
(Low level), V during other periods_CC(Hi
gh level).

The phase of the comparison signal S _COM and the reference signal S _COM
When the phases of _REF match, the value of the phase error signal Pd is always V _CC / 2, and the control signal Ph is always V _CC (High
Level).

Next, FIG. 5 shows a configuration example of a low-pass filter for inputting the phase error signal Pd output from the phase comparator 6. The low-pass filter of FIG. 5 is a lag lead low-pass filter, and is composed of a resistor R6, a resistor R7, a capacitor C5, and a capacitor C6.

One end of the resistor R6 is connected to the terminal to which the phase error signal Pd is supplied. The other end of the resistor R6 is connected to one end of the capacitor C5, one end of the capacitor C6, and the control voltage V
Connected to the terminal that outputs _CON . Capacitor C5
The other end of is connected to the ground line via a resistor R7,
The other end of the capacitor C6 is directly connected to the ground line.

When the phase of the comparison signal S _COM is delayed with respect to the phase of the reference signal S _REF at the time of power-on, etc., the low-pass filter 7 holds the high level of the phase error signal Pd to control voltage V _CON. Becomes V _CC . As a result, the oscillation frequency of the crystal voltage controlled oscillator 1 becomes F + ΔF.

Further, when the phase of the comparison signal S _COM is advanced with respect to the phase of the reference signal S _REF when the power source is started,
Low of the phase error signal Pd by the low pass filter 7
The level is held and the value of the control voltage V _CON becomes zero. As a result, the oscillation frequency of the crystal voltage controlled oscillator 1 becomes F-ΔF.

When the phase of the comparison signal S _COM matches the phase of the reference signal S _REF when the power is turned on, the value of the control voltage V _CON output from the low pass filter 7 is V V.
It becomes _CC / 2. As a result, the oscillation frequency of the crystal voltage controlled oscillator 1 becomes F. Note that F is 20 in this embodiment.
[MHz] and ΔF are set to 200 [Hz].

Next, the M phase shift circuit 4 and the selector 5
An example of the configuration will be described with reference to FIG. In this embodiment, a signal of 5 [kHz] is used as the reference signal S _REF .
Then, the division ratio of the 1 / N frequency divider 2 is set to 500, and 1 / M
The frequency division ratio of the frequency divider 3 is set to 8.

The M-phase phase shift circuit 4 is an 8-bit shift register composed of flip-flops 40, 41 and 42 and an inverter circuit 43. The output signal of the 1 / N frequency divider 2 is input to the clock input terminals of the flip-flops 40, 41, 42. As a result, the clock frequency of the flip-flops 40, 41, 42 is 40 [k
Hz] (= 20 [MHz] / 500).

The output side of the 1 / M frequency divider 3 is connected to the data input terminal of the flip-flop 40, the D terminal of the switch 50 and the input side of the inverter circuit 43. The non-inverting output terminal of the flip-flop 40 is connected to the data input terminal of the flip-flop 41 and the C terminal of the switch 50. The non-inverting output terminal of the flip-flop 41 is connected to the data input terminal of the flip-flop 42 and the B terminal of the switch 50. The non-inverting output terminal of the flip-flop 42 is connected to the A terminal of the switch 50.

The output side of the inverter circuit 43 is the switch 5
0 a terminal. Also, the flip-flop 40
The non-inverting output terminal of is connected to the b terminal of the switch 50. Further, the non-inverting output terminal of the flip-flop 41 is connected to the c terminal of the switch 50. Further, the non-inverting output terminal of the flip-flop 42 is connected to the d terminal of the switch 50.

With such a configuration, each of the switches 50
The signal waveform supplied to the terminals is the time chart shown in Fig. 7.
become that way. That is, the M phase shift circuit 4 has 5
Frequency division signal S of [kHz] (= 40 [kHz] / 8)_DIV2
Signal S of 5 [kHz] with a phase difference of 45 degrees from_A~
S_D, S_a~ S_dAnd the signal S of its 8 phases (8 types) _A
~ S_D, S_a~ S_dIs output to the selector 5.

The selector 5 includes a switch 50, a microcomputer (hereinafter referred to as a microcomputer) 51, and a resistor R.
8 and a capacitor C7. The switch 50 selects one terminal from terminals A to d based on the signal from the microcomputer 51 and connects it to the terminal 14 (see FIG. 3) of the phase comparator 6.

Control signal Ph output from the phase comparator 6
Is integrated by an integrating circuit including a resistor R8 and a capacitor C7, and then input to the A / D conversion input terminal of the microcomputer 51. The operation of the microcomputer 51 will be described with reference to the flowchart of FIG.

In step # 10, it is determined whether the integrated value of the control signal Ph is larger than the target voltage V _tg . The target voltage V _tg is expressed by equation (2). In addition,
Since M in the equation (2) is the frequency division ratio of the 1 / M frequency divider 3,
In the case of this embodiment, M = 8. V _tg = (1-1 / M) × V _CC (2)

The integrated value of the control signal Ph is the target voltage V
If it is larger than _tg (Yes in step # 10), the phase difference between the comparison signal S _COM and the reference signal S _REF is within 45 degrees, so that among the eight-phase signals S _{A to} S _D and S _{a to} S _d . Reference signal S
_This means that the signal having the smallest phase difference from _REF is selected as the comparison signal S _COM . Therefore, without switching the terminals connected to the phase comparator 6, the process proceeds to step # 10 in preparation for the case where the lock is released again after the lockup.

On the other hand, if the integrated value of the control signal Ph is not larger than the target voltage V _tg (N in step # 10).
o) Since the phase difference between the comparison signal S _COM and the reference signal S _REF is larger than 45 degrees, the phase difference between the reference signal S _REF is the highest among the eight-phase signals S _{A to} S _D and S _{a to} S _d. This means that the small signal is not selected as the comparison signal S _COM . Therefore, the switch 50 is controlled so as to shift one terminal connected to the phase comparator 6 (step # 20). For example, when the D terminal and the phase shift comparator 6 are connected in step # 10, the switch 50 is controlled so that the a terminal and the phase shift comparator 6 are connected in step # 20. After that, the process shifts to step # 10 and the signal having the smallest phase difference from the reference signal S _REF is selected from among the eight-phase signals S _{A to} S _D and S _{a to} S _d as the comparison signal S _COM . Determine whether or not.

By the microcomputer 51 performing such an operation, the reference signal S is selected from the eight-phase signals S _{A to} S _D and S _{a to} S _d.
The signal having the smallest phase difference from _REF is selected as the comparison signal S _COM . Therefore, the comparison signal S _COM and the reference signal S
_The maximum phase difference from _REF is only 45 degrees.

[0052] Then, the oscillation signal S the frequency difference between the comparison signal S _COM and the reference signal S _REF when the phase of the phase and the reference signal S _REF does not match the _OUT is ΔF / (N × M) [ Hz]
Becomes Therefore, although the comparison signal S _COM is phase-shifted by 360 degrees with respect to the reference signal S _REF , (N × M) / Δ
It takes F [seconds]. Further, in the PLL circuit of this embodiment,
As described above, the maximum phase difference between the comparison signal S _COM and the reference signal S _REF is 45 degrees. Therefore, the PLL of the present embodiment
The maximum lockout time T in the circuit is expressed by equation (3). T = 45/360 × (N × M) / ΔF = 1/8 × (N × M) / ΔF [sec] ... (3)

Here, N = 500, M = 8, ΔF = 20
Since it is 0 [Hz], the maximum lockout time T is 2.
It becomes 5 [seconds]. FIG. 10 under the same conditions (oscillation frequency of crystal voltage controlled oscillator 1 is 20 [MHz], frequency of reference signal S _REF is 5 [kHz], and variable width ΔF of oscillation frequency of crystal voltage controlled oscillator 1 is 200 [Hz]). Since the maximum lockup time of the conventional PLL circuit shown in (1) is 10 seconds, the maximum lockup time can be shortened to 1/4.

Further, the maximum lockup time can be shortened by increasing the number of stages of the phase shift circuit 4.
That is, an arbitrary maximum lockup time can be set by setting the number of phases of the signals generated by the M-phase phase shift circuit 4. For example, add four more flip-flops and set the clock frequency of each flip-flop to 80.
By setting [kHz], the maximum lockup time is 1.
It can be set to 25 [seconds].

Although the microcomputer 51 is used for controlling the switch 50 in this embodiment, a hard logic circuit may be used instead of the microcomputer 51. Further, the 1 / N frequency divider 2 and the 1 / M frequency divider 3 may not be configured by separate frequency dividers, but may be configured by providing taps by one frequency divider. Further, the 1 / M frequency divider 3 may be provided with an inverting output terminal, and the inverting terminal may be connected to the a terminal of the switch 50 so that the inverter circuit 43 is not used. In this configuration, the 1 / M frequency divider 3 is replaced by the M-phase phase shift circuit 4
Will be responsible for some of the functions of.

[0056]

According to the present invention, since the crystal voltage controlled oscillator having the crystal oscillator is provided, the S / N ratio of the output signal is increased.
Can be higher. Further, one signal is selected from a plurality of signals having substantially the same frequency as the reference signal supplied from the outside and having different phases in synchronization with the oscillation signal of the crystal voltage controlled oscillator, and used as a comparison signal. Therefore, the phases of the comparison signal and the reference signal can be reduced. As a result, the maximum lockup time can be shortened. Further, since it is not necessary to provide a plurality of crystal voltage controlled oscillators, the cost can be suppressed.

Further, according to the present invention, since the plurality of signals are signals whose phases are shifted by an interval obtained by dividing one cycle of the reference signal by a predetermined natural number of 2 or more, the plurality of signals include There is a signal whose phase difference from the reference signal is equal to or less than the interval obtained by dividing one cycle of the reference signal by a predetermined natural number of 2 or more. Therefore, the phase difference between the comparison signal and the reference signal can be set to be equal to or less than the interval divided by a predetermined natural number of 2 or more.

Further, according to the present invention, the signal generating means for generating a plurality of signals having substantially the same frequency as the reference signal supplied from the outside and having different phases in synchronization with the oscillation signal of the crystal voltage controlled oscillator. Is a 1 / N frequency divider that divides the oscillation signal of the crystal voltage controlled oscillator by 1 / N;
A 1 / M frequency divider that divides the output signal of the N frequency divider by 1 / M,
Using the output signal of the 1 / M frequency divider as the input signal,
Since the M-bit shift register uses the output signal of the N frequency divider as a clock signal, the signal generating means can be realized with a simple configuration. Thereby, cost reduction can be achieved.

Further, according to the present invention, the signal having the smallest phase difference from the reference signal among the plurality of signals is selected as the comparison signal, so that the maximum lockup time can be further shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a crystal voltage controlled oscillator included in the PLL circuit of FIG.

FIG. 3 is a diagram showing a configuration of a phase comparator included in the PLL circuit of FIG.

4 is a signal waveform time chart in the phase comparator of FIG.

5 is a diagram showing a configuration of a low-pass filter included in the PLL circuit of FIG.

6 is a diagram showing configurations of an M-phase phase shift circuit and a selector included in the PLL circuit of FIG.

FIG. 7 is a time chart of signal waveforms output by the M-phase phase shift circuit shown in FIG.

8 is an operation flowchart of the microcomputer shown in FIG.

FIG. 9 is a diagram showing a configuration of a conventional PLL circuit.

FIG. 10: Conventional PLL with crystal voltage controlled oscillator
It is a figure which shows the structure of a circuit.

FIG. 11 is a diagram showing a configuration of a conventional PLL circuit including a plurality of crystal voltage controlled oscillators.

[Explanation of symbols] 1 Crystal voltage controlled oscillator 2 1 / N divider 3 1 / M frequency divider 4 M phase shift circuit 5 selector 6 Phase comparator 7 Low-pass filter 10 Crystal unit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yutaka Ishimaru             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F-term (reference) 5J079 AA04 BA12 DA13 FA13 FA14                       FA21 FA26 FB03 FB25 FB29                       FB35 FB48 GA09 KA08                 5J106 AA04 CC01 CC21 CC41 CC52                       CC58 DD09 DD26 JJ01 KK03                       KK27 LL01

Claims (4)

[Claims] 1. A crystal voltage controlled oscillator having a crystal oscillator, wherein an oscillation signal of the crystal voltage controlled oscillator is frequency-divided and phase-shifted to have a frequency substantially the same as that of a reference signal supplied from the outside. Signal generating means for generating a plurality of signals each having a different phase in synchronization with the oscillation signal of the crystal voltage controlled oscillator, and selecting one signal from the plurality of signals and outputting the selected signal as a comparison signal. Selecting means, a phase comparator for comparing the phases of the comparison signal and the reference signal and outputting a phase error signal and a control signal according to the phase difference, and a control voltage according to the phase error signal And a filter for performing the selecting operation according to the control signal,
A PLL circuit, wherein the crystal voltage controlled oscillator outputs an oscillation signal according to the control voltage. 2. The PLL circuit according to claim 1, wherein the plurality of signals are signals whose phases are shifted by an interval obtained by dividing one cycle of the reference signal by a predetermined natural number of 2 or more. 3. The signal generating means divides the oscillation signal of the crystal voltage controlled oscillator by 1 / N, and the output signal of the 1 / N divider is divided by 1 / M. And a M-bit shift register that uses the output signal of the 1 / M frequency divider as a data signal and the output signal of the 1 / N frequency divider as a clock signal. PLL described in
circuit. 4. The PLL circuit according to claim 1, wherein the selection means selects a signal having a minimum phase difference from the reference signal from the plurality of signals.