JP4479435B2 - PLL circuit - Google Patents

Description

  The present invention relates to a PLL circuit including a voltage controlled oscillation circuit that changes an oscillation frequency according to an input voltage and a phase locked loop, and more particularly to a PLL circuit that can shorten a lock time until the oscillation frequency is stabilized.

  In recent years, a PLL circuit (phase synchronization circuit) is often used for the purpose of generating a high-speed clock inside a logic LSI in a communication device or adjusting a phase with a RAM module connected outside the LSI.

  FIG. 6 is a block diagram showing a basic configuration of a conventional PLL circuit. This PLL circuit includes a phase comparator (phase comparator: PC) 1, a charge pump circuit (CP) 2, a low-pass filter (LPF) 3, a voltage controlled oscillation circuit (VCO) 4, and a frequency divider circuit (DV) 5. Is done.

  The phase comparator 1 detects the phase difference between the reference signal (reference clock REF_CK) S0 input to one terminal and the comparison signal (divided signal: DIV) S2 fed back to the other terminal, Control signals such as a P gate signal UP and an N gate signal DN are output according to the phase difference. The charge pump circuit 2 charges and discharges the capacitor of the low-pass filter 3 according to whether the pulse signal input thereto is the P gate signal UP or the N gate signal DN. The low-pass filter 3 smoothes the output of the charge pump circuit 2 and outputs a control signal that gives a control voltage to the voltage controlled oscillation circuit 4. The voltage controlled oscillation circuit 4 oscillates at a frequency corresponding to the voltage value of the control signal.

  Here, a frequency-dividing circuit 5 is provided between the output terminal of the voltage-controlled oscillation circuit 4 and the other terminal to which the comparison signal S2 of the phase comparator 1 is input, and a feedback loop is formed. The output signal S1 from the control oscillation circuit 4 is set to a predetermined frequency.

  The PLL circuit having such a configuration is controlled such that the phase and frequency of the reference signal S0 and the comparison signal S2 are the same. Here, an arbitrary positive integer can be selected as the frequency division number N of the frequency divider circuit 5, and at the time of convergence, the output signal S1 is output from the voltage controlled oscillation circuit 4 at a frequency N times the reference signal REF_CK. Is done.

  In such a conventional PLL circuit, the time constant of the low-pass filter 3 is fixed, and if the stability of the frequency is improved at the time of convergence of the voltage controlled oscillation circuit 4, the lock time becomes longer, and conversely the lock time becomes shorter. When set to be, there is a problem that the frequency stability at the time of convergence is lowered. In order to solve such a problem, for example, in the invention of Patent Document 1, a branch circuit for increasing the lock speed provided in the first filter of the loop filter and an analog for connecting or disconnecting the branch circuit are provided. In a phase synchronization circuit (PLL circuit) including a switch circuit, a control signal for switching the analog switch circuit is supplied via a D / A converter.

According to Patent Document 1, an analog switch circuit made of a semiconductor element has a control signal that varies continuously and intermittently at an arbitrary interval within an offset voltage range until it is turned off. To obtain a phase locked loop circuit that is supplied via a / A converter and configured to continuously and intermittently connect and disconnect the branch circuit and satisfy both high-speed lock and stable steady state. it can.
JP 2003-163594 A

  However, in the invention of Patent Document 1, since it is necessary to output a control signal for switching the analog switch circuit from the CPU, software is required, the circuit configuration is complicated, and the cost is increased. there were.

  Also, in a PLL circuit with a simple configuration that does not require a CPU, the PLL circuit is activated to charge / discharge the capacitor of the low-pass filter with a single charge pump circuit, or it is restarted to switch the channel of the radio. After that, there is a problem that the time (lock time) until the oscillation frequency of the output signal of the voltage controlled oscillation circuit is stabilized becomes long.

  Conversely, if the time constant of the low-pass filter between the charge pump circuit and the voltage control oscillation circuit is reduced in an attempt to shorten the lock time in the voltage control oscillation circuit, the voltage pulsation in the capacitor increases, so the voltage control oscillation circuit There has been a problem that the oscillation output frequency becomes unstable.

  The present invention has been made in view of the above points, and converges to a desired frequency in a short time when the frequency is switched, and has a simple configuration that does not require a CPU and is inexpensive. An object of the present invention is to provide a simple PLL circuit.

In the present invention, in order to solve the above problem, a reference clock generation circuit that generates a reference signal having a reference frequency, a voltage-controlled oscillation circuit that generates an output signal having a frequency corresponding to a control voltage, and the voltage-controlled oscillation circuit (the N, 2 or more integer) one output signal N content of a dividing circuit for dividing the, their phase between the output signal of the reference signal and the divided circuit of the reference clock generating circuit In comparison, when the phase of the output signal of the frequency divider circuit is delayed, a first gate signal is generated, and when the phase is advanced, a phase comparator that generates a second gate signal ; A charge pump circuit for generating a control signal for applying the control voltage to the voltage controlled oscillation circuit in response to the first gate signal and the second gate signal; and an output signal from the voltage controlled oscillation circuit. frequency The comparison with the frequency of the reference signal comprises a frequency detection circuit for generating an active signal when the frequency of the output signal is within the predetermined range, by the active signal, the two resistors connected in series resistor And first and second resistor circuits each having a switching transistor connected in parallel to one resistor of the resistor, one end of the first resistor circuit, and one end of the second resistor circuit And a time constant circuit composed of the first resistor circuit and the capacitor, and a time constant circuit composed of the second resistor circuit and the capacitor, each having two large and small time constants. changeably configured, and a low pass filter for removing high frequency components from the control signal generated by the charge pump circuit, said first gate A power supply voltage is supplied from the charge pump circuit to the other end of the first resistance circuit, and when the second gate signal is output, the charge pump circuit supplies the second resistance circuit to the second resistance circuit. The other end of the output signal is grounded to generate the control signal, and when the frequency of the output signal falls within a predetermined range, the frequency of the output signal is in a predetermined range in a direction in which the time constant of the low-pass filter increases. If it is outside, a PLL circuit is provided in which the frequency of the output signal is controlled by switching in a direction in which the time constant of the low-pass filter is reduced.

  According to the present invention, since the frequency detection circuit configured by a simple logic circuit is provided, the frequency of the output signal from the voltage controlled oscillation circuit is within a predetermined range close to the frequency of the reference signal (reference clock). When it is not included, the time constant of the low-pass filter is reduced. Thereby, the lock time can be shortened without the CPU. In addition, by switching the time constant of the low-pass filter so as to increase the time constant when it is within the range, it is possible to improve the frequency stability at the time of convergence.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing a PLL circuit according to the embodiment, and parts corresponding to those of the conventional circuit shown in FIG. 6 are denoted by the same reference numerals.

  In FIG. 1, this PLL circuit is different from the conventional circuit shown in FIG. 6 in that it includes a frequency detection circuit 6 to which a reference signal (reference clock REF_CK) S0 and an output signal S1 of the voltage controlled oscillation circuit 4 are input. It is that you are. The frequency detection circuit 6 compares the frequency of the reference signal S0 with the frequency of the output signal S1 fed back from the voltage controlled oscillation circuit 4, and when the frequency of the output signal S1 falls within a predetermined range, An active signal to the filter 3 is generated. Therefore, if the frequency of the output signal S1 is controlled by switching the direction in which the time constant of the low-pass filter 3 is increased by the active signal output from the frequency detection circuit 6, the frequency stability at the time of convergence can be improved. In addition, when the output frequency of the output signal S1 is switched, it can be converged to a desired frequency in a relatively short time.

FIG. 2 is a circuit diagram showing a detailed configuration of the PLL circuit shown in FIG.
Among these, the phase comparator 1 has its input terminal X1 connected to the external terminal 7 and supplied with a reference signal S0. A reference clock generation circuit (not shown) is connected to the external terminal 7, and a reference signal S0 having a reference frequency is generated here. The input terminal ZRST of the phase comparator 1 is connected to another external terminal 8 from which a reset signal S3 is supplied.

  The output terminals P_GATE and N_GATE of the phase comparator 1 are connected to the charge pump circuit 2, and the P gate signal UP and the N gate signal DN are output to the charge pump circuit 2, respectively. The charge pump circuit 2 includes a P-channel type MOS transistor M41 and an N-channel type MOS transistor M42. A P gate signal UP is supplied to the gate of the MOS transistor M41, and the gate of the MOS transistor M42 is supplied to the gate. Is supplied with an N gate signal DN. The source of the MOS transistor M41 is connected to the power supply terminal 9, from which the power supply voltage Vcc is supplied. Further, the source of the MOS transistor M42 is grounded.

  In the charge pump circuit 2, when the P gate signal UP is input, the MOS transistor M41 is turned on so as to connect the low pass filter 3 to the power supply terminal 9, and the power supply voltage Vcc is supplied. On the contrary, when the N gate signal DN is input, the MOS transistor M42 is turned on and the low pass filter 3 is grounded, so that the capacitors C1 and C2 of the low pass filter 3 can be driven to charge and discharge. The low-pass filter 3 removes high frequency components from the control signal generated by the charge pump circuit 2, and includes a series circuit composed of resistors R1 and R2, a series circuit composed of resistors R3 and R4, and these resistors R2 and R4. Are connected in parallel to the resistor R5 connected to the connection point, the capacitor C1 connected in series with the resistor R5, the capacitor C2 connected in parallel to the series circuit of the resistor R5 and the capacitor C1, and the resistors R1 and R3. Switching transistors M51 and M52.

  The voltage control oscillation circuit 4 has its control signal input terminal VIN connected to the connection point of the resistors R2 and R4 of the low-pass filter 3, its first power supply terminal VCC connected to the power supply terminal 9, and the second power supply terminal VSS connected to the ground. Has been. The output terminal OUT of the voltage controlled oscillation circuit 4 is connected to the external terminal 10 and outputs an output signal S1, and the output signal S1 is also sent from the voltage controlled oscillation circuit 4 to the frequency dividing circuit 5 and the frequency detection circuit 6. I have feedback. Of these, the frequency dividing circuit 5 generates a comparison signal S2 obtained by dividing the output signal S1 supplied to the input terminal IN by 1/16, and the comparison signal S2 is output from the frequency division output terminal div16 to the phase comparator. 1 to the input terminal Y1.

Further, the output signal S1 is fed back to the input terminal vco_ck as it is to the frequency detection circuit 6. The frequency detection circuit 6 includes a reference terminal ref_ck, and a signal from the reference terminal ref_ck to the input terminal vco_ck, that is, a reference signal S0 serving as a reference for comparing the frequency of the output signal S1 is input. The two output terminals lock_on and lock_on_ output lock-on signals S4 and S5 that become active when the frequency of the output signal S1 from the voltage controlled oscillation circuit 4 falls within a predetermined range. These lock-on signals S4 and S5 are generated as their gate signals so that the switching transistors M51 and M52 of the low-pass filter 3 are simultaneously switched from on to off, respectively. by switching the direction in which the constant is increased, it can control the frequency of the output signal S1.

Next, the operation of the PLL circuit shown in FIG. 1 will be described.
The output of the voltage controlled oscillation circuit 4 is frequency-divided by 1/16 by the frequency divider circuit 5 and input to the phase comparator 1. In the voltage controlled oscillation circuit 4, if the phase and frequency of the comparison signal S2 and the reference signal S0 divider 5 for 1 frequency division of the output 16 minutes match, the output signal S1 is the reference signal S0 and the phase The frequency is 16 times that of the reference signal S0. At this time, if the frequency of the comparison signal S2 is close to the reference signal S0, the lock-on signals S4 and S5 from the frequency detection circuit 6 are output at the active level, and the switching transistors M51 and M52 shown in FIG. And the time constant of the low-pass filter 3 is increased to stabilize the output frequency of the voltage controlled oscillation circuit 4.

However, if the frequency of the comparison signal S2 is far from the frequency of the reference signal S0, the lock-on signals S4 and S5 from the frequency detection circuit 6 are output at the inactive level, and the switching transistors M51 and S5 shown in FIG. By turning M52 on, the time constant of the low-pass filter 3 is reduced and the time until locking is shortened. As described above, the PLL circuit shown in FIG. 1 has the effect of reducing the lock time and at the same time increasing the frequency stability at the time of lock.

FIG. 3 is a circuit diagram showing an example of a detailed circuit of the frequency detection circuit 6. FIG. 4 is a timing chart showing the operation of the frequency detection circuit 6 of FIG.
The frequency detection circuit 6 includes a counter circuit 61 that forms a 32 (= 2 ⁵ ) -ary counter by ^five D-type flip-flops FF0 to FF4, and a decoder 62 that includes NOR gates G1 and G2 and a multiplexer circuit MUX1. And a toggle circuit 63 and a latch circuit 64. The toggle circuit 63 is composed of a D-type flip-flop in which an input terminal D and an inverted output #Q are connected, and a reference signal S0 shown in FIG. 4B is input to the clock terminal ck. The toggle signal Stg1 having the timing waveform shown in FIG. The latch circuit 64 includes a multiplexer circuit MUX2, a D-type flip-flop FF5, and an inverter circuit IV.

  In the first-stage D-type flip-flop FF0 of the counter circuit 61, the output signal S1 of the voltage controlled oscillation circuit 4 shown in FIG. 4C is input as a trigger pulse to the clock terminal ck. The bit output Q0 from the first stage of the counter circuit 61 is a trigger (clock) pulse of the D-type flip-flop FF1 of the next stage. Similarly, the bit outputs Q1 to Q3 of the counter circuit 61 are D-type of each stage. The signals are input to the clock terminals ck of the flip-flops FF2 to FF4.

  In the counter circuit 61, the number of pulses of the output signal S1 of the voltage controlled oscillation circuit 4 is counted, and count data composed of the bit outputs Q0 to Q4 is generated as shown in FIG. 4 (d). In FIG. 4D, the count value of the count data is expressed as a hexadecimal number. Since these D-type flip-flops FF0 to FF4 are supplied with the toggle signal Stg1 generated at the half frequency of the reference signal S0 from the toggle circuit 63 to each reset terminal RB, the count is performed every period of the reference signal S0. A period and a reset period are set.

  Based on these bit outputs Q0 to Q4, the decoder 62 determines whether or not the frequency of the output signal S1 is within a predetermined range. That is, the first, second, third and fifth bit outputs Q0, Q1, Q2 and Q4 are input from the counter circuit 61 to the NOR gate G1, and the second, third and third counters of the counter circuit 61 are input to the NOR gate G2. The fifth bit output Q1, Q2, Q4 is input. The fourth bit output Q3 of the counter circuit 61 is supplied as a select signal to the select terminal S of the multiplexer circuit MUX1. If the fourth bit output Q3 (= S) is at the H level, the multiplexer circuit MUX1 outputs the operation result at the NOR gate G2 supplied to the input terminal A, and the fourth bit output Q3 (= S). If L is at L level, the calculation result at the NOR gate G1 supplied to the input terminal B is output. Here, as shown in FIGS. 4D to 4F, the decoder output signal S6 from the decoder 62 is inverted to the H level when the count value is 10, 0F, 0E in hexadecimal notation, By fixing the lock-on signal S4 to the H level, it can be determined that the frequency of the output signal S1 is within a predetermined range.

  In the latch circuit 64, the decoder output signal S6 is supplied to the input terminal A of the multiplexer circuit MUX2, and the inverting output terminal of the D-type flip-flop FF5 is connected to the input terminal B. Toggle signal Stg1 is supplied as a select signal from toggle circuit 63 to select terminal S of multiplexer circuit MUX2, and reference signal S0 shown in FIG. 4B is input to clock terminal ck of D-type flip-flop FF5. Yes.

  In the latch circuit 64, the lock-on signal S4 shown in FIG. 4F is generated from the inverting output terminal of the D-type flip-flop FF5. Further, the lock-on signal S5 obtained by inverting the lock-on signal S4 is generated from the inverter circuit IV. Is output.

  Thus, in the phase comparator 1, when the phase of the comparison signal S2 is advanced by comparing the phases of the reference signal S0 and the comparison signal S2, the N gate signal DN is output to the charge pump circuit 2 as an H level signal. Thus, the MOS transistor M42 is turned on. On the other hand, if the phase of the comparison signal S2 is delayed by comparing the phases of the reference signal S0 and the comparison signal S2, the P gate signal UP is output to the charge pump circuit 2 as the H level signal, and the MOS transistor M41 is turned on. Is done. In other words, this PLL circuit includes a frequency detection circuit 6 together with the phase comparator 1, and when the frequency of the output signal S1 of the voltage controlled oscillation circuit 4 falls within a predetermined range, an active lock-on signal is output from the frequency detection circuit 6. Since S4 and S5 are output, the lock-on signals S4 and S5 can be switched so as to increase the time constant of the low-pass filter 3, so that the frequency and phase of the reference signal S0 and the output signal S1 can be controlled to match. . The high-frequency component is removed from the control signal output from the charge pump circuit 2 by the low-pass filter 3 and is input to the voltage-controlled oscillation circuit 4, so that the voltage-controlled oscillation circuit 4 has a stable frequency according to the input voltage. It oscillates at.

  FIG. 5 is a diagram illustrating time-oscillation frequency characteristics in the PLL circuit of the embodiment. In this figure, the characteristic of the PLL circuit according to the present invention is shown by a solid line. The characteristic A when the time constant of the low-pass filter 3 is high (shown by a broken line in the figure) and the characteristic when the time constant is small. B (indicated by a dotted line in the figure) is also shown.

  In the characteristic A, the oscillation frequency finally converges to the set value of 260 [KHz] after about 7500 [μs] has elapsed. In the characteristic B, when about 2500 [μs] has passed, the value approaches the set value of about 260 [KHz], but after that, vibration continues in the range of ± 5 [KHz]. In contrast to these characteristics A and B, the characteristics of the PLL circuit according to the present invention converge to the set value of 260 [KHz] when about 5500 [μs] has elapsed, and thereafter the range of ± 0.5% is obtained. There is no vibration exceeding.

  In the PLL circuit of the present invention described above, the comparison signal S2 is generated by using the frequency detection circuit 6 that generates the active signals (lock-on signals S4 and S5) when the frequency of the output signal S1 falls within a predetermined range. Is close to the reference signal S0, the lock-on signals S4 and S5 are output at the active level, the switching transistors M51 and M52 are turned off to increase the constant of the low-pass filter 3, and the voltage controlled oscillation circuit 4 The output frequency can be stabilized. At this time, if the frequency detection circuit 6 counts for one cycle of the reference signal S0, the next cycle is a reset period during which counting is not performed. The result of counting the reference signal S0 for one cycle is decoded by the decoder 62, and it is determined whether or not the frequency of the output signal S1 of the voltage controlled oscillation circuit 4 is within a certain range. When the frequency of the output signal S1 falls within a certain range, the decoder output signal S6 becomes active and is latched by the latch circuit 64 to switch and drive the switching transistors M51 and M52 of the low-pass filter 3. is there.

In the frequency detection circuit 6, the counter circuit 61 is a 32 (= 2 ⁵ ) -ary counter composed of five D-type flip-flops FF0 to FF4. However, any m counter circuits (m is 2 or more). (Integer integer) flip-flops. The decoder 62 of the frequency detection circuit 6 is configured to output the lock-on signals S4 and S5 when the count value of the counter circuit 61 coincides with either 0F or 0F ± 1, A lock-on signal may be output when the count value matches n + 1,... N + s (n and s are integers of 2 or more).

It is a block circuit diagram showing a PLL circuit according to an embodiment. FIG. 2 is a circuit diagram showing a detailed configuration of a PLL circuit shown in FIG. 1. It is a circuit diagram which shows an example of the detailed circuit of a frequency detection circuit. FIG. 4 is a timing diagram illustrating an operation of the frequency detection circuit of FIG. 3. It is a figure which shows the time-oscillation frequency characteristic in the PLL circuit of embodiment. It is a block diagram which shows the basic composition of the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Charge pump circuit 3 Low pass filter 4 Voltage control oscillation circuit 5 Frequency dividing circuit 6 Frequency detection circuit 61 Counter circuit 62 Decoder 63 Toggle circuit 64 Latch circuit FF0-FF4 D type flip-flop S0 Reference signal (reference clock REF_CK)
S1 output signal S2 comparison signal S3 reset signal S4, S5 lock-on signal

Claims (4)

A reference clock generation circuit for generating a reference signal having a reference frequency;
A voltage controlled oscillation circuit that generates an output signal having a frequency corresponding to the control voltage;
A frequency dividing circuit that divides the output signal of the voltage controlled oscillation circuit by 1 / N (N is an integer of 2 or more);
By comparing their phase between the output signal of the reference signal and the divided circuit of the reference clock generating circuit, the phase of the output signal of the divider circuit is delayed to generate the first gate signal A phase comparator that generates a second gate signal when advanced ;
A charge pump circuit for generating a control signal for applying the control voltage to the voltage controlled oscillation circuit in response to the first gate signal and the second gate signal from the phase comparator;
A frequency detection circuit that compares the frequency of the output signal from the voltage controlled oscillator circuit with the frequency of the reference signal and generates an active signal when the frequency of the output signal falls within a predetermined range;
First and second resistor circuits each including a resistor including two resistors connected in series by the active signal , and a switching transistor connected in parallel to one of the resistors; A capacitor connected to a connection point between one end of one resistor circuit and one end of the second resistor circuit, and a time constant circuit including the first resistor circuit and the capacitor, and the second resistor circuit; A low-pass filter configured to change a time constant of the time constant circuit composed of the capacitor in two different sizes, a high-frequency component removed from the control signal generated by the charge pump circuit;
A power supply voltage is supplied from the charge pump circuit to the other end of the first resistor circuit when the first gate signal is output, and the charge pump circuit is output when the second gate signal is output. Grounds the other end of the second resistor circuit to generate the control signal, and when the frequency of the output signal falls within a predetermined range, the output of the low-pass filter increases in the direction of increasing the time constant. A PLL circuit, wherein the frequency of the output signal is controlled by switching in a direction in which the time constant of the low-pass filter becomes smaller if the frequency of the signal is outside a predetermined range. 2. The PLL circuit according to claim 1, wherein the frequency detection circuit counts the number of pulses of the output signal of the voltage controlled oscillation circuit and determines the predetermined range based on the count value. . The frequency detection circuit includes a counter circuit having a count value larger than the frequency division number N set in the frequency divider circuit, and a decoder circuit that determines the predetermined range,
  2. The frequency detection circuit according to claim 1, wherein the counter circuit counts the length of the output signal, and outputs the active signal when the count value matches a set value in the decoder circuit. The PLL circuit according to 2. The counter circuit is a counter composed of m D-type flip-flops, and the decoder circuit has a count value of the counter circuit of n + 1,... N + s (m, n, s are all integers of 2 or more). (N + s) ≦ 2 ^m 4. The PLL circuit according to claim 3, wherein the active signal is output when the value coincides with.

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