JP2001127629A - Pll frequency synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a noise component furthermore by adopting the configura tion of a PLL frequency synthesizer circuit that can prevent propagation of jitter in a prescaler output signal and jitter caused by fluctuation in power supply VDD and ground GND to post-stage circuits in addition to prevention of propagation of jitter caused in an output of a frequency divider to a phase comparator. SOLUTION: The PLL frequency synthesizer circuit is provided with a prescaler 5 that frequency-divides a frequency signal outputted from a VCO 4 that frequency-divides a signal outputted from the prescaler 5 and provides an output, a DFF 8 that is triggered at a leading edge of an output signal of the VCO 4, receives an output signal of the prescaler 5 and provides an output, a DFF 7 that is triggered at a leading edge of an output signal of the DFF8, receives an output signal of the frequency divider 6 and provides an output, the phase comparator 1, a charge pump 2 and a loop filter 3 that receive an output signal of the DFF 7 and a comparison frequency signal being a comparison reference, generate an output voltage in response to the phase difference and give the output voltage to the VCO 4 as a control voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable telephone, a PHS
More particularly, the present invention relates to a PLL frequency synthesizer circuit having a configuration capable of reducing spurious (noise components) caused by the propagation of jitter.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional general PLL frequency synthesizer circuit.

As shown in FIG. 3, a conventional general PLL is used.
The frequency synthesizer circuit includes a phase comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator (VCO)
4, a prescaler 5, and a frequency divider 6, and the output of the VCO 4 is an output signal f having a predetermined frequency.
out. In the figure, the comparison frequency signal is, for example, a signal obtained by dividing the output signal of a reference oscillator by a reference frequency divider having a fixed frequency division ratio. This is a reference signal.

In the PLL frequency synthesizer circuit shown in FIG. 3, the output signal fout of the VCO 4 is frequency-divided by the prescaler 5 at a frequency division ratio of 1 / L, and further divided by the frequency divider 6 to 1 / N. Be circulated. Here, L and N are natural numbers. The phase comparator 1 receives the output signal a2 of the frequency divider 6 and the comparison frequency signal b1 as inputs, and outputs a phase difference signal corresponding to the phase difference between them.

FIG. 4 is a timing chart showing the operation of the PLL frequency synthesizer circuit shown in FIG. In the figure, (a) shows the output signals a1, a1 of the prescaler 5,
(B) is an output signal a2 of the frequency divider 6. When the divider 6 is triggered by the output signal of the prescaler 5 and operates,
Due to the circuit delay, the output of the frequency divider 6 changes with a delay of a predetermined time. FIG. 4 (b ′) is an enlarged view of FIG. 4 (b),
The shaded portion indicates jitter generated by inversion of the logical value of the output of the frequency divider 6 and the like. The signal containing this jitter is
When the signal is directly input to the phase comparator 1, the output signal of the phase comparator 1 and the output signal of the charge pump 2 include jitter, and thus a problem occurs in that the output signal of the VCO 4 includes a noise component.

As a conventional PLL frequency synthesizer circuit that solves this problem, there is a PLL frequency synthesizer circuit disclosed in Japanese Patent Application Laid-Open No. 9-167961. The P
FIG. 5 shows the configuration of the LL frequency synthesizer circuit. In the figure, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in the figure, this PLL frequency synthesizer circuit has a configuration shown in FIG. 3 in which a D flip-flop (DFF) 7 and an inverter 9 are added, and the output signal a1 of the prescaler 5 is inverted by the inverter 9. The output signal thus obtained is supplied to the clock input of the DFF 7, and the output signal a 2 of the frequency divider 6 is supplied as the data input of the DFF 7.
As an output signal a3, and is used as one input of the phase comparator 1.

FIG. 6 is a timing chart showing the operation of the PLL frequency synthesizer circuit of FIG. In the figure, (a), (b) and (b ') correspond to FIG.
(A), (b), and (b '), which correspond to the output signal a1 of the prescaler 5, the output signal a2 of the frequency divider 6, and the expanded signal of the output signal a2 of the frequency divider 6, respectively. Is shown. (C) is the output signal a3 of the DFF 7, and (c ') is an enlarged view of (c).

As shown in FIG. 6, the output signal a of the frequency divider 6
2 is taken into the DFF 7 at a timing shifted from the timing at which the jitter occurs, and is output to the phase comparator 1, whereby the jitter given to the phase comparator 1 can be reduced. The noise component included in the output signal of the VCO 4 can be reduced.

[0010]

However, in the conventional PLL frequency synthesizer circuit shown in FIG. 5, the power supply VDD and the ground GND are common to each circuit, and the output signal of the prescaler 5 is inverted. DF signal
Because the clock is input to F7, prescaler 5
Power supply VDD, ground GND due to the occurrence of jitter in the output signal a1, or the operation of the prescaler and the frequency divider.
Jitter occurs on the output signal a3 of the DFF 7 and propagates to the subsequent circuits such as the phase comparator 1 and the charge pump 2, and as a result, spurious (noise component) occurs in the output signal of the VCO 4. There is a problem of doing.

FIG. 7 is a timing chart showing the operation of the PLL frequency synthesizer circuit shown in FIG. 5, and is a diagram for explaining the above problem. In the figure, (a) is the output signal a1 of the prescaler 5, (b) is the output signal a2 of the frequency divider 6, and (c) is the output signal a3 of the DFF 7. The shaded portions in (a), (b) and (c) represent jitter caused by inversion of a logical value or the like.

As shown in FIG. 7, when jitter occurs in the output signal a1 of the prescaler 5, the jitter propagates to the output signal a3 of the DFF 7 clocked by a signal obtained by inverting the output signal a1 of the prescaler 5 by the inverter 9, Jitter propagates to the phase comparator 1 and also to the VCO 4, causing spurious noise.

The present invention has been made in view of the above-mentioned problems of the prior art, and in addition to preventing the propagation of the jitter generated in the frequency divider output to the phase comparator, the present invention has been applied to a post-stage circuit of the jitter of the prescaler output signal. Propagation, power supply VDD, ground GN
An object of the present invention is to provide a PLL frequency synthesizer circuit having a configuration capable of preventing the propagation of jitter caused by the fluctuation of D to a subsequent circuit, thereby enabling a further reduction in spurious (noise components).

[0014]

Means for Solving the Problems The P of the present invention (first invention)
The LL frequency synthesizer circuit generates a signal having a frequency corresponding to the input control voltage, and outputs a voltage-controlled oscillating means; and a prescaler which divides and outputs a frequency signal output from the voltage-controlled oscillating means. A frequency divider that divides and outputs a signal output from the prescaler, and a frequency divider that outputs and outputs the output signal of the prescaler triggered by a rising edge or a falling edge of an output signal of the voltage controlled oscillator. A first D-flip-flop means, and a rising edge or a falling edge of an output signal of the first D-flip-flop means, and fetching an output signal of the frequency dividing means,
A second D flip-flop means for outputting, an output signal of the second D flip-flop means, and a comparison frequency signal serving as a comparison reference, and generating an output voltage corresponding to the phase difference; Phase comparison / control voltage output means for providing an output voltage as the control voltage to the voltage controlled oscillation means.

The PLL frequency synthesizer circuit according to the present invention (second invention) is a PLL frequency synthesizer circuit according to the first invention, wherein the first power supply circuit and the second power supply circuit are independent of each other. Wherein the prescaler and the frequency dividing means are connected to the first power supply circuit, and the first and second D flip-flop means and the phase comparison / control voltage output means are connected to the second power supply circuit. And a power supply circuit.

According to the PLL frequency synthesizer circuit of the present invention (first invention), the jitter generated in the prescaler output signal due to the inversion of the logical value or the like can be eliminated or reduced by the first D flip-flop means. As a result, it is possible to reduce the spurious generated by the propagation of the jitter to the subsequent circuit.

Further, according to the PLL frequency synthesizer circuit of the present invention (second invention), it is possible to prevent the jitter caused by the fluctuations of the power supply VDD and the ground GND caused by the operation of the prescaler and the frequency divider from propagating to the subsequent circuit. It is possible,
Thereby, spurs can be further reduced.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a block diagram showing the configuration of a PLL frequency synthesizer circuit according to one embodiment of the present invention. The same components as those shown in FIGS. 3 and 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the drawing, the PLL frequency synthesizer circuit of the present embodiment has a DF instead of an inverter 9 in the conventional PLL frequency synthesizer circuit shown in FIG.
F8, and the output signal of the VCO 4 is
8 and the output signal a1 of the prescaler 5
Is applied to the data input of the DFF 8 and the output signal a
4 is applied to the clock input of the DFF 7. Then, an output signal a2 of the frequency divider 6 is given as a data input of the DFF 7 and output as an output signal a3 of the DFF 7, and is used as one input of the phase comparator 1.

Also, two independent power supply circuits, that is, a first power supply circuit for supplying a first power supply VDD and a first ground GND, and a second power supply VDD and a second power supply circuit
A pre-scaler 5 and a frequency divider 6 are connected to the first power supply circuit, and the DFFs 7 and 8 and the phase comparator 1 are connected to the second power supply circuit. As a configuration for connecting to the supply circuit, the prescaler 5 and the frequency divider 6, and the power supply VDD and the ground GND of the DFFs 7 and 8 and the phase comparator 1 are mutually independent.

In FIG. 1, the VCO 4 and the charge pump 2 are each connected to a single power supply (VCO power supply and charge pump power supply). The loop filter 3 receives the output of the charge pump 2 and is composed of a capacitor, a resistor, and the like.
It is not directly connected to the power supply voltage.

According to the PLL frequency synthesizer circuit of the present embodiment, the DFF 8 takes in the output signal a1 of the prescaler 5 in synchronization with the rise of the output signal of the VCO 4, and outputs it as the output signal a4. The signal a4 is a DFF
7, the DFF 7 captures the output signal a2 of the frequency divider 6 in synchronization with the rising of the clock signal a4, and outputs the output signal a3 as the phase comparator 1
Output to

In the present embodiment, the DFFs 7 and 8 are configured to take in input data at the time of rising of the input clock signal. However, one or both of the DFFs are input. It is also possible to use a DFF configured to take in data at the falling edge of the clock signal.

FIG. 2 is a timing chart showing the operation of the PLL frequency synthesizer circuit of the present embodiment.

In the figure, (a) is the output signal of the VCO 4 and (b) is the output signal a1, (c) of the prescaler 5.
Is an output signal a4 of the DFF 8, (b ') is an enlarged view of (b), (c') is an enlarged view of (c), and (c '') is (c)
(D) is an output signal a2 of the frequency divider 6, and
(E) is the output signal a3 of the DFF7.

Due to the delay of the output signal a1 caused by the circuit delay in the prescaler 5, the DFF 8 takes in the output signal a1 of the prescaler 5 with one cycle delay of the VCO output signal and outputs it as an output signal a4. For this reason, D
The jitter generated in the output signal of the prescaler 5 is not propagated to the output signal a4 of the FF 8, and the prescaler output signal from which the jitter has been removed is input to the DFF 7 as a clock signal. Further, due to the delay of the output signal a2 caused by the circuit delay in the frequency divider 6, the DFF 7 captures the output signal a2 of the frequency divider 6 with a delay of one cycle of the output signal a4 of the DFF 8, and as the output signal a3. Output. For this reason,
The jitter generated in the frequency divider output signal a2 is not propagated to the output signal a3 of the DFF 7, and the signal from which the jitter has been removed is input to the phase comparator 1. As a result, the spurious generated in the VCO output signal can be reduced.

Since the power supplies of the prescaler 5 and the frequency divider 6 and the power supplies of the DFFs 7, 8 and the phase comparator 1 are independent of each other, the power supply VDD and the ground GND are generated by the operation of the prescaler and the like. It is also possible to prevent the propagation of the jitter due to the fluctuation to the subsequent circuit, and to further reduce the spurious.

[0029]

As described above in detail, according to the PLL frequency synthesizer circuit of the present invention (the first invention), the jitter generated in the prescaler output signal due to the inversion of the logical value or the like can be reduced by the first D flip-flop. This can eliminate or reduce the spurious components in the VCO output signal due to the propagation of the jitter to the subsequent circuit.

Further, according to the PLL frequency synthesizer circuit of the present invention (second invention), it is possible to prevent the jitter caused by the fluctuation of the power supply VDD and the ground GND caused by the operation of the prescaler and the frequency divider from propagating to the subsequent circuit. It is possible,
Thereby, spurs can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL frequency synthesizer circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional general PLL frequency synthesizer circuit.

FIG. 4 is a timing chart showing the operation of the conventional general PLL frequency synthesizer circuit shown in FIG.

5 is a block diagram showing a configuration of a conventional PLL frequency synthesizer circuit that solves the problem of the conventional general PLL frequency synthesizer circuit shown in FIG.

6 is a timing chart showing the operation of the conventional PLL frequency synthesizer circuit shown in FIG.

FIG. 7 is a timing chart for explaining a problem of the conventional PLL frequency synthesizer circuit shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 phase comparator 2 charge pump 3 loop filter 4 VCO 5 prescaler 6 frequency divider 7 DFF 8 DFF

Claims (2)

[Claims] 1. A voltage controlled oscillating means for generating and outputting a signal having a frequency corresponding to an input control voltage; a prescaler for dividing a frequency signal output from the voltage controlled oscillating means and outputting the frequency signal; Frequency dividing means for dividing and outputting the signal output from the prescaler; and a rising edge or a falling edge of an output signal of the voltage controlled oscillation means, for capturing and outputting the prescaler output signal. A first D-flip-flop means, and a second D-flip-flop for receiving and outputting an output signal of the frequency dividing means, triggered by a rising edge or a falling edge of an output signal of the first D-flip-flop means. Means, an output signal of the second D flip-flop means and a comparison frequency signal serving as a comparison reference, PLL frequency synthesizer circuit, characterized in that to produce an output voltage, and a phase comparator and control voltage output means for applying to said voltage controlled oscillator means output voltage as the control voltage corresponding to the phase difference. , 2. The PLL frequency synthesizer circuit according to claim 1, further comprising a first power supply circuit and a second power supply circuit which are independent of each other, wherein said prescaler and frequency dividing means include: The first power supply circuit is connected to the first and second D flip-flops, and the phase comparison / control voltage output means is connected to the second power supply circuit. PLL frequency synthesizer circuit.