JP2001177404A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a highly precise frequency synthesizer at a low cost. SOLUTION: A phase comparator circuit 10 compares a phase of a reference clock signal Kr with a phase of a comparison clock signal Kv and produces an up-pulse U or a down-pulse D. A charge pump circuit 12 generates an error voltage in response to the up-pulse U or the down-pulse D, a control signal generating circuit 14 generates a control voltage Vc1 in response to the error voltage, and a multi-phase clock variable oscillator 16 oscillates a frequency signal in response to the control voltage Vc1 and provides outputs of polyphase clock signals K0-K7 in response to timing resulting from dividing equally the oscillated frequency. A main phase selection circuit 18 selects two clocks KA, KB among the polyphase clock signals K0-K7 in response to a phase selection signal S1, a sub-phase selection circuit 20 selects either of the clock signals KA, KB in response to a phase selection signal S2 and gives the selected signal to the phase comparator circuit 10 as the comparator clock signal Kv. A control logic circuit 22 outputs the phase selection signals S1, S2 with contents in response to frequency setting data DF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high precision (ex.
And a frequency synthesizer that outputs a clock signal.

[0002]

2. Description of the Related Art FIG. 11 is a schematic block diagram of a conventional example of a frequency synthesizer. The frequency dividing circuit 110 divides the frequency of the reference clock signal Kr having the frequency fr by a fixed frequency dividing number Nr, and uses the frequency division result as a reference signal R as the phase comparison circuit 1.
12 The control signal generation circuit 116 supplies a drive control signal to the voltage control oscillator 118, and the voltage control oscillator 118 oscillates at a frequency fv according to the drive control signal. The output signal Kv having the frequency fv is output to the outside and also applied to the variable frequency dividing circuit 220. The variable frequency dividing circuit 220 converts the output of the voltage controlled oscillator 118 into the frequency dividing number N.
The frequency is divided by v, and the frequency division result is supplied to the phase comparison circuit 112 as a comparison signal V. The frequency division number Nv can be freely changed by the frequency division number setting data DF. Phase comparison circuit 112
Supplies an up pulse U (or down pulse D) to the charge pump circuit 114 when the comparison signal V is delayed (or advanced) from the reference signal R. Charge pump circuit 1
14 generates an error voltage from the up pulse U or the down pulse D and supplies it to the control signal generation circuit 116. The control signal generation circuit 116 generates a drive control signal such that the comparison signal V is in phase with the reference signal R in accordance with the error voltage from the charge pump circuit 114 and supplies the drive control signal to the voltage control oscillator 118.

In the conventional example shown in FIG. 11, the following relationship is established. That is, fv = (Nv / Nr) × fr (1) In this way, the frequency synthesizer shown in FIG. 11 outputs the clock signal Kv having the frequency fv obtained by multiplying the reference clock frequency fr by the coefficient.

A frequency synthesizer is defined by a frequency variable range and frequency setting accuracy. For example, frequency variable range: ± 1500 ppm or more, frequency setting accuracy: 15 pp
m. In this case, 1/2 ＾ 16 = 1/65536 = 15.25 ppm 65536 / (65536-128) = + 1953 pp
m (65536-256) / (65536-128) =-
Since it is 1957 ppm, the variable frequency dividing circuit 220 can be designed as follows as an example. That is, the number of counter bits: 16 bits, the division number setting data DF: 8 bits, the division number range: 65280 to 65408 to 65536.

[0005]

The conventional frequency synthesizer has the following problems. That is, it is necessary to increase the frequency dividing number Nv of the variable frequency dividing circuit in order to increase the frequency setting accuracy. This means that the frequency check interval of the output signal Kv increases, and the voltage-controlled oscillator 118
Needs to have a configuration capable of stably maintaining the oscillation frequency for tens of thousands of clocks as in this case. The voltage-controlled oscillator 118 that can maintain the frequency stability over tens of thousands of clocks cannot be easily realized only by a general-purpose LSI process, and therefore cannot be implemented at low cost.

In order to stably maintain the oscillation frequency, it is necessary to stabilize the output of the voltage controlled oscillator 118 not only by the voltage controlled oscillator 118 but also by the charge pump circuit 114 using a large-capacity capacitor which cannot be realized by the LSI. There is. However, this sacrifices the attack / recovery capability, does not allow rapid output frequency switching, and limits the scope of application.

An object of the present invention is to provide a frequency synthesizer that solves such a problem.

[0008]

A frequency synthesizer according to the present invention is a frequency synthesizer for generating an output signal having a frequency obtained by multiplying the frequency of a reference clock signal by a coefficient, wherein the frequency of the output signal is substantially equally divided. A variable oscillation circuit that generates a clock signal group having a phase difference, a control circuit that generates a phase selection control signal according to frequency setting data,
A phase selection circuit that selects one clock signal from the group of clock signals according to the phase selection control signal and outputs the selected clock signal as a comparison clock signal, a phase comparison circuit that compares the phases of the reference clock signal and the comparison clock signal, A frequency control circuit for controlling an oscillation frequency of the variable oscillation circuit according to an output of the phase comparison circuit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. The reference clock signal Kr is input to a phase comparison circuit 10 that generates a general up pulse U and down pulse D. Of course, the reference clock signal Kr is
The original clock signal may be divided or multiplied for convenience. The phase comparison circuit 10 compares phases between a reference clock signal Kr and a comparison signal Kv described later, and outputs an up pulse U or a down pulse D according to the phase relationship. The output pulse of the phase comparison circuit 10 is also input to a general charge pump circuit 12, and the charge pump circuit 12 generates an error voltage corresponding to the up pulse U and the down pulse D from the phase comparison circuit 10, It is supplied to the control signal generation circuit 14. The control signal generation circuit 14 controls the control voltage Vc according to the error voltage from the charge pump circuit 12.
1 is supplied to the multi-phase clock variable oscillator 16.
Details of the multi-phase clock variable oscillator 16 will be described later. The phase comparison circuit 10, the charge pump circuit 12, and the control signal generation circuit 14 have a general performance.

The multi-phase clock variable oscillator 16 oscillates at a frequency corresponding to the control voltage Vc 1 and outputs to the main phase selection circuit 18 multi-phase clock signals K 0 to K 7 at a timing obtained by dividing the oscillation frequency by eight. Multi-phase clock variable oscillator 1
The sixth clock signal K7 is output to the outside as the output signal CK of the present embodiment.

The main phase selection circuit 18 includes a control logic circuit 22
Multi-phase clock signal K0 according to phase selection signal S1 from
~ K7 to select two main selection clocks KA and KB,
Output to the sub phase selection circuit 20. Sub phase selection circuit 20
Selects one of the main selection clock signals KA and KB according to the phase selection signal S2 from the control logic circuit 22 and supplies it to the phase comparison circuit 10 as the above-mentioned comparison signal Kv. Supply as
The frequency setting data DF is input to the control logic circuit 22, and the control logic circuit 22 uses the phase selection signals S 1 and S 2 according to the frequency setting data DF to generate the main phase selection circuit 1.
8 and the sub-phase selection circuit 20 are controlled.

FIG. 2 is a block diagram showing a schematic configuration of the multi-phase clock variable oscillator 16. Differential delay circuits 30, 32, 34, and 36 having the same configuration are connected in a ring shape. However, the output differential signal of the differential delay circuit 36 is connected to the input of the differential delay circuit 30 with the positive electrode / negative electrode being different from each other. Thus, an oscillation circuit is formed.

FIG. 3 shows an example of a CMOS circuit configuration of the differential delay circuits 30 to 36. The drive voltage Vd is applied to the gates of the field effect transistors (FETs) 50 and 52. FET
52, the drain current I1 is equal to the F
Supplied from ETs 54 and 46. A positive signal Pi is applied to the gate of the FET 54, and a negative signal Ni is input to the gate of the FET 56. The drain of the FET 50 is connected to the drains of the FETs 58 and 60 whose gate and drain are short-circuited and the gate of the FET 62. FET60,6
2 outputs a current I2. The drains of the FETs 60 and 62 are connected to the drains of the FETs 54 and 56, respectively. The drains of the FETs 60 and 62 are also connected to the sources of the FETs 64 and 66 whose gate and drain are short-circuited.
It outputs a positive signal Po and a negative signal No.

If I2 = I1 / 2, Po and N
In each transition period of o, charging and discharging are performed by the current I2. Since the current I2 is determined by the drive voltage Vd,
Thereby, the input / output delay time can be controlled. Therefore, the delay time of each of the differential delay circuits 30 to 34 is equal to 1 of the oscillation cycle Tv.
/ 8. The oscillation frequency fv can be controlled by setting the control voltage Vc1 to each control voltage Vd of the differential delay circuits 30 to 36.

The differential output signals of the differential delay circuits 30 to 36 are respectively 1/8 through differential buffers 38 to 44.
The signals are output as multi-phase clock signals K0 to K7 having different phases for each cycle.

The variable oscillator 16 having the configuration shown in FIG.
It can be easily formed in an LSI by the OS process.

The operation of the main phase selection circuit 18 will be described. The main phase selection circuit 18 can take eight states according to the phase selection signal S1. FIG. 4 shows the output signal K in each state.
The correspondence table of A and KB is shown. Here, the signals KA and KB
Is a differential clock signal. Characteristically, both signals KA and KB have two state numbers, and the output clock does not change. In addition, the states are sequentially transitioned by the phase selection signal S1, such as state 0 → state 7, state 0 → state 7, state 0 ← state 7, and state 0 ← state 7.

The configuration and operation of the sub phase selection circuit 20 will be described. FIG. 5 is a schematic block diagram of the configuration of the sub-phase selection circuit 20. The differential clock signals KA and KB from the main phase selection circuit 18 are input to the selection circuits 70a to 70h. The phase selection signal S2 from the control logic circuit 22 includes 1-bit signals S2a to S2h. Each of the selection circuits 70a to 70
h selects the clock KA when the signals S2a to S2h are at the L level, and selects the clock KB when the signals S2a to S2h are at the H level. Outputs of the selection circuits 70a to 70h are input to differential delay circuits 72a to 72h, respectively. Differential delay circuit 7
2a to 72h have the same configuration as the configuration shown in FIG. 3, for example. The control voltage Vd may be the same voltage as the control voltage Vc1 applied to the variable oscillator 16. This eliminates the need to provide a new control circuit.

The differential output terminals of the differential delay circuits 72a to 72h are connected to each other, and the differential buffer 74 outputs the common connection output as a comparison clock signal Kv. The comparison clock signal Kv has ten states A to E and a to e as shown in FIGS. 6A and 6B, and one of the states is one of the phase selection signals S2a to S2S.
2h. FIG. 6A shows the clock KB.
FIG. 6 shows a state where the clock is behind the clock KA.
(B) shows a state where the clock KB is ahead of the clock KA.

FIG. 7A shows differential delay circuits 72a-72.
7 shows one differential signal waveform at the output connection point of h. State A
Or, a is the state with the most advanced phase, and charges and discharges with a current of 8 × I2 in the transition region (periods t0 to t2 and periods t4 to t6). Since the parasitic capacitance is also approximately eight times, the rising and falling speeds of the voltage are almost equal to those of the output signal of the differential delay circuit in the variable oscillator 16, and the transition time is about １ ／ of the clock cycle Tv. In state B or b, period t
The charge / discharge current is (7-1) × I at 0 to t1 and t4 to t5.
2 = 6 × I2, and thereafter, the charge / discharge current exceeds 8 × I2 until the voltage transition exceeds the threshold voltage Vth and the voltage transition ends.
It is.

In state C or c, periods t0 to t1 and t
From 4 to t5, the charge / discharge current is (6-2) × I2 = 4 × I2, and thereafter, the charge / discharge current is 8 × I2 until the voltage transition exceeds the threshold voltage Vth. State D
In the case of d, the charge / discharge current is (5-3) × I2 = 2 × I2 in the periods t0 to t1 and t4 to t5, and thereafter, the charge / discharge current exceeds the threshold voltage Vth until the voltage transition is completed. The discharge current is 8 × I2. State E or e is the state with the most delayed phase, and charges and discharges the transition regions (periods t1 to t3 and periods t5 to t7) with a current of 8 × I2, and the states A and a
, The phase is delayed by 1/8 Tv.

By the above operation, the charge / discharge waveform in the transition region of each state is as shown in FIG. 7A, and the states A (a) to E (e) have a phase shift of 1 / 32Tv each. And outputs a clock signal having the same phase.

FIG. 7B shows differential delay circuits 72a-72.
The operation waveforms in each state when the parasitic capacitance at the output connection point of h is relatively larger than the variable oscillator 16 by about 50% on the layout are shown. Even in such a case, the operation of equally dividing the phase is satisfied, and it can be seen that the operation described above is surely realized. It is difficult to operate the differential delay circuit with a delay time of 0.5 ns or less stably, and if the clock frequency exceeds 200 MHz, the variable oscillator 16 that outputs a multiphase clock signal exceeding 8 cannot be realized.

The variable oscillator 1 is controlled by the sub-phase selection circuit 20.
6 can be easily realized by logical interpolation processing.

Next, the prescaler operation will be described. First, the specifications of the frequency synthesizer are set as follows, as in the conventional example. That is, the frequency variable range is ± 150
0 ppm or more, and the frequency setting accuracy is about 15 ppm.

The control logic circuit 22 includes a variable frequency dividing circuit that counts the comparison clock signal Kv by n or n−1 (where n = 512) and divides the operation cycle into 128 periods. In the present embodiment, the prescaler operation is performed in cooperation with the main phase selection circuit 18, the sub phase selection circuit 20, and the control logic circuit 22. The prescaler operation of this embodiment will be described with reference to FIGS.

1) When fv = fr In this case, the frequency setting data DF is set to 00h. The control logic circuit 22 forcibly fixes the phase selection signals S1 and S2. Thereby, the comparison clock signal Kv has a constant phase, and the circuit shown in FIG. 1 operates as a simple PLL circuit that outputs a clock frequency fv equal to the reference clock frequency fr.

2) When fv = fr + Δf (however,
Δf is the minimum frequency shift. In this case, the frequency setting data DF is set to 81h. As shown in FIG. 8, the control logic circuit 22 includes the main phase selection circuit 18
N count operation is performed by the
Times and n-1 count operations are performed 15 times, and states 1 to 7
Then, only the n-count operation is performed 16 times. The carry signal C of the variable frequency divider determines the phase selection signals S1 and S2.

FIG. 9 shows the operation when fv> fr.
Things. FIG. 9A shows an operation state of the main phase selection circuit 18 and the sub phase selection circuit 20, and FIG. 9B shows a phase change of the comparison clock signal Kv. Main phase selection circuit 1
8 starts in the state 0 and the sub-phase selection circuit 20 starts in the state e. When the carry signal C is generated four times (one n-1 count operation and three n count operations), the phase selection is started. The sub phase selection circuit 20 is set to the state B by the signal S2. At this time, the phase of the comparison clock signal Kv is delayed by 360 degrees / 32. Next, when the carry signal C is generated four times (n count operations are performed four times), the phase selection signal S2 sets the sub-phase selection circuit 20 to the state C. At this time, the phase of the comparison clock signal Kv is further delayed by 360 degrees / 32. When these operations are repeated two more times, the sub-phase selection circuit 20
Becomes state E, and the phase of the comparison clock signal Kv is delayed by 45 degrees from the beginning. At this time, the main phase selection circuit 18
Changes to state 1 by the phase selection signal S1, and the clock KA changes from K0 to K2. The sub phase selection circuit 20 is in the state E, and the output phase of the clock Kv is not affected by the phase change of the clock KA. In addition, when the state change of the main phase selection circuit 18 is performed within the 511 (512) clock period, it does not affect the prescaler operation.

Next, when the carry signal C is generated four times (n count operations are performed four times), the sub-phase selection circuit 20 enters the state b by the phase selection signal S2, and the comparison clock signal K
The phase of v is delayed by 360 degrees / 32. When this operation is repeated three more times, the sub-phase selection circuit 4 enters the state e. At this time, the main phase selection circuit 18 changes to the state 2 by the phase selection signal S1, and the clock KB changes from K1 to K3. The sub-phase selection circuit 20 is in the state e, and the output phase of the comparison clock signal Kv is not affected by the phase change of the clock KB. Thereafter, by repeating this operation, 65535 clock cycles (n × 127 + (n−1))
× 1), the phase of the comparison clock signal Kv is delayed by 360 degrees. This is because the phases of the output signals K0 to K7 of the variable oscillator 16 are different from the reference clock signal Kr by 36 in this period.
Means to advance 0 degrees.

Equivalently, the output frequency fv becomes higher than the reference frequency fr as shown by the following equation. That is, fv = fr + (1/65535) fr = fr + Δf Therefore, the minimum frequency shift Δf is about 15 ppm of the reference clock frequency fr which is a desired value.

In this embodiment, the comparison clock signal Kv is 3
Since the phase jump is performed by 60 degrees / 32, jitter of the output signal of the variable oscillator 16 is concerned. However, since the phase jump is corrected to a continuous one by the capacitance element in the charge pump circuit 12, the jitter amount is suppressed to 1/100 cycle or less, which is practically no problem in a normal charge pump circuit. In the sub-phase selection circuit 20, the interpolation amount is reduced to 1/4 for the sake of simplicity, but the configuration for reducing the interpolation amount to about 1/8 is easy. In this case, the jitter amount can be further suppressed.

3) When fv = fr + k × △ f In this case, the frequency setting data DF is 256-k.
The phase delay operation of the comparison clock signal Kv by the main phase selection circuit 18, the sub phase selection circuit 20, and the control logic circuit 22 is as shown in FIG. 9 as in the case described above. The only difference is that k (n-1) counting operations of the variable frequency dividing circuit in the control logic circuit 22 are allocated to 128 carry generation periods. However, (n-1)
When the count operation periods are allocated as evenly as possible, the phase transition characteristic of the comparison clock signal Kv becomes linear, and the frequency stability of the output CK can be optimized. The operation cycle is (65
536−k) × Tv, so the output frequency is set in this operation cycle. The output frequency fv becomes the maximum output frequency when the frequency setting data DF is FFh, as shown by the following equation: fv = (65536) / (65536-k) × fr ≒ fr + k × △ f That is, fv (max) = 65536 / (65536-127) fr ≒ fr + 127 × △ f At this time, the frequency shift with respect to the reference clock frequency fr is about 1900 ppm, which satisfies the above condition.

4) When fv = fr- △ f In this case, the frequency setting data DF is set to 01h. The control logic circuit 22 includes, as shown in FIG.
Only when the state 8 is in the state 0, the variable frequency dividing circuit performs the n count operation once and the n-1 count operation 15 times.
In step 7, only the n-count operation is performed 16 times. The phase selection signals S1 and S2 are determined by the carry signal C of the variable frequency dividing circuit.

FIG. 10 shows the operation when fv> fr. FIG. 10A shows the operation states of the main phase selection circuit 18 and the sub phase selection circuit 20, and FIG. 10B shows the phase change of the comparison clock signal Kv. Main phase selection circuit 18
Is in state 0 and the sub-phase selection circuit 20 is in state a, and when the carry signal C is generated four times (one n-1 count operation and three n count operations), the phase selection is performed. The signal S2 causes the sub-phase selection circuit 20 to enter the state D. At this time, the phase of the comparison clock signal Kv advances by 360 degrees / 32.

Next, when the carry signal C is generated four times (n count operations are performed four times), the sub phase selection circuit 20 changes to the state C from the phase selection signal S2. The phase of the comparison clock signal Kv further advances by 360 degrees / 32. When this operation is repeated two more times, the sub-phase selection circuit 20 enters the state A,
The phase of the comparison clock signal Kv advances from the beginning by 45 degrees. At this time, the main phase selection circuit 18 further transitions to state 7 by the phase selection signal S2, and the clock KB changes from K1 to K7.
Changes to The sub-phase selection circuit 20 is in the state A, and the phase of the comparison clock signal Kv is not affected by any phase change of the clock KB. Moreover, the main phase selection circuit 18
Does not affect the prescaler operation if performed within the 511 (512) clock period.

Next, when the carry signal C is generated four times (n count operations are performed four times), the sub-phase selection circuit 20 enters the state d by the phase selection signal S2, and the comparison clock signal K
The phase of v advances by 360 degrees / 32. When this operation is repeated three more times, the sub-phase selection circuit 20 enters the state a. The phase selection signal S1 causes the main phase selection circuit 18 to transition to state 6, and the clock KA changes from K0 to K6. At this time,
The sub-phase selection circuit 4 is in the state a, and the output phase of the comparison clock signal Kv is not affected by any phase change of the clock KA. Thereafter, by repeating this operation,
65535 clock cycles (n × 127 + (n−1) ×
In 1), the phase of the comparison clock signal Kv advances by 360 degrees.
This is because the phases of the output signals K0 to K7 of the variable oscillator 16 become 360 degrees in this period with respect to the reference clock signal kr.
Degree means delay.

The output frequency fv is equivalent to the reference frequency f
r becomes lower as shown by the following equation. That is, fv = fr- (1/65535) fr = fr-Δf Therefore, the minimum frequency shift Δf is about 15 ppm of the reference clock frequency fr which is a desired value.

5) When fv = fr-k × △ f In this case, the frequency setting data DF is set to 256-k.
The phase delay operation of the comparison clock signal Kv by the main phase selection circuit 18, the sub phase selection circuit 20, and the control logic circuit 22 is as shown in FIG. The only difference is that k (n-1) counting operations of the variable frequency dividing circuit in the control logic circuit 22 are allocated to 128 carry generation periods. However, when the (n-1) count operation periods are allocated as evenly as possible, the phase transition characteristic of the comparison clock signal Kv becomes linear, and the frequency stability of the output signal CK can be optimized. Since the operation cycle is (65536-k) × Tv, the output frequency is set in this operation cycle. The output frequency fv is given by fv = (65536-k) / (65536) × fr ≒ fr-k × △ f, as shown by the following equation. When the frequency setting data DF is FFh, the minimum output frequency is obtained, and fv (min) = (65536-127) / (65536) × frｆfr-127 × △ f. At this time, the frequency shift with respect to the reference clock frequency fr is about 1900 ppm, which satisfies the above condition.

In this embodiment, since the phase comparison operation for determining the target output frequency can be performed for each output signal period, the phase comparison operation of the charge pump circuit 12, the variable oscillator 16, and the like is performed.
A general PLL configuration circuit can be used as it is for the LL configuration circuit block.

In this embodiment, the sub-phase selection circuit 20 is provided for the purpose of improving the prescaler operation. However, it is obvious that the prescaler operation can be realized without this. If the sub-phase selection circuit 20 is not provided, it is necessary to suppress the jump of the control phase by increasing the capacitance value in the charge pump circuit 12, for example.

The variable oscillator 16 directly generates the multi-phase clock, but supplies the output of the single-phase output variable oscillation circuit 17 to a delay chain circuit in which delay circuits are cascaded.
A similar multi-phase clock signal may be generated.

In this embodiment, the comparison clock signal Kv is input to the control logic circuit 22 for generating the phase selection signals S1 and S2. However, since the timing restrictions are small for the phase selection signals S1 and S2, the clocks K0 to K0 are used. K7, KA, and KB may be input to the control logic circuit 22.

[0045]

As can be easily understood from the above description, according to the present invention, the phase comparison operation for controlling the target output signal frequency can be performed for each cycle of the output signal.
Moreover, since this phase comparison operation is not related to the target frequency setting accuracy, a high-precision frequency synthesizer can be easily realized using a general PLL variable oscillation circuit and a charge pump circuit, and an LSI can be realized. It can be realized at low cost. Since the attack / recovery ability in the frequency control operation is not impaired for the improvement of the frequency setting accuracy,
Fast output frequency switching becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of a variable oscillator 16;

FIG. 3 is a schematic configuration block diagram of differential delay circuits 30 to 36.

FIG. 4 is an operation correspondence table of the main phase selection circuit 18.

FIG. 5 is a schematic configuration block diagram of a sub-phase selection circuit 20;

FIG. 6 is an operation correspondence table of the sub-phase selection circuit 20;

FIG. 7 is a waveform diagram of the sub-phase selection circuit 20.

FIG. 8 is an explanatory table of a prescaler operation according to the present embodiment.

FIG. 9 is a diagram illustrating a first state in a prescaler operation according to the present embodiment.

FIG. 10 shows a second example of the prescaler operation of the present embodiment.
It is a figure showing a state.

FIG. 11 is a schematic block diagram of a conventional example.

[Description of Signs] 10: Phase comparison circuit 12: Charge pump circuit 14: Control signal generation circuit 16: Multi-phase clock variable oscillator 18: Main phase selection circuit 20: Sub-phase selection circuit 22: Control logic circuit 30, 32, 34 , 36: differential delay circuit 38, 40, 42, 44: differential buffer 50, 52, 54, 56, 58, 60, 62, 64, 6
6: Field-effect transistors 70a to 70h: selection circuits 72a to 72h: differential delay circuit 74: differential buffer 110: frequency divider circuit 112: phase comparison circuit 114: charge pump circuit 116: control signal generation circuit 118: voltage controlled oscillator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J043 AA22 AA26 LL01 5J106 AA04 CC01 CC24 CC38 CC41 DD09 DD32 FF08 GG08 GG20 HH02 JJ01 JJ05 KK03 KK05 KK37 PP03 QQ01 QQ06 QQ09 RR18

Claims (3)

[Claims] 1. A frequency synthesizer for generating an output signal having a frequency obtained by multiplying a frequency of a reference clock signal by a coefficient, wherein the variable oscillator circuit generates a clock signal group having a phase difference obtained by substantially equally dividing the cycle of the output signal. A control circuit that generates a phase selection control signal according to frequency setting data; a phase selection circuit that selects one clock signal from the group of clock signals according to the phase selection control signal and outputs it as a comparison clock signal; A frequency synthesizer comprising: a phase comparison circuit that compares a phase of a clock signal with a phase of the comparison clock signal; and a frequency control circuit that controls an oscillation frequency of the variable oscillation circuit according to an output of the phase comparison circuit. 2. A main phase selection circuit, wherein the phase comparison circuit selects two clock signals of adjacent phases from the clock signal group according to a first control signal of the phase selection control signal; According to a second control signal, one clock signal is selected from the two clock signals selected by the main phase selection circuit and a clock phase within a phase difference between the two clock signals, and a sub phase selection circuit that outputs the selected clock signal as a comparison clock signal. The frequency synthesizer according to claim 1. 3. An oscillation circuit, wherein said variable oscillation circuit is capable of changing an oscillation frequency and generates a single clock signal;
3. A delay circuit comprising a plurality of cascade-connected delay elements and a delay circuit for delaying the output of the oscillation circuit in multiple stages.
The frequency synthesizer according to 1.