JPH09172371A - Method for controlling charge pump provided for lpl circuit and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which can shorten lock up time and which can reduce power consumption. SOLUTION: A phase compactor 1 inputs a reference signal fr and a comparison signal fp and detects the phase deviation of the signals fr and fp. When a phase is deviated phase difference signals ϕ R and ϕ P, which correspond to the phase difference, are outputted to a charge pump part 2. The charge pump part 2 is constituted by two charge pumps 2a and 2b. The phase comparator 1 generates a lock detection signal LD outputted until the phase of the reference signal fr and that of the comparison signal are matched, and outputs it to a charge pump driving control circuit 3. The charge pump driving control circuit 3 sequentially operates the charge pumps from the charge pumps 2a and 2b in accordance with the time of the lock detection signal LD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump, and more particularly to a charge pump provided in a PLL circuit.

[0002] In recent years, along with the digitalization of mobile communication devices, it has been attempted to achieve high-speed lockup of a PLL synthesizer circuit provided in the mobile communication device, that is, to shorten the lockup time. PL as one method
The drive capability of the charge pump forming the L circuit is being increased. However, the power consumption is increased by increasing the driving capability of the charge pump, and a device for reducing the power consumption is required.

[0003]

2. Description of the Related Art Generally, a PLL circuit is required to have a high-speed lockup, that is, to shorten the lockup time. That is, when the set frequency is switched, it is required to shorten the time until the frequency of the output signal is fixed to the switched set frequency.

As a method for achieving high-speed lockup, it is advisable to increase the drive capability of the charge pump when switching the set frequency. Conventionally, the drive capacity of the charge pump is
Since it is fixed, the drive capacity of the charge pump is set so that the required maximum channel interval and the required maximum lockup time can be realized for each application such as a cordless phone, a mobile phone, and a PHS. Further, in order to improve the driving ability of the charge pump, it has been proposed to provide a plurality of charge pumps and drive them simultaneously (Japanese Patent Laid-Open No. 6-2760).
90).

[0005]

By the way, in the PLL circuit designed for each application described above, the driving capability of the charge pump can realize the required maximum channel interval and the required maximum lockup time. Since it is set, the charge pump always consumes the maximum power consumption for driving. Therefore, even if the channel switching is small and the lockup time is short, the charge pump consumes the maximum power consumption and is driven. As a result, useless power consumption is used, and a problem arises in mobile phones and the like that require low voltage and low power consumption. This also has a similar problem when a plurality of charge pumps described above are provided and driven simultaneously.

A PLL circuit having general versatility for each application is advantageous in consideration of manufacturing cost and the like. However, for a versatile PLL circuit, it is necessary to consider the drive capability of the charge pump so as to be compatible with each application as described above. Therefore, as described above, even in this case, wasteful power is used in the PLL circuit used for an application that does not require a large drive capacity for the charge pump, which is a problem in achieving low power consumption.

The present invention has been made to solve the above problems, and its purpose is to reduce the lock-up time and power consumption, and further, to reduce the power consumption. The object of the present invention is to provide a charge pump control method and a PLL circuit that have good properties.

[0008]

According to the invention of claim 1, the phases of the reference signal and the comparison signal are compared by a phase comparator, and the phase difference signal output from the phase comparator is determined based on the comparison result. A control method of a charge pump provided in a PLL circuit having a charge pump unit comprising a plurality of charge pumps for inputting and outputting an output voltage according to the phase difference signal to an output terminal, the method being compared with the reference signal. The number of charge pumps operating based on the phase difference signal is increased relative to the time required for the phases of the signals to coincide with each other, so that the drive capability of the charge pump unit is increased.

The invention of claim 2 is the PL according to claim 1.
In the method of controlling the charge pump provided in the L circuit, the time required for the phases of the reference signal and the comparison signal to coincide with each other is until the phases of the reference signal and the comparison signal generated by the phase comparator coincide with each other. The lock detection signal output is timed by the oscillation signal from the crystal oscillator used to generate the reference signal.

According to the third aspect of the invention, as shown in the principle explanatory diagram of FIG. 1, the phase comparator 1 uses the reference signal fr and the comparison signal fp.
Is input to detect a phase shift between both signals fr and fp. When the phases shift, the phase difference signals φR and φP corresponding to the phase difference are detected.
Is output to the charge pump unit 2. Charge pump unit 2
Is composed of two charge pumps 2a and 2b.

The phase comparator 1 also generates a lock detection signal LD that is output until the phases of the reference signal fr and the comparison signal fp match, and outputs the lock detection signal LD to the charge pump drive control circuit 3. The charge pump drive control circuit 3 sequentially operates the charge pumps from the charge pumps 2a and 2b based on the lock detection signal LD.

The invention of claim 4 is the PL according to claim 3.
In the L circuit, the charge pump drive control circuit is
The lock detection signal from the phase comparator and the oscillation signal from the crystal oscillator used to generate the reference signal are input, the time of the lock detection signal is measured by the oscillation signal, and the lock signal is generated. A selection signal generation circuit that generates a selection signal for selecting the charge pump to be driven corresponding to the time of the detection signal, and a plurality of charge pumps sequentially based on the selection signal from the selection signal generation circuit. A selector circuit which selects a charge pump and operates the selected charge pump based on the phase difference signal.

The invention of claim 5 is claim 3 or claim 4.
In the PLL circuit described in paragraph 1, the plurality of charge pumps have the same driving ability. (Operation) According to the invention of claim 1, the number of charge pumps that operate based on the phase difference signal is increased relative to the time required until the phases of the reference signal and the comparison signal match. Therefore, the drive capability of the charge pump unit increases as the time required until the phases of the reference signal and the comparison signal match. Therefore, the lockup time becomes shorter due to the increase in the driving ability. Further, for example, when the channel switching is small and the lockup time is within a short allowable range, that is, when the time until the coincidence is short, only the minimum number of charge pumps operate, which unnecessarily increases the driving capability. There is no need to drive an excessive number of charge pumps, and no unnecessary power consumption is consumed.

According to the invention of claim 2, in the method of controlling the charge pump provided in the PLL circuit according to claim 1, the phases of the reference signal and the comparison signal generated by the phase comparator match. The number of oscillation signals output while the lock detection signal is output is the time required for the phases of the reference signal and the comparison signal to match. Therefore, since the oscillation signal of the crystal oscillator incidental to the PLL circuit is used, the circuit scale of the PLL circuit is not increased.

According to the third aspect of the invention, the charge pump drive control circuit 3 based on the lock detection signal LD sequentially selects the charge pump 2 from the charge pumps 2a and 2b.
Operate a and 2b. Therefore, the lockup time becomes shorter due to the increase in the driving ability. Further, for example, when the channel switching is small and the lockup time is within a short allowable range, that is, when the time until the coincidence is short, only the minimum number of charge pumps operate, which unnecessarily increases the driving capability. There is no need to drive an excessive number of charge pumps, and no unnecessary power consumption is consumed.

According to the invention of claim 4, the selection signal generation circuit inputs the lock detection signal from the phase comparator and the oscillation signal from the crystal oscillator used for generating the reference signal. Then, the selection signal generation circuit clocks the time of the lock detection signal with the oscillation signal, and generates a selection signal for selecting the charge pump to be driven corresponding to the time of the lock detection signal. The selector circuit is provided between the plurality of charge pumps and the phase comparator and sequentially selects the charge pump from the plurality of charge pumps based on the selection signal from the selection signal generation circuit. Then, the selector circuit operates the selected charge pump based on the phase difference signal.

According to the fifth aspect of the invention, since the plurality of charge pumps have the same driving ability, the driving ability of the charge pump section is increased to double or triple. Moreover, since the circuit constants of the respective charge pumps are the same, an extra manufacturing process does not increase in manufacturing the PLL circuit.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows a block circuit of the PLL circuit. The PLL circuit is a crystal oscillator 1
1, reference frequency divider 12, comparison frequency divider 13, phase comparator 1
4, charge pump unit 15, low-pass filter (LP
F) 16, a voltage controlled oscillator (VCO) 17, a selection signal generation circuit 18, and a selector circuit 19. In the present embodiment, the crystal oscillator 1
Each circuit except 1 is formed in a one-chip semiconductor integrated circuit device, and the crystal oscillator 11 is formed by an external circuit.

The reference frequency divider 12 frequency-divides a predetermined oscillation signal Refin from the crystal oscillator 11 into a reference signal fr having a reference frequency shown in FIG. 6, and supplies the reference signal fr to the phase comparator 14. The comparison frequency divider 13 frequency-divides the output signal fvco from the VCO 17 and supplies the comparison signal fp shown in FIG. 6 to the phase comparator 14. Further, the comparison frequency divider 13 outputs the output signal f
When the frequency of vco is switched, that is, when so-called channel switching is performed, the division ratio is changed.

The phase comparator 14 compares the phases of the reference signal fr and the comparison signal fp. Then, the phase comparator 14
Outputs the first phase difference signal φR at the H level and the second phase difference signal φP at the L level when the phase of the comparison signal fp and the phase of the reference signal fr coincide with each other. Also, the phase comparator 1
4, when the phase of the comparison signal fp leads the phase of the reference signal fr, it outputs to the charge pump unit 15 the second phase difference signal φP which becomes H level as shown in FIG. In the present embodiment, the phase comparator 14 outputs the second phase difference signal .phi.P which becomes H level from the H level rising of the comparison signal fp to the rising of the reference signal fr.
At this time, the phase comparator 14 outputs the first phase difference signal φR which becomes H level.

On the contrary, the phase comparator 14 outputs the comparison signal fp.
6 is delayed from the phase of the reference signal fr, the first phase difference signal φR which becomes L level is output to the charge pump unit 15 as shown in FIG. In the present embodiment, the phase comparator 14 outputs the first phase difference signal .phi.R which becomes L level from the fall of the reference signal fr to the L level to the fall of the comparison signal fp. At this time, the phase comparator 14 outputs the second phase difference signal φP which becomes L level.

Further, the phase comparator 14 has a lock detection signal L.
Generate D. The lock detection signal LD is a signal that is output only after the phase difference between the reference signal fr and the comparison signal fp occurs and when they match. Then, in the present embodiment, as shown in FIG. 6, the phase comparison base 14 causes the first phase shift and the first H-level second phase difference signal φP.
(Or, the first phase difference signal φR of L level is output, and the first second phase difference signal φP thereof is changed from H level to L level.
When it falls to the level (or when the first first phase difference signal φR rises from the L level to the H level)
Outputs the H-level lock detection signal LD until the reference signal fr and the comparison signal fp are in phase with each other. Therefore, the longer the time from the occurrence of the phase shift between the reference signal fr and the comparison signal fp until the coincidence, the longer the phase comparator 14
Will continue to output the H-level lock detection signal LD for a long time.

The first and second phase difference signals φR and φP
Are supplied to the charge pump unit 15. As shown in FIG. 3, the charge pump unit 15 is composed of four first to fourth charge pumps CHP1 to CHP4. Since the first to fourth charge pumps CHP1 to CHP4 have the same circuit configuration, only the first charge pump CHP1 will be described and the other second to fourth charge pumps CHP2 to CHP2.
The description of CHP4 is omitted.

The first charge pump CHP1 has a PNP transistor T1 and an NPN transistor T2. The emitter terminal of the PNP transistor T1 is the power supply V
Connected to CC, collector terminal is NPN transistor T2
It is connected to the collector terminal of. The output terminal drawn from the node connecting the collector terminal of the PNP transistor T1 and the collector terminal of the NPN transistor T2 is
It is connected to the LPF 16 in the next stage. A resistor R is provided between the base terminal and the emitter terminal of the PNP transistor T1.
1 is connected. The emitter terminal of the NPN transistor T2 is grounded. A resistor R2 is connected between the base terminal and the emitter terminal of the NPN transistor T2.

In the first charge pump CHP1, the first phase difference signal φR is input to the base terminal of the PNP transistor T1 and the second phase difference signal φP is input to the base terminal of the NPN transistor T2. . When both the first and second phase difference signals φR and φP are L level (when the phase of the comparison signal fp is behind the phase of the reference signal fr), the PNP transistor T1 is turned on,
The NPN transistor T2 is turned off. At this time, the current from the power supply voltage Vcc flows from the output terminal of the first charge pump CHP1 to the LPF 16, and the first charge pump CHP1
The voltage D01 of the output terminal, that is, the charging voltage of the capacitor (not shown) provided in the LPF 16 is increased.

On the contrary, the first and second phase difference signals φR,
When both φP are at the H level (when the phase of the comparison signal fp leads the phase of the reference signal fr), the PNP transistor T1 is turned off and the NPN transistor T2 is turned on. At this time, a current flows from the LPF 16 into the first charge pump CHP1 to reduce the voltage D01 at the output terminal of the first charge pump CHP1, that is, the charging voltage of the capacitor of the LPF 16.

The second to fourth charge pumps CHP2 to
Signals φR1 to φR3 and φP1 to φP3 corresponding to the first and second phase difference signals φP are input to the base terminals of the PNP transistor T1 and the NPN transistor T2 in the CHP4 via the selector circuit 19, respectively.

The selector circuit 19 includes three first to third inverters 21 to 23 and three first to third NAND circuits 24.
To 26 and three first to third AND circuits 27 to 29
have.

The first NAND circuit 24 has two input terminals, and one of the input terminals receives the first phase difference signal φR via the first inverter 21. First NAND circuit 2
The other input terminal of 4 receives the first selection signal A from the selection signal generation circuit 18. The output terminal of the first NAND circuit 24 is connected to the base terminal of the PNP transistor T1 of the second charge pump CHP2. The first AND circuit 27 has two input terminals, and one input terminal receives the second phase difference signal φP. The other input terminal of the first AND circuit 27 receives the first selection signal A from the selection signal generation circuit 18. In addition, the first AND circuit 27
Is connected to the base terminal of the NPN transistor T2 of the second charge pump CHP2.

Therefore, when the first selection signal A is at H level,
The first and second phase difference signals φR from the phase comparator 14,
The signals φR1 and φP1 corresponding to φP are input to the second charge pump CHP2. Second charge pump CHP2
Controls the voltage D02 at the output terminal of the second charge pump CHP2, that is, the charging voltage of the capacitor provided in the LPF 16, in synchronization with the first charge pump CHP1 based on the signals φR1 and φP1.

The second NAND circuit 25 has two input terminals, and one of the input terminals receives the first phase difference signal φR via the second inverter 22. Second NAND circuit 2
The other input terminal of 5 receives the second selection signal B from the selection signal generation circuit 18. The output terminal of the second NAND circuit 25 is connected to the base terminal of the PNP transistor T1 of the third charge pump CHP3. The second AND circuit 28 has two input terminals, and one input terminal receives the second phase difference signal φP. The other input terminal of the second AND circuit 28 receives the second selection signal B from the selection signal generation circuit 18. In addition, the second AND circuit 28
Is connected to the base terminal of the NPN transistor T2 of the third charge pump CHP3.

Therefore, when the second selection signal B is at H level,
The first and second phase difference signals φR from the phase comparator 14,
The signals φR2 and φP2 corresponding to φP are input to the third charge pump CHP3. Third charge pump CHP3
Controls the voltage D03 of the output terminal of the third charge pump CHP3, that is, the charging voltage of the capacitor provided in the LPF 16, in synchronization with the first charge pump CHP1 based on the signals φR2 and φP2.

The third NAND circuit 26 has two input terminals, and one input terminal receives the first phase difference signal φR via the third inverter 23. Third NAND circuit 2
The other input terminal of 6 receives the third selection signal C from the selection signal generation circuit 18. The output terminal of the third NAND circuit 26 is connected to the base terminal of the PNP transistor T1 of the fourth charge pump CHP4. The third AND circuit 29 has two input terminals, and one input terminal receives the second phase difference signal φP. The other input terminal of the third AND circuit 29 receives the third selection signal C from the selection signal generation circuit 18. Also, the third AND circuit 29
Is connected to the base terminal of the NPN transistor T2 of the fourth charge pump CHP4.

Therefore, when the third selection signal B is at H level,
The first and second phase difference signals φR from the phase comparator 14,
Signals φR3 and φP3 corresponding to φP are input to the third charge pump CHP3. Fourth charge pump CHP4
Controls the voltage D04 at the output terminal of the fourth charge pump CHP4, that is, the charging voltage of the capacitor provided in the LPF 16, in synchronization with the first charge pump CHP1 based on the signals φR3 and φP3.

Next, the selection signal generating circuit 18 for generating the first to third selection signals A, B and C output to the selector circuit 19 will be described. The selection signal generation circuit 18 is
Three first to third flip-flops (FF) 31 to 33
And two AND circuits 34 and 35. First to first
The third FFs 31 to 33 are D-type flip-flops. The first FF 31 inputs the lock detection signal LD from the phase comparator 14 to the data input terminal and the reset input terminal. Further, the first FF 31 inputs the oscillation signal Refin from the crystal oscillator 11 to the control input terminal. 1st floor
F31 is a lock detection signal L input to the data input terminal at that time in response to the rising edge of the oscillation signal Refin.
The state of D is output from the output terminal. That is, when the oscillation signal Refin is input while the H-level lock detection signal LD is being output, the first FF 31 outputs the H-level output signal from the output terminal. The H-level output signal is output to the first NAND circuit 24 and the first AND circuit 27 as the first selection signal A. Also, 1st floor
The F31 is reset when the H-level lock detection signal LD falls from the H level to the L level, and sets the output signal (first selection signal A) output from the output terminal to the L level.

The second FF 32 inputs the first selection signal A to the data input terminal and the lock detection signal LD to the reset input terminal. Further, the second FF 32 inputs the oscillation signal Refin to the control input terminal. 2nd FF32
Outputs the state of the first selection signal A input to the data input terminal at that time from the output terminal in response to the rising of the oscillation signal Refin. That is, when the oscillation signal Refin is input while the H-level first selection signal A is being output, the second FF 32 outputs an H-level output signal from the output terminal. When the H-level lock detection signal LD falls from the H level to the L level, the second FF 32 is reset and sets the output signal output from the output terminal to the L level.

The output signal of the second FF 32 is the AND circuit 3
4 is output. The AND circuit 34 uses the first FF 31
The first selection signal A from is input. Then, when the AND circuit 34 inputs the H level output signal from the second FF 32 in the state where the H level first selection signal A is input,
The H-level output signal is output as the second selection signal B to the second NAND circuit 25 and the second AND circuit 28.

The third FF 33 has a data input terminal to which the second F is connected.
The output signal of F32 is input, and the lock detection signal LD is input to the reset input terminal. Further, the third FF 33 inputs the oscillation signal Refin to the control input terminal. 3rd FF
In response to the rising of the oscillation signal Refin, 33 outputs the state of the output signal of the second FF 32 input to the data input terminal at that time from the output terminal. That is, when the H level output signal is being output, the oscillation signal R
When efin is input, the third FF 33 outputs an H level output signal from the output terminal. Also, the third FF 33 is H
When the level lock detection signal LD falls from H level to L level, the output signal output from the output terminal is reset to L level.

The output signal of the third FF 33 is the AND circuit 3
5 is output. The AND circuit 35 includes the second FF 32.
The second selection signal B from is input. When the AND circuit 35 inputs the H-level output signal from the third FF 33 while the H-level second selection signal B is being input,
The H-level output signal is output as the third selection signal C to the third NAND circuit 26 and the third AND circuit 29.

Therefore, as shown in FIG. 4, when the phase comparator 14 outputs the H-level lock detection signal LD, the selection signal generation circuit 18 first oscillates after the detection signal LD is output. First H level in response to signal Refin
The selection signal A is output. Then, the selection signal generation circuit 18
Responds to the second oscillating signal Refin at the second H-level
The selection signal B is output. Therefore, at this point, the selection signal generation circuit 18 has the H-level first and second selection signals A,
B is output. If the lock detection signal LD becomes L level before the second oscillation signal Refin is output, the first F
Since F31 is reset and the first selection signal A becomes L level and disappears, the output signal of the second FF 32 remains L level.

Then, the selection signal generating circuit 18 responds to the third oscillation signal Refin to output the third selection signal C at the H level.
Is output. Therefore, at this point, the selection signal generation circuit 1
8 outputs the H-level first to third selection signals A to C. If the lock detection signal LD becomes L level before the third oscillation signal Refin is output, the first and second FFs are output.
31 and 32 are reset, and the first and second selection signals A,
Since B becomes L level and disappears, the output signal of the third FF 33 remains L level.

That is, when the H-level lock detection signal LD continues for a long time, the H-level first selection signal A is first output, and the first and second phase difference signals φR and φP are first and second. It is output to the charge pumps CHP1 and CHP2. Subsequently, when the second selection signal B is newly added, the first and second phase difference signals φR and φP are output to the first to third charge pumps CHP1 to CHP3. Further, when the third selection signal C is newly added, the first and second phase difference signals φR and φP are changed to the first to fourth charge pumps CHP1 to CHP.
It is output to P4. That is, if the unlocked state is long,
First to fourth charge pumps C that operate in accordance with it
The number of HP1 to CHP4 will increase.

Therefore, the first and second charge pumps CH
When P1 and CHP2 are selected and operated, the first and second charge pumps CHP1 and CHP2 are connected in parallel to the LPF 16. Therefore, when both the first and second phase difference signals φR and φP are at L level, the output terminals of the first and second charge pumps CHP1 and CHP2 are L level.
The current from the power supply voltage Vcc flows through the PF16, and the voltages D01 and D02 (= D0) of the output terminals of the first and second charge pumps CHP1 and CHP2, that is, the charging voltage of the capacitor provided in the LPF16 is doubled. Increase with ability.
On the contrary, the first and second phase difference signals φR and φP are both H
At the time of level, current flows from the LPF 16 into the first and second charge pumps CHP1 and CHP2, and the voltage D0 at the output terminals of the first and second charge pumps CHP1 and CHP2.
1, D02 (= D0), that is, the charging voltage of the capacitor of the LPF 16 is reduced by a double drive capability.

The first to third charge pumps CHP1 to CHP1
When CHP3 is selected and operated, the first to third charge pumps CHP1 to CHP3 are connected in parallel to the LPF 16. Therefore, when both the first and second phase difference signals φR and φP are at the L level, currents from the power supply voltage Vcc flow to the LPF 16 from the output terminals of the first to third charge pumps CHP1 to CHP3, and the first to the first 3 Voltages D01 to D03 of output terminals of charge pumps CHP1 to CHP3
(= D0), that is, the charging voltage of the capacitor provided in the LPF 16 is increased by a triple driving capability. On the contrary, when both the first and second phase difference signals φR and φP are at the H level, the LPF 16 causes the first to third charge pumps CHP1.
To CHP3, current flows, and the voltages D01 to D03 (=) at the output terminals of the first to third charge pumps CHP1 to CHP3
D0), that is, the charging voltage of the LPF 16 capacitor is set to 3
Double the driving ability to reduce.

The first to fourth charge pumps CHP1 to CHP1
When CHP4 is selected and operated, the first to fourth charge pumps CHP1 to CHP4 are connected in parallel to the LPF 16. Therefore, when both the first and second phase difference signals φR and φP are at the L level, currents from the power supply voltage Vcc flow to the LPF 16 from the output terminals of the first to third charge pumps CHP1 to CHP3, and the first to the first 4 Charge pumps CHP1 to CHP4 output terminal voltages D01 to D04
(= D0), that is, the charging voltage of the capacitor provided in the LPF 16 is increased by four times the driving capability. On the contrary, when the first and second phase difference signals φR and φP are both at the H level, the LPF 16 causes the first to fourth charge pumps CHP1.
Current flows into CHP4 to CHP4, and voltages D01 to D04 (=) at output terminals of the first to fourth charge pumps CHP1 to CHP4.
D0), that is, the charging voltage of the LPF 16 capacitor is set to 4
Double the driving ability to reduce.

The LPF 16 has a voltage D0 at the output terminals of the first to fourth charge pumps CHP1 to CHP4 at that time.
The charging voltage of the capacitor in the LPF 16 corresponding to
Output to O17. The VCO 17 generates an output signal fvco having a frequency corresponding to the charging voltage value of this capacitor and feeds it back to the comparison frequency divider 13.

Next, the operation of the PLL circuit configured as described above will be described. When the frequency of the output signal fvco locked at a certain frequency is changed, the frequency division ratio of the comparison frequency divider 13 is changed to a predetermined value. Thereby, the comparison signal f corresponding to each pulse of the reference signal fr of the reference frequency divider 12
The phase of each pulse of p changes and the comparison signal fp
Frequency changes.

Then, as shown in FIG. 6, the comparison signal fp
Phase leads the phase of the reference signal fr, the phase comparator 1
4 outputs to the charge pump unit 15 the second phase difference signal φP that becomes H level (the first phase difference signal φR remains at H level). That is, the phase comparator 14 outputs the second phase difference signal .phi.P which becomes the H level from the rising of the H level of the comparison signal fp to the rising of the reference signal fr output with a delay.

The first and second phase difference signals φR and φP
Is output to the first charge pump CHP1 and also to the selector circuit 19. At this point, the selection signal generation circuit 18 outputs the first to third selection signals A to
Since C is not output, the selector circuit 19 does not output the phase difference signals φR and φP from the phase comparator 14 to the second to fourth charge pumps CHP2 to CHP4.

Therefore, only the first charge pump CHP1 operates and the NPN transistor T1 turns on. And
A current flows from the LPF 16 to the first charge pump CHP1 to reduce the voltage D01 (= D0) at the output terminals of the first charge pumps CHP1 to CHP4, that is, the charging voltage of the capacitor of the LPF 16. The VCO 17 generates an output signal fvco having a frequency corresponding to the charging voltage value of this capacitor and feeds it back to the comparison frequency divider 13.

When the H level of the second phase difference signal φP becomes L level, the phase comparator 14 outputs the H-level lock detection signal LD. That is, the phase comparator 14 selects the lock detection signal LD which becomes H level until the comparison signal fp and the reference signal fr are in phase with each other.
Output to

When the H level lock detection signal LD is input, the selection signal generation circuit 18 responds to the oscillation signal Refin from the crystal oscillator 11 and outputs from the first FF 31 to the H level first signal.
The selection signal A is output. Based on the first selection signal A, the first NAND circuit 24 and the first AND circuit 27 of the selector circuit 19 are opened, and the first NAND circuit 24 outputs the signal φR1 corresponding to the first phase difference signal φR to the first AND circuit. The circuit 27 is in a state where it can output the signal φP1 corresponding to the second phase difference signal φP to the second charge pump CHP2.

In this state, the next comparison signal fp and the reference signal f
The phase comparison of r is performed by the phase comparator 14, and the comparison signal f
When the phase of p lags the phase of the reference signal fr, the phase comparator 14 outputs the first phase difference signal φR (the second phase difference signal φP remains at the H level) to the L level to the charge pump unit 15. Output to. That is, the phase comparator 14 is at the L level from the fall of the L level of the reference signal fr to the fall of the delayed comparison signal fp.
And outputs the phase difference signal φR.

The first and second phase difference signals φR and φP
Is output to the first charge pump CHP1. Further, the first and second phase difference signals φR and φP become the first and second phase difference signals φR1 and φP1 and are output to the second charge pump CHP2.

Therefore, the first and second charge pumps CH
P1 and CHP2 operate and the PNP transistor T2 turns on. Then, current flows from the output terminals of the first and second charge pumps CHP1, CHP2 from the LPF 16 to the LPF 16, and the first and second charge pumps CHP1, C
The voltage D01, D02 (= D0) at the output terminal of HP2, that is,
The charging voltage of the capacitor of the LPF 16 is increased with double the driving ability.

The VCO 17 generates an output signal fvco having a frequency corresponding to the charging voltage value of this capacitor and feeds it back to the comparison frequency divider 13. After that, the H-level lock detection signal LD
Is output, that is, until the phase of the comparison signal fp and the phase of the reference signal fr coincide with each other, the phase comparator 14 responds to the oscillation signal Refin by the second selection signal generating circuit 18 in response to the oscillation signal Refin.
The selection signal B and then the third selection signal C are generated, and the third charge pump CHP3 and then the fourth charge pump CHP4 are generated.
To be able to operate sequentially. That is, the drive capability of the charge pump unit 15 is 2 each time the oscillation signal Refin is output.
The PLL circuit promptly generates the output signal fvco in which the phases of the comparison signal fp and the reference signal fr coincide with each other while increasing the number of times, three times, four times. In addition, while the drive capability of the charge pump unit 15 is being doubled or tripled, the comparison signal f
When the phases of p and the reference signal fr match, that is, when the H-level lock detection signal LD disappears to the L level, the second to fourth charge pumps CHP2 to CHP4 are immediately deselected. When the two signals fP and fr are out of phase with each other again, the charge pump unit 15 again causes the first charge pump C
The operation is performed from HP1.

Next, the features of the embodiment configured as described above will be described below. (1) According to the present embodiment, the drive capability of the charge pump unit 15 is increased to 2 times, 3 times, and 4 times. Therefore, the lockup time can be shortened.

(2) According to the present embodiment, the drive capability of the charge pump unit 15 is determined by the comparison signal fp and the reference signal fr.
2 times, 3 relative to the time required to match the phases of
The number was increased four times. That is, in the present embodiment, the drive capability of the charge pump unit 15 is not always operated at the maximum drive capability from the beginning, but is gradually increased. Therefore, for example, when the channel switching is small and the lockup time is short in the permissible range, it is only necessary to operate the minimum number of charge pumps, and the drive capacity is unnecessarily increased to drive the extra number of charge pumps, which is a waste. It does not consume a lot of power.

(3) Further, as described above, the driving capability of the charge pump section 15 is increased relative to the time required for the phases of the comparison signal fp and the reference signal fr to match. Therefore, a PLL circuit used in an application that does not require much drive capacity of the charge pump,
It can also be used for both types of PLL circuits such as PLL circuits used in applications that require a large drive capacity of the charge pump. As a result, the PLL circuit of this embodiment can be provided with versatility and low power consumption.

(4) In this embodiment, since the charge pumps CHP1 to CHP4 of the charge pump unit 15 have the same configuration and the same circuit constants of the same elements, the PLL is the same.
This is advantageous in manufacturing without increasing the manufacturing process in manufacturing the circuit.

(5) Further, in the present embodiment, the comparison signal f
time required for the phase of p and the reference signal fr to match,
That is, the oscillation signal Refin of the crystal oscillator 11 incidental to the PLL circuit is used to measure the lock detection signal LD.
Therefore, since it is not necessary to provide an oscillation circuit for generating a dedicated signal for clocking the lock detection signal LD, the circuit scale can be reduced accordingly.

The present invention is not limited to the above embodiment, but may be carried out in the following modes. (1) In the above embodiment, the four first to fourth charge pumps CHP1 to CHP4 are used. The present invention is not limited to this, and may be implemented by appropriately changing the number to 2, 3, or 5 or more, for example.

(2) In the above embodiment, the oscillation signal Ref
The driving ability was increased to 2 times, 3 times, and 4 times each time in was output, but the timing for increasing the driving ability was appropriately changed, for example, it was increased each time two oscillation signals Refin were output. You may carry out.

(3) In the above embodiment, the oscillation signal R from the crystal oscillator 11 is set as the timing for increasing the driving capability.
Although efin is used, it may be implemented using a timer provided in a semiconductor integrated circuit in which a PLL circuit is formed, a clock signal from an external device, or the like.

(4) In the above embodiment, the first phase shift occurs and the first H-level second phase difference signal φP is generated.
(Or, the first phase difference signal φR of L level is output, and the first second phase difference signal φP thereof is changed from H level to L level.
When it falls to the level (or when the first first phase difference signal φR rises from the L level to the H level)
Therefore, the H-level lock detection signal LD is output until the phases of the reference signal fr and the comparison signal fp match.
This is the H-level lock detection signal LD from when the first phase difference occurs and the first H-level second phase difference signal φP (or L-level first phase difference signal φR) is output. May be output. In this case, it is necessary to generate the selection signals A to C sequentially from the second oscillation signal Refin.

[0066]

According to the first aspect of the present invention, the lockup time can be shortened and the power consumption can be reduced.

According to the invention of claim 2, in addition to the effect of the invention of claim 1, since the oscillation signal incidental to the PLL circuit is used, the circuit scale of the PLL circuit is not increased. According to the invention of claim 3, the lock-up time can be shortened and the power consumption can be reduced.

According to the invention of claim 4, in addition to the effect of the invention of claim 3, since the oscillation signal from the crystal oscillator incidental to the PLL circuit is used, the circuit scale of the PLL circuit is not increased.

According to the invention of claim 5, the manufacturing of the PLL circuit is very easy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a PLL circuit according to an embodiment.

FIG. 3 is a circuit diagram showing a charge pump unit, a selection signal generation circuit, and a selector circuit.

FIG. 4 is a time chart for explaining the operation of the selection signal generation circuit.

FIG. 5 is a time chart for explaining the operation of the selector circuit.

FIG. 6 is a time chart for explaining the operation of the PLL circuit.

[Explanation of symbols]

 1 phase comparator 2 charge pump unit 2a, 2b charge pump 3 charge pump drive control circuit fr reference signal fp comparison signal φR, φP phase difference signal LD lock detection signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuji Washimi 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu Viersuai Co., Ltd. (72) Akiki Aoki 1844-2 Kozoji-cho, Kasugai-shi, Aichi Within Fujitsu VIS Ltd.

Claims (5)

[Claims] 1. A phase difference between a reference signal and a comparison signal is compared by a phase comparator, a phase difference signal output from the phase comparator is input based on the comparison result, and an output corresponding to the phase difference signal is input. A method for controlling a charge pump provided in a PLL circuit having a charge pump unit comprising a plurality of charge pumps for outputting a voltage to an output terminal, wherein the time required for the phases of the reference signal and the comparison signal to coincide A method of controlling a charge pump provided in a PLL circuit in which the number of charge pumps operating based on a phase difference signal is increased to increase the drive capability of a charge pump unit. 2. The method of controlling a charge pump provided in the PLL circuit according to claim 1, wherein the time required for the phases of the reference signal and the comparison signal to coincide with each other is a reference generated by the phase comparator. A charge pump provided in a PLL circuit for timing a lock detection signal that is output until the phases of the signal and the comparison signal match with the oscillation signal from the crystal oscillator used to generate the reference signal. Control method. 3. The phase of the reference signal and that of the comparison signal are compared by the phase comparator, the phase difference signal output from the phase comparator is input based on the comparison result, and the output corresponding to the phase difference signal is output. A PLL circuit having a charge pump unit composed of a plurality of charge pumps for outputting a voltage to an output terminal, wherein a lock detection signal is output by the phase comparator until the phases of the reference signal and the comparison signal match. As well as generate
A PLL circuit provided with a charge pump drive control circuit for sequentially operating charge pumps from a plurality of charge pumps based on the lock detection signal to increase the drive capability of the charge pump unit. 4. The PLL circuit according to claim 3,
The charge pump drive control circuit inputs a lock detection signal from the phase comparator and an oscillation signal from a crystal oscillator used to generate the reference signal, and sets the time of the lock detection signal to the oscillation. A selection signal generation circuit that generates a selection signal for timing the signal and selects the charge pump to be driven corresponding to the time of the lock detection signal; and a plurality of selection signal generation circuits based on the selection signal from the selection signal generation circuit. A PLL including a selector circuit configured to select a charge pump from the individual charge pumps and operate the selected charge pump based on the phase difference signal.
circuit. 5. The PLL circuit according to claim 3, wherein the plurality of charge pumps have the same driving ability.