KR940005934B1 - Phase difference detecting circuit - Google Patents

Phase difference detecting circuit Download PDF

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KR940005934B1
KR940005934B1 KR90008663A KR900008663A KR940005934B1 KR 940005934 B1 KR940005934 B1 KR 940005934B1 KR 90008663 A KR90008663 A KR 90008663A KR 900008663 A KR900008663 A KR 900008663A KR 940005934 B1 KR940005934 B1 KR 940005934B1
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South Korea
Prior art keywords
signal
input
output
phase
phase difference
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KR90008663A
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Korean (ko)
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KR910002135A (en
Inventor
시니찌 세끼네
후미따까 아사미
유끼노리 가미조노
Original Assignee
야마모또 다꾸마
후지쓰 가부시끼가이샤
미야따 아쓰미
규슈 후지쓰 일렉트로닉스 가부시끼가이샤
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Priority to JP1-152901 priority Critical
Priority to JP1152901A priority patent/JP2795323B2/en
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0802Details of the phase-locked loop the loop being adapted for reducing power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Abstract

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Description

Phase difference detection circuit

1 is a block diagram showing the structure of a phase difference detection circuit according to the present invention.

2 is a block diagram showing a phase difference detection circuit applied to a PLL frequency synthesizer.

3 is a diagram schematically showing a structure divided by the N-type counter of FIG.

4 is a schematic view showing the structure of the phase comparator and charge pump of FIG.

5 and 6 are timing diagrams showing a method of operating a phase difference detection circuit.

FIG. 7 (a) shows a condition in which the phase difference between the input signals INA and INB is always higher than the predetermined time difference dt.

7 (b) shows a condition in which the phase difference is smaller than the predetermined time difference dt.

8 is a timing diagram used to explain why a signal INA is input to a three input NAND gate in addition to the output XQ1 of DFF1 and the output Q2 of DFF2.

9 is a timing diagram illustrating how the PLL IC of FIG. 2 operates.

10 is a block diagram showing the structure of a conventional PLL frequency synthesizer.

The present invention relates to a phase difference detection circuit and more particularly to a circuit used in a frequency synthesizer using a PLL (Phase Synchronous Loop).

Phase-locked loops, or PLLs, are circuits that generate signals corresponding to input signals in phase and frequency and are widely used in speed control and frequency synthesizers of motors (e.g., audio players). To stabilize the oscillation frequency and to change the frequency, the PLL synthesizer-type oscillator is very suitable and is also used in FM transmitters.

With the recent expansion of PLL applications, various characteristics of PLLs have been required. For example, shorter lock-up times and improved PLL stability have been required. Among frequency synthesizers that use PLLs to minimize power consumption of the entire circuit, the circuits are intermittently intercepted into two types of PLLs: standby mode with low power consumption and operating mode with the circuit operating. Frequency synthesizers that operate are known.

In an intermittent PLL frequency synthesizer, there are basically two ways of stopping operation. The power supply is turned off for circuits other than voltage controlled oscillators (VCOs) in the PLL, the VCO input voltage remains at the time constant of the lowpass filter, and the VCO output frequency is approximately equal to the frequency at the lock time of the PLL. There is one way to maintain the frequency. There is another way to turn off the power supply for all circuits, including the VCO. In either of these methods, the VCO output oscillating frequency should not fluctuate when the PLL's operation is restarted by applying power.

A conventional PLL frequency synthesizer of this type is shown in FIG. In that figure, reference oscillator 1 comprises a stable crystal oscillator and generates the original signal X in . The reference divider 2 is programmed to divide the original signal X in frequency from the reference oscillator 1 by the number R, and occurs so that the frequency of the reference signal f r is equal to the frequency of the original signal X in divided by R. Comparative divider 4 is programmed to divide the frequency of the output signal X in from VCO 7 by the number N and occurs such that the frequency of the conversion signal f v is equal to the frequency of the VCO output signal X in divided by N. The phase comparator 3 becomes a phase detection circuit by a logic element and compares the frequency and phase of the reference signal f r with the frequency and phase of the converted signal f v . Phase comparator 3 outputs comparison outputs E U and E D in proportion to the frequency and phase difference between the two signals f r and f v . If the reference signal f r leads the converted signal f v at a phase or if f r is higher at a frequency than f v (f r > f v ), the comparison output E U is at a time proportional to the phase difference between the two signals. Will be low, but the comparative output E D will remain high. On the other hand, if the conversion signal f v leads the reference signal f r in phase, or if f v is higher in frequency than f r (f v > f r ), the comparison output E D is applied to the signal proportional to the phase difference between the two signals. Will be low, but the comparative output E U will remain high. If the reference signal f r and the conversion signal f v are in phase, both the comparison outputs E U and E D will be high. For example, charge pump 5 includes P-channel and N-channel MOS (metal oxide semiconductor) transistors and inverters. Comparing the output to a E U, and based on the E D, a comparison output E U and E D when both high charge pump 5 outputs a signal at a high impedance and a low E U E D is high or E U is high and E O When low, it outputs a high or low signal. In other words, the comparison output E U or E D is low for a time proportional to the phase difference between the two signals f r and f v such that the MOS transistor of the charge pump 5 is turned on to charge or discharge the output line. low). By this function, the error voltage resulting from the phase difference between the two signals f r and f v generates the output of the LPF (low pass filter) 6 connected to the charge pump 5. VCO 7 is an oscillator whose output frequency can be easily converted by a change in the external applied voltage. If the phase of signal f v leads the phase of signal f r , the VCO oscillation frequency will be reduced until the two signals f r and f v are in phase. If the phase of signal f r leads the phase of signal f v , the VCO oscillation frequency will be increased until the two signals f r and f v are in phase.

In the PLL configured as described above, a signal is generated in phase with the reference signal f r at the output terminal of VCO 7 and has a frequency f vco (= Nf r ). Therefore, if the comparator 4 constitutes a programmable counter and the number N applied to the divider is changed to an arbitrary value by an external control signal, a signal having a desired frequency is generated at the VCO output terminal.

However, in the conventional phase difference detection circuit having intermittent operation by the two modes of the standby mode and the operation mode, when the circuits are alternately operated and stopped at predetermined time intervals, the two signals at the time when the standby mode is switched to the operation board The relative phase relationship between the reference signal f r and the comparison signal f v becomes unstable even if the frequency of? In other words, it is impossible to predict at what point the signals f r and f v are output because the change of mode cannot make the flip-flop levels of the reference divider 2 and the compare divider 4 stable. For this reason, phase comparator 3 tends to output a very large error signal if the circuit is operated again under the condition that the phase difference between the signals f r and f v supplied to the phase comparator 3 becomes large. In that case, the VCO output oscillation frequency f vco changes significantly after the operation of the PLL because the PLL operates to reduce the phase difference between signals f r and f v . As a result, a problem arises that the loop takes a long time to acquire a lock.

It is therefore an object of the present invention to provide a phase difference detection circuit which is used in PLL frequency synthesizers and the like and which can significantly shorten the time required to minimize VCO output frequency variation at the start time of PLL operation and to lock the loop at phase and frequency. It is.

According to the object of the invention, between the phase comparison means and the first and second input signals having an output mode corresponding to the phase difference between the first input signal and the second input signal and having an active mode and a standby mode for reducing power consumption. It is to provide a phase comparison circuit including phase difference detection means connected to the phase comparison means for outputting a control signal when the phase difference of P is smaller than a predetermined value. The phase comparison means is switched to the active mode in the standby mode in response to the control signal.

According to another object of the present invention, there is provided a phase comparison means and an external power saving control signal having a standby mode which generates an output signal in response to the phase difference between the first external input signal and the second external input signal and reduces the active mode and power consumption. A semiconductor integrated circuit device comprising phase difference detecting means connected to phase comparing means for outputting a control signal when instructing switching from the standby mode to the active mode and when the phase difference between the first and second external inputs is less than a predetermined value; To provide. The phase comparing means switches from the standby mode to the active mode in response to the control signal.

According to still another object of the present invention, there is a standby mode which generates an output signal synchronized in phase of a reference signal, has an active mode and a power consumption reduction, and switches from an active mode to a standby mode in response to a power saving control signal. A phase difference detection circuit connected to the phase-synchronous loop circuit to output the control signal when the phase-synchronous loop circuit and the power saving control signal are released and when the phase difference between the reference signal and the output signal is smaller than a predetermined value. An intermittent-operated phase-locked loop system is included. The phase-locked loop circuit is switched from the standby mode to the active mode in response to the control signal.

According to another object of the present invention, by configuring the phase of the first signal compared to the phase of the second signal and by putting the phase-locked loop system portion in a standby state, power consumption is reduced and the phase difference between the first and second signals is reduced. The present invention provides a method of reducing power consumption of a phase-locked loop system by detecting and switching a power reduction step to a phase comparison step when the phase difference is smaller than a predetermined value.

According to still another object of the present invention, there is a substantial phase difference between the two signals when the two signals held by the holding means and the holding means for holding logic levels of two different frequency input signals rise or fall within a predetermined range. It is to provide a phase comparison circuit including a signal output means for outputting a signal so as not to generate.

According to another object of the present invention, a first flip-flop having a data input terminal into which a first signal having a first frequency is input and a clock input terminal into which a second signal having a second frequency is input, and delaying the second signal by a predetermined delay. A second flip-flop having a delay input for inputting the first signal and a clock input terminal to which the output of the delay means is input, an output of the first signal and the first flip-flop and an output of the second flip-flop A phase comparison, comprising logic means, wherein a signal is output by the logic means indicating that there is substantially no phase difference between the two outputs when the first flip-flop output and the second flip-flop output rise or fall within a predetermined range To provide a circuit.

In FIG. 1, a preferred embodiment of the phase difference detection circuit 11 according to the present invention is shown. The phase difference detection circuit 11 latches the output of the phase difference detection unit 12 and the phase difference detection unit 12 for detecting the phase difference between the first signal INA having the first frequency and the second signal INB having the second frequency, and outputs “OUT” of the phase difference detection circuit 11. As a latching portion 13 for outputting it. The phase difference detection section 12 is connected to the first D flip-flop (DFF1) 14, the second D flip-flop (DFF2) 15, the delay circuit 18 including the inverters 16 and 17, and the three-input NAND gate (logic means) 19. It is composed.

The first D flip-flop (DFF1) 14 is a data terminal D to which the first signal INA having a different frequency from the second signal INB is input, a clock terminal CK to which the second signal INB is input, a reset terminal to which the reset signal RES is input, and a 3-input NAND. It has an output terminal XQ1 connected at the input terminal of the gate 19. Similarly, the second D flip-flop (DFF2) 15 is the data terminal D to which the first signal INA is input, and the clock terminal to which the third signal INC delayed from the second signal INB is input by the predetermined time (phase) difference dt by the delay circuit 18. CK, a reset terminal to which the reset signal RES is input, and an output terminal Q2 connected to the input terminal of the three-input NAND gate 19. The first signal INA with the first frequency is also input to the three-input NAND gate 19. The output X of the three-input NAND gate 19 is output to the latching portion 13 consisting of the cross-coupled NAND gates 20, 21 and the inverter 22. The NAND gate 20 has an input terminal to which the output X of the 3-input NAND gate 19 is input, while the NAND gate 21 has an input terminal to which the reset signal RES is input. Thus, the same first signal INA is input to both the first flip-flop 14 and the second flip-flop 15 and the clock of the second flip-flop 15 is delayed from the clock of the first flip-flop 14 by the time difference dt between the signals INB and INC. .

2 shows a PLL frequency synthesizer to which the phase difference detection circuit 11 is applied. Parts substantially the same as the corresponding parts in FIG. 10 are designated by the same reference numerals and detailed description thereof will be omitted. In FIG. 2, the PLL integrated circuit 31 is output from the first AND gate 32 to which the signals OSC IN and the power saving control signal PS corresponding to the INA and RES signals of FIG. 1 are input, respectively, and the power saving control signals PS and VCO. Second AND gate 33 to which signal f IN (corresponding to INB in FIG. 1) is input, programmable reference frequency divider 2 to which the output of the first AND gate 32 is input, and programmable comparative frequency divider to which the output of the second AND gate 33 is input. It consists of four. The outputs of the AND gates 32 and 33 and the power saving control signal PS are input to the phase difference detecting circuit 11, and the phase difference detecting circuit 11 detects the phase difference between the OSC IN and f IN signals to output the output of the phase difference detecting circuit 11 of FIG. ) And the control signal PS1 corresponding to the reference frequency divider 2 and the comparison frequency divider 4 are output. The output f r of the reference frequency divider 2, the output f v of the comparison frequency divider 4, the power saving control signal PS and the control signal PS1 are input to the phase comparator 3. The phase comparator 3 is connected to a charge pump 5 which outputs the PLL IC output D 0 to the low pass filter 6 connected to VCO 7. The standby control of the phase comparator 3 may be performed by the power saving control signal PS instead of the control signal PS1 as shown by the dotted line in FIG. In this case, phase comparator 3 is more easily active than frequency dividers 2 and 4, but it is not a problem because frequency dividers 2 and 4 are not active until the phases of signals OSC IN and f IN become small.

3 schematically shows the structure of frequency divider 4 divided by N which is substantially the same as the structure of frequency divider 2 divided by R. FIG. The output control signal PS1 from the phase difference detection circuit 11 goes low in the standby mode (when PS = 0). If the SET terminals of the first flip-flop F1 and the second flip-flop F2 are low and the CLEAR terminal of the third flip-flop is low, the output Q1 of the first flip-flop F1 and the output Q2 of the second flip-flop F2 are high ( ) And the output of the third flip-flop is Q3 low. The output Q3 of the third flip-flop F3 is connected to the LOAD terminal and the NOR gate 34 from the flip-flop f1 to fn. The output Q of fn in the flip-flop f1 is connected to the input of the detection circuit DET to detect the digital value through the inverter. The output of the circuit DET is connected to the input D of the first flip-flop F1. At the time of the load state (LOAD = low), the flip-flop f1 to fn are in the split ratio data read state and cannot proceed to the counting state even when the clock signal f IN is input. Since these two inputs of the NOR gate 34 is then low and high output f v of the frequency divider 4 is low. In active mode (when PS = 1), the control signal PS1 will be high if the input signals of frequency dividers 2 and 4 rise simultaneously. As a result, when both inputs of the NOR gate 34 are low when the control signal PS1 goes high, the output f v becomes high, so the output f v is output. If control signal PS1 is high, flip-flops F1, F2 and F3 are all reset and the count will begin when clock signal f IN transitions from low to high. If the LOAD terminal from flip-flop f1 to fn is high level, all of fn at flip-flop f1 will be reset and the division operation will begin. Thereafter, the division operation is executed according to the predetermined division ratio.

4 schematically shows the structure of the phase comparator 3 and the charge pump 5. As shown in FIG. In the standby mode (when PS = 0), the flip-flops Fa and Fb of phase comparator 3 are cleared because the control signal PS1 is low. Output Q of flip-flop Fa goes low and output XQ of flip-flop Fb goes high. At this time, both the P-channel and N-channel MOS transistors of charge pump 5 are blocked and the PLL IC output D 0 is in a high impedance state. If control signal PS1 goes high, flip-flops Fa and Fb are reset (because one of the two inputs of NAND gate 35 goes high) and the normal phase to detect the phase difference between reference signal f r and converted signal f v The comparison operation is executed. The PLL IC output D 0 remains in a high impedance state until the phase comparison operation begins.

The operation will be described below.

5 and 6 are timing diagrams showing the operation of the phase difference detection circuit 11. 5 shows waveforms when the phase difference between the input signals INA and INB becomes larger than the phaser dt between the input signals INB and INC, while FIG. 6 shows that the phase difference t2 between the input signals INA and INB is equal to the input signals INB and INC. The waveform when smaller than the phase dt in between is shown. Assume that signals INA and INB are other signals whose frequencies are not equal in phase. With this condition, if two signals INA and INB are input without RES input, the relationship between the two signals will be in the state shown in Figs.

In FIG. 5, the output XQ1 of D flip-flop 14 or DFF1 is low so that the output OUT of phase difference detection circuit 11 is low because the phase difference t1 between two signals INA and INB is greater than the phase difference dt between signals INB and INC. And output Q2 of D flip-flop 15 or DFF2 is high.

As shown in FIG. 6, if the rising edge of the signal INB leads the rising edge of the signal INA and the phase difference t2 between the two signals INA and INB is within the phase difference dt between the signals INB and INC, the output XQ1 of DFF1 is DFF1 will go high because it reads the level of signal INA before the rising edge of signal INA, and output Q2 of DFF2 will go high because DFF2 reads the level of signal INA after rising of signal INA. At this time, since the signal INA is high, the output X of the NAND gate 19 goes low and the output OUT of the detection circuit 11 goes low. In this way, the state where the phase difference between the two signals INA and INB is within the phase difference dt between the signals INB and INC is detected.

As shown in Fig. 7 (a), if both the input signals INA and INB have no frequency conversion and the phase difference t1 is larger than dt, the PLL will not operate because the phase difference is always larger than the predetermined time difference dt. To avoid this condition, it is instantaneous that the signals INA and INB are not equal in frequency and phase and therefore the phase difference t6 is smaller than dt as shown in Fig. 7 (b). In fact, in the intermittent operation of the PLL, the charge pump output becomes high impedance at the standby time and the low pass filter can maintain the output voltage when the loop is locked by capacity. However, the condition of FIG. 7 (a) in which the phase difference is always larger than the predetermined time difference dt cannot occur because the output voltage changes slightly due to the leakage current and the frequency changes slightly.

The phase difference dt between the signals INB and INC can be easily converted by simply increasing and decreasing the values of the inverters 16 and 17 of the delay circuit 18. The phase difference dt between the signals INB and INC is set such that the two low to high transitions or the high to low transition can be quickly matched depending on the frequencies of the two signals. For example, a larger phase difference dt is set when the low to high transition of the signal INA does not match the low to high transition of the signal INB. In the phase difference detection circuit 11, the transitions from the low to the high of the signals INA and INB are simultaneously detected. If the output OUT of the phase difference detection circuit 11 changes, it is necessary to reset the circuit after that time to detect the transition from low to high. The reset signal RES is input to the DFF1, DFF2 and latching section 13 as shown in FIG.

In the embodiment of FIG. 1, the signal INA is input to the three-input NAND gate 19 in addition to the output XQ1 of DFF1 and the output Q2 of DFF2. The reason for this is as follows. That is, if only the outputs of XQ1 and Q2 are connected without the signal INA connected, then the output X of circuit 11 will go low regardless of the phase difference between the signals INA and INB as shown at point A in FIG. As a result, the output OUT of circuit 11 that changes at the point of FIG. 8 will change. The reason is that when output Q2 of DFF2 goes high at point a of FIG. 8, output XQ1 of DFF1 goes high at point A and output Q2 goes low, output Q2 is delayed by the phase difference dt between signals INB and INC. This is because the output X of the NAND gate 19 goes low level. In the embodiment of Fig. 1, the signal INA is input to the NAND gate 19 to eliminate this improper operation and thus the problem described above is overcome.

9 is a timing diagram when the phase difference detection circuit 11 is applied to the PLL IC 31. In this figure, it is assumed that PLL IC 31 is in standby mode (PS = low). In addition to this state, each counter is reset and the charge-pump output is in a high impedance state. Therefore, at lock time the voltage is maintained by the time constant CR of the low pass filter 6 and the external VCO 7 ideally oscillates at the frequency f IN of time, but in fact the VCO oscillation frequency changes somewhat due to leakage.

If the standby mode is switched to the operation mode, each input gate is opened and the oscillating output of the external OSC is input by the OSC IN signal and transmitted to the phase difference detecting circuit 11. The VCO oscillation output is also input by the f IN signal and transmitted to the phase difference detection circuit 11. If the rising edges of the two signals are as shown in Fig. 6, the control signal PS1 is output from the circuit 11 to the frequency dividers 2 and 4. If the frequency dividers 2 and 4 are operated simultaneously with the input of the control signal PS1 to the frequency dividers 2 and 4 to output the signals f r and f v to the phase comparator 3, the error signal will be very small and the lock-up ) Time can be significantly faster.

In the present invention, a transition state in which two different frequency signals become high or low in a predetermined range is detected, and the counter of the reference frequency divider 2 and the comparison frequency divider 4 are operated at the same time. Therefore, if the phase difference detection circuit 11 according to the present invention is used, for example, by operating the PLL IC intermittently, the reference signal f r and the comparison signal f v having the same phase can be generated for a very short time. As a result, the error signal can be very small, so that the lock-up time is very short, which greatly improves the performance of the PLL synthesizer.

The present invention has been described in connection with a preferred embodiment. Obviously, it should be noted that modifications and variations can be made by reading and understanding the present application within the spirit of the invention.

Claims (12)

  1. Phase comparison means for generating an output signal corresponding to the phase difference between the first input signal and the second input signal, and having a standby mode for reducing an active mode and power consumption; and a phase difference between the first and second input signals is greater than a predetermined value. And a phase difference detecting means connected to said phase comparing means for outputting a control signal when small and said phase comparing means switches from said standby mode to an active mode in response to said control signal.
  2. 2. The apparatus according to claim 1, wherein the phase comparing means inputs a first frequency divider for dividing a first input signal, a second frequency divider for dividing a second input signal, and an output of the first frequency divider and an output of the second frequency divider. A phase comparator, wherein each of said first and second frequency dividers has said active mode and a standby mode and switches from said standby mode to an active mode in response to said control signal.
  3. The phase comparison circuit of claim 2, wherein the phase comparator has an active mode and a standby mode, and switches from the standby mode to the active mode in response to a control signal.
  4. The second flip-flop according to claim 1, wherein said phase difference detecting means comprises: a first flip-flop having a data input terminal to which said first input signal is input and a clock input terminal to which said second input signal is input; A second flip-flop, a first input signal, an output of the first flip-flop, and a second flip-up having a delay means for delaying the signal and a data input terminal to which the first input signal is input and a clock input terminal to which the output of the delay means is input. Logic means into which the output of the flop is input, and when the output of the first flip-flop and the output of the second flip-flop rise or fall within a predetermined range, there is substantially no phase difference between the two outputs And a signal for informing that the signal is output by said logic means.
  5. Phase comparison means having a standby mode for generating an output signal corresponding to the phase difference between the second external input signal and reducing the power consumption and an external power saving control signal from the standby mode to the active mode. A phase difference detecting means connected to said phase comparing means for outputting a control signal when instructing switching and when said phase difference between said first and second external input signals is less than a predetermined value, said phase comparing means being said And a switch from the standby mode to the active mode in response to a control signal.
  6. 6. The apparatus according to claim 5, wherein said phase comparing means comprises: a first frequency divider for dividing a first external input signal, a second frequency divider for dividing a second external input signal, an output of said first frequency divider and said second frequency divider; And a phase comparator to which an output is input, said first and second frequency dividers each having said active mode and a standby mode and switching from a standby mode to an active mode in response to said control signal.
  7. 7. The semiconductor integrated circuit device according to claim 6, wherein the phase comparing means has an active mode and a standby mode and switches from a standby mode to an active mode in response to the external power saving control signal.
  8. 7. The semiconductor integrated circuit device of claim 6, wherein the phase comparator has an active mode and a standby mode and switches from a standby mode to an active mode in response to the control signal.
  9. 7. The apparatus according to claim 6, wherein the phase comparison means includes: a first gate circuit and a second external input signal having an input terminal to which the first external input signal and an external power saving control signal are input, and an output terminal connected to the first frequency divider; And a second gate circuit having an input terminal to which an external power saving control signal is input and an output terminal connected to the first frequency divider, wherein the first and second gate circuits are the first external input signal when the external power saving control signal is active. And allowing the second external input signal to pass through and preventing the first external input signal and the second external input signal from passing when the external power saving control signal is inactive.
  10. A phase-locked loop circuit and power saving which generate an output signal synchronized with a phase of a reference signal and have a standby mode for reducing power consumption and switching from the active mode to the standby mode in response to a power saving control signal A phase difference detection circuit connected to said phase-synchronous loop circuit for outputting a control signal when a control signal is restored and a phase difference between said reference signal and said output signal is smaller than a predetermined value, and said phase-synchronous loop circuit Is switched from the standby mode to the active mode in response to the control signal.
  11. A holding means for maintaining the logic level of two different frequency input means and a signal indicating that there is substantially no phase difference between the two signals when the two signals held by the holding means rise or fall within a predetermined range; Phase comparison circuit comprising a signal output means for outputting.
  12. A first flip-flop having a data input terminal to which a first signal having a first frequency is input and a clock input terminal to which a second signal having a second frequency is input; delay means for delaying the second signal by a predetermined delay; A second flip-flop having a data input terminal to which a signal is input and a clock input terminal to which an output of the delay means is input, and logic means to which an output of the first signal and a first flip-flop are input; When the first flip-flop output and the second flip-flop output rise or fall within a predetermined range, a signal is output by the logic means to indicate that there is substantially no phase difference between the two outputs. Phase comparison circuit.
KR90008663A 1989-06-14 1990-06-13 Phase difference detecting circuit KR940005934B1 (en)

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JP1-152901 1989-06-14
JP1152901A JP2795323B2 (en) 1989-06-14 1989-06-14 Phase difference detection circuit

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KR910002135A KR910002135A (en) 1991-01-31
KR940005934B1 true KR940005934B1 (en) 1994-06-24

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JPH0318122A (en) 1991-01-25
EP0402736B1 (en) 1996-04-24
DE69026646D1 (en) 1996-05-30
KR910002135A (en) 1991-01-31
DE69026646T2 (en) 1996-09-12
US5103192A (en) 1992-04-07
EP0402736A2 (en) 1990-12-19
JP2795323B2 (en) 1998-09-10
EP0402736A3 (en) 1991-05-08

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