CN107565935B

CN107565935B - Circuit for reducing power consumption of oscillator

Info

Publication number: CN107565935B
Application number: CN201710797912.XA
Authority: CN
Inventors: 侯力梅
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2017-09-06
Filing date: 2017-09-06
Publication date: 2021-07-02
Anticipated expiration: 2037-09-06
Also published as: CN107565935A

Abstract

The invention discloses a circuit for reducing power consumption of an oscillator, which comprises a current source and a control switch, wherein a current mirror comprises M4, M5 and M7, a current mirror M6 is additionally arranged in the current mirror, and the M6 is connected to the drain electrode of M5 through a switch S3 to provide bias current for a resistor. Since the switch S3 is turned off during discharging, the M6 is in an off state, thereby reducing dynamic power consumption.

Description

Circuit for reducing power consumption of oscillator

Technical Field

The invention belongs to the technical field of oscillators, and particularly relates to an on-chip RC oscillator technology.

Background

With the rise of the internet of things era, smart homes and smart health MCUs have an increasingly large market, and a body fat scale and a kitchen scale become indispensable parts in life of people for the health life style pursued by people at present. The clock generation circuit is an indispensable module in the fields of SoC and MCU, and the performance of the clock generation circuit plays an important role for MCU and SoC chips. The long power consumption time and the large power consumption of the chip can generate heat, which affects the service life of the chip, so that the reduction of the power consumption is particularly important.

For example, patent application 201710110975.3 discloses a high-stability low-power consumption on-chip OSC circuit, in which a capacitor is charged and discharged by a current source, and a switching tube controls the charging and discharging of the capacitor; the control circuit converts the level state output by the charge and discharge circuit to generate a final output signal of an oscillator, and the output signal of the oscillator controls the on and off of a switching tube in the charge and discharge circuit; the circuit has simple structure and low power consumption, and can realize the output oscillation function; the current source mirrors current by a cascode current mirror, so that the generated currents I1 and I2 are high in stability, and the oscillation frequency of the OSC circuit is stable; the NMOS tube M13 is a decoupling capacitor, so that the power supply voltage can be stabilized, the generated current is stable, the stability of the oscillation frequency of the OSC circuit is improved, and the noise is low; the invention omits a comparator and a control part in the prior art, adopts a phase inverter, a two-input NOR gate and an RS trigger, and occupies small chip area. This application realizes keeping oscillation frequency through carrying out charge-discharge control to the current source to reduce the consumption, but its realization circuit is complicated, and just realizes oscillator frequency stabilization output through the steady voltage, and the discharge cycle consumption does not reduce, and in the time use, hardly does to the voltage stabilization of power, can not satisfy people to the improvement demand of oscillator.

Simplified CMOS grounded capacitor current controlled oscillator as shown in fig. 1, a timing capacitor C is alternately connected between the charging and discharging current sources. Control current IC is mirrored toM3 to provide a discharge current or mirrored to M5 to provide a charge current. Assuming that the switch S1 is closed initially, the capacitor is charged, and the current source M5 charges the capacitor C through the switch S1 until the voltage of the upper plate of the capacitor C exceeds an upper threshold voltage V_THThen the control circuit opens switch S1, closes switch S2, the capacitor starts to discharge, the capacitor discharges to ground through switch S2 and current source M3, when the voltage of the upper plate of the capacitor is lower than a lower threshold voltage V_TLAt this point, the discharge process ends, which is a complete clock cycle, and the operation is repeated.

According to the oscillator structure built by a standard CMOS relaxation oscillator, as shown in FIG. 2, a bias circuit provides a bias current which is mirrored to a PMOS tube to provide a charging current and mirrored to an NMOS tube to provide a discharging current, a capacitor is connected between a charging current source and a discharging current source, and assuming that the initial moment is a charging mode, the current source charges the capacitor, when the charging voltage exceeds a threshold voltage VH, a discharging switch S2 is opened, the capacitor starts to discharge, and when the voltage on the capacitor is lower than a threshold voltage VL, the capacitor starts to charge again, which is a complete clock cycle, and the operation is repeated. The charging and discharging period M5 is always in the on state, where the dynamic power consumption is (2I + 2I)/2I, so it can be seen that the current source is always in the on state during charging and discharging, so that the dynamic power consumption is increased.

Disclosure of Invention

Based on this, the first object of the present invention is to provide a circuit for reducing the power consumption of an oscillator, which reduces the power consumption of the discharge cycle by adding a switch in the path of the discharge current source, thereby reducing the dynamic power consumption of the oscillator.

Another object of the present invention is to provide a circuit for reducing power consumption of an oscillator, which is simple and convenient to implement, has low cost, and reduces power consumption under normal operation.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a circuit for reducing power consumption of an oscillator comprises a current source and a control switch, wherein the current mirror comprises M4, M5 and M7, and the circuit is characterized in that a current mirror M6 is additionally arranged in the current mirror, and the M6 is connected to the drain electrode of M5 through a switch S3 to provide bias current for a resistor. Since the switch S3 is turned off during discharging, the M6 is in an off state, thereby reducing dynamic power consumption.

Furthermore, the source of M8 is connected below the resistor connected to the drain of M5, the gate-drain of M8 is shorted, and a part of the reference voltage VREF is provided, and VREF is 2I × 2R + VDS8 in charging and VREF is I × 2R + VDS8 in discharging.

When S1 and S3 are turned on, a charging cycle is started, and when the capacitor top plate voltage reaches 2I × 2R + VDS8, the charging is ended, at this time, S1 and S3 are turned off, S2 is turned on, the capacitor is discharged to the ground, and when the capacitor top plate voltage reaches I × 2R + VDS8, the discharging is ended.

The current of M1 is mirrored to M2, M3, M3 as a discharge current source.

During charging: switches S1, S3 are on, S2 is off, and during discharging: s1, S3 are off, and S2 is on.

The implementation process comprises the following steps: and (3) charging process: switches S1, S3 are closed, switch S2 is open, and current source M7 charges the capacitor through switch S1; and (3) discharging: when switches S1, S3 are open and switch S2 is closed, the capacitor is discharged to ground through current source M3.

The current of the current sources M5 and M6 flows through the resistor during the charging period, only the current of the current source M5 flows through the resistor during the discharging period, and the current source M6 is not switched into the circuit due to the disconnection of the switch S3.

The oscillator circuit realized by the invention reduces the power consumption of the discharge period by adding the switch in the circuit of the discharge current source, thereby reducing the dynamic power consumption of the oscillator. The circuit is simple and convenient to realize, low in cost and low in power consumption under the condition of normal work.

Drawings

FIG. 1 is a block diagram of a standard CMOS relay oscillator implemented in the prior art.

Fig. 2 is a circuit diagram of a CMOS relay oscillator of a prior art implementation.

Fig. 3 is a block diagram of an oscillator embodying the present invention.

Fig. 4 is a diagram of simulation results of current source current implemented by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 3, an oscillator circuit implemented by the present invention is shown, which includes a current source and a control switch, wherein the IC current source flows through M1, and is mirrored to M2, and M4 and M2 are connected in series, and the current of M4 is mirrored to M5, M6, M7, M5 and M6 to provide bias current for the resistors. M6 in the current mirror is connected to the drain of M5 through a switch S3 to provide bias current for the resistor. Since the switch S3 is turned off during discharging, the M6 is in an off state, thereby reducing dynamic power consumption.

The resistor connected to the drain of the M5 is connected to the source of M8, and the gate of M8 is shorted to the drain to provide a part of the reference voltage VREF, which is equal to 2I × 2R + VDS8 during charging and equal to I × 2R + VDS8 during discharging.

The current of M1 is mirrored to M2, M3, M3 as a discharge current source.

The control circuit: the states of the switches S1, S2, S3 are controlled.

The current of the current sources M5 and M6 flows through the resistor during the charging period, only the current of the current source M5 flows through the resistor during the discharging period, and the current source M6 is not connected to the circuit because the switch S3 is turned off, so the dynamic power consumption of charging is

Dynamic power consumption during discharge of

The total dynamic power consumption here is

The dynamic power consumption is 2I before the switch S3 is not added, and other circuits are not changed, so that the power consumption is reduced.

The current simulation result of the current source M6 is shown in fig. 4, and it can be seen that when the switch S3 is turned on, the circuit is in a charging state, M6 works normally, and when the switch S3 is turned off, the circuit is in a discharging state, and the current of M6 is turned off, so that the design of reducing power consumption is realized.

Since the switch S3 is a PMOS transistor, the switch S3 is open when the gate voltage of the switch S3 is high, the path current of I2 is 0, and the switch S3 is closed when the gate voltage of the switch S3 is low, the path current of M6 conducts the current I.

In summary, the oscillator circuit realized by the invention reduces the power consumption of the discharge period by adding the switch in the circuit of the discharge current source, thereby reducing the dynamic power consumption of the oscillator. The circuit is simple and convenient to realize, low in cost and low in power consumption under the condition of normal work.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A circuit for reducing power consumption of an oscillator, wherein the oscillator is an on-chip RC oscillator, the circuit comprises a current source, a current mirror and a switch S3, the current mirror comprises CMOS transistors M4, M5 and M7, the source of the CMOS transistor M5 is connected with a power supply VS, and the drain of the CMOS transistor M5 is connected with one end of a resistor in the on-chip RC oscillator, the circuit is characterized in that a CMOS transistor M6 is additionally arranged in the current mirror, the source of the CMOS transistor M6 is connected with the power supply VS, the gate of the CMOS transistor M5 is connected with the gate of the CMOS transistor M5, and the drain of the CMOS transistor M5 is connected with the drain of the CMOS transistor M3 to provide bias current for the resistor in the.

2. The circuit for reducing power consumption of an oscillator according to claim 1, wherein the on-chip RC oscillator includes two resistors connected in series, a drain of the CMOS transistor M5 is connected to one end of the series resistor, one end of the series resistor outputs a reference voltage VREF, the other end of the series resistor is connected to a drain of the CMOS transistor M8, a gate and a drain of the CMOS transistor M8 are shorted, the CMOS transistor M8 provides a portion of the reference voltage VREF, VREF is 2I 2R + VDS8 during charging, VREF is I2R + VDS8 during discharging, where I is a current provided by a current source, 2R is a total resistance value of the series resistor in the on-chip RC oscillator, and VDS8 is a conduction voltage drop of the CMOS transistor M8.