CN108599745B - Single-capacitor duty ratio controllable oscillator - Google Patents

Single-capacitor duty ratio controllable oscillator Download PDF

Info

Publication number
CN108599745B
CN108599745B CN201810376609.7A CN201810376609A CN108599745B CN 108599745 B CN108599745 B CN 108599745B CN 201810376609 A CN201810376609 A CN 201810376609A CN 108599745 B CN108599745 B CN 108599745B
Authority
CN
China
Prior art keywords
terminal
nmos transistor
pmos transistor
transistor
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810376609.7A
Other languages
Chinese (zh)
Other versions
CN108599745A (en
Inventor
奚冬杰
罗永波
宣志斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 58 Research Institute
Original Assignee
CETC 58 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 58 Research Institute filed Critical CETC 58 Research Institute
Priority to CN201810376609.7A priority Critical patent/CN108599745B/en
Publication of CN108599745A publication Critical patent/CN108599745A/en
Application granted granted Critical
Publication of CN108599745B publication Critical patent/CN108599745B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • H03B5/1246—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance

Abstract

The invention discloses a single-capacitor duty ratio controllable oscillator, which comprises a first current source I1, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eight NMOS transistor, a first capacitor C1, a first resistor R1, a first inverter INV1, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a seventh PMOS transistor, wherein the first current source I1 is connected with the first current source I; the first capacitor C1 is a charge-discharge capacitor, the fourth NMOS tube and the sixth NMOS tube form a discharge branch, the third PMOS tube MP3 forms a charge branch, and the duty ratio of the output voltage can be controlled by adjusting the proportion of the mirror current sources of the third NMOS tube and the fourth NMOS tube. According to the invention, any required duty ratio can be obtained by charging and discharging the first capacitor C1 through two independent branches; the seventh NMOS tube and the eighth NMOS tube are used for accurately setting the charging and discharging upper and lower turning points of the circuit, so that the circuit complexity and the power consumption are reduced; meanwhile, the seventh NMOS tube and the eighth NMOS tube introduce hysteresis to the upper turning point and the lower turning point of the circuit, so that the anti-interference capability of the circuit is improved.

Description

Single-capacitor duty ratio controllable oscillator
Technical Field
The invention belongs to the technical field of electronics, relates to the technical field of analog integrated circuits, and particularly relates to a single-capacitor duty ratio controllable oscillator.
Background
Oscillators are key modules of clock and data recovery circuits used in IC design. The duty cycle of an oscillator is often dependent on the ratio of charging and discharging currents in the oscillator to the charging and discharging capacitors.
At present, the oscillator mostly determines to perform charging or discharging operation by comparing the voltage on the charging/discharging capacitor with the reference voltage, and this method has the following disadvantages: 1. either the charging current or the discharging current is generated by the switching tube, so that the output voltage duty ratio of the oscillator is too narrow, and the anti-interference capability is weak. 2. A comparator is needed in the circuit, so that the transient power consumption and the complexity of the circuit are increased.
Therefore, a single capacitance duty cycle controllable oscillator is needed.
Disclosure of Invention
In order to solve the technical problem, the invention provides a single-capacitor duty ratio controllable oscillator.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a single-capacitor duty ratio controllable oscillator, which comprises a first current source I1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first capacitor C1, a first resistor R1, a first inverter INV1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a seventh PMOS transistor MP 7;
the first capacitor C1 is a charge-discharge capacitor, the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 form a discharge branch, the third PMOS transistor MP3 forms a charge branch, and the duty ratio of the output voltage can be controlled by adjusting the proportion of mirror current sources of the third PMOS transistor MP3 and the fourth NMOS transistor MN 4;
the eighth NMOS transistor MN8 is matched with the second PMOS transistor MP2 and the fourth NMOS transistor MP4 to form a mirror current source, the proportion of the mirror current source is greater than that of the second PMOS transistor MP2, and the mirror current source is used for introducing a hysteresis effect when the first capacitor C1 is switched between a charging state and a discharging state, so that the anti-jamming capability of the circuit is improved;
the seventh PMOS transistor MP7 is used to ensure that the voltage at C is low when the circuit is initially powered up, preventing logic errors.
Preferably, the upper end of the first current source I1 is connected to the power supply, and the lower end thereof is connected to the drain terminal of the first NMOS transistor MN 1; the drain terminal of the first NMOS tube is connected with the gate terminal of the first NMOS tube, the gate terminal of the first NMOS tube is connected with the lower end of a first current source I1, and the source terminal (S) of the first NMOS tube is connected with GND; the drain terminal of the second NMOS transistor MN2 is connected to the drain terminal of the first PMOS transistor MP1, the gate terminal thereof is connected to the gate terminal of the first NMOS transistor MN1, and the source terminal (S) thereof is connected to GND; the drain end of the third NMOS tube MN3 is connected with the gate end thereof, the gate end thereof is connected with the gate end of the fourth NMOS tube MN4, and the source end (S) thereof is connected with GND; the drain end of the fourth NMOS transistor MN4 is connected with the source end (S) of the seventh NMOS transistor MN7, the gate end of the fourth NMOS transistor MN4 is connected with the drain end of the third NMOS transistor MN3, and the source end (S) of the fourth NMOS transistor MN is connected with GND; the drain terminal of the fifth NMOS transistor MN5 is connected to the drain terminal of the fifth PMOS transistor MP5, the gate terminal thereof is connected to the source terminal (S) of the seventh PMOS transistor MP7, and the source terminal (S) thereof is connected to GND; the drain terminal of the sixth NMOS transistor MN6 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the source terminal (S) of the sixth PMOS transistor MP6, and the source terminal (S) thereof is connected to the drain terminal of the fourth NMOS transistor MN 4; the drain terminal of the seventh NMOS transistor MN7 is connected to the drain terminal of the fourth PMOS transistor MP4, the gate terminal thereof is connected to the upper end of the first capacitor C1, and the source terminal (S) thereof is connected to the upper end of the first resistor R1; the drain terminal of the eighth NMOS transistor MN8 is connected to the drain terminal of the second PMOS transistor MP2, the gate terminal thereof is connected to the drain terminal of the fourth PMOS transistor MP4, and the source terminal (S) thereof is connected to the upper end of the first resistor R1; the upper end of the first capacitor C1 is connected with the drain terminal of the third PMOS tube MP3, and the lower end thereof is connected with GND; the upper end of the first resistor R1 is connected with the source end (S) of the seventh NMOS tube MN7, and the lower end thereof is connected with GND; the input end of the first inverter INV1 is connected to the drain end of the fifth PMOS transistor MP5, and the output end thereof is connected to VOUT; the drain terminal of the first PMOS transistor MP1 is connected to the drain terminal of the second NMOS transistor MN2, the gate terminal thereof is connected to the drain terminal thereof, and the source terminal (S) thereof is connected to VDD; the drain terminal of the second PMOS transistor MP2 is connected to the source terminal (S) of the sixth PMOS transistor MP6, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the third PMOS transistor MP3 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the fourth PMOS transistor MP4 is connected to the drain terminal of the seventh NMOS transistor MN7, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the fifth PMOS transistor MP5 is connected to the drain terminal of the fifth NMOS transistor MN5, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the sixth PMOS transistor MP6 is connected to the drain terminal of the third NMOS transistor MN3, the gate terminal thereof is connected to the upper end of the first resistor R1, and the source terminal (S) thereof is connected to the gate terminal of the sixth NMOS transistor MN 6; the drain terminal of the seventh PMOS transistor MP7 is connected to GND, the gate terminal thereof is connected to the drain terminal of the second PMOS transistor MP2, and the source terminal (S) thereof is connected to the gate terminal of the fifth NMOS transistor MN 5.
Preferably, the voltage V at the upper end of the first capacitor C1C1And a voltage V at the upper end A of R1AWhen the circuit is switched to the charge-discharge state, the circuit is suddenly changed through the eighth NMOS transistor MN 8.
Preferably, in the charging state, the voltage V at the upper end of the first capacitor C1 is initiallyC1If the voltage is low, the seventh NMOS transistor MN7 is turned off; then the voltage V at CCThe fourth PMOS transistor MP4 is pulled high, the eighth NMOS transistor MN8 is turned on, and the current flowing through the resistor R1 is IMP2。
Preferably, at the beginning of the discharge phase, the voltage V at CCWhen the voltage is low, the eighth NMOS transistor MN8 is turned off, and the current flowing through the resistor R1 is IMP4。
The invention has the following beneficial effects: according to the invention, any required duty ratio can be obtained by charging and discharging the first capacitor C1 through two independent branches; the charging and discharging upper and lower turning points of the circuit are accurately set through the seventh NMOS tube MN7 and the eighth NMOS tube MN8, so that the circuit complexity and the power consumption are reduced; meanwhile, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 introduce hysteresis to the upper and lower turning points of the circuit, so that the anti-interference capability of the circuit is improved.
Drawings
Fig. 1 is a schematic diagram of an oscillator circuit according to the present invention.
Fig. 2 is a waveform diagram of a key node of the oscillator circuit of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
In order to achieve the object of the present invention, as shown in fig. 1, in one embodiment of the present invention, a single-capacitor duty ratio controllable oscillator is provided, including a first current source I1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first capacitor C1, a first resistor R1, a first inverter INV1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP 7;
the first capacitor C1 is a charge-discharge capacitor, the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 form a discharge branch, the third PMOS transistor MP3 forms a charge branch, and the duty ratio of the output voltage can be controlled by adjusting the proportion of mirror current sources of the third PMOS transistor MP3 and the fourth NMOS transistor MN 4;
the eighth NMOS transistor MN8 is matched with the second PMOS transistor MP2 and the fourth NMOS transistor MP4 to form a mirror current source, the proportion of the mirror current source is greater than that of the second PMOS transistor MP2, and the mirror current source is used for introducing a hysteresis effect when the first capacitor C1 is switched between a charging state and a discharging state, so that the anti-jamming capability of the circuit is improved;
the seventh PMOS transistor MP7 is used to ensure that the voltage at C is low when the circuit is initially powered up, preventing logic errors.
As shown in fig. 1, the first current source I1 has its upper end connected to the power supply and its lower end connected to the drain of the first NMOS transistor MN 1; the drain terminal of the first NMOS tube is connected with the gate terminal of the first NMOS tube, the gate terminal of the first NMOS tube is connected with the lower end of a first current source I1, and the source terminal (S) of the first NMOS tube is connected with GND; the drain terminal of the second NMOS transistor MN2 is connected to the drain terminal of the first PMOS transistor MP1, the gate terminal thereof is connected to the gate terminal of the first NMOS transistor MN1, and the source terminal (S) thereof is connected to GND; the drain end of the third NMOS tube MN3 is connected with the gate end thereof, the gate end thereof is connected with the gate end of the fourth NMOS tube MN4, and the source end (S) thereof is connected with GND; the drain end of the fourth NMOS transistor MN4 is connected with the source end (S) of the seventh NMOS transistor MN7, the gate end of the fourth NMOS transistor MN4 is connected with the drain end of the third NMOS transistor MN3, and the source end (S) of the fourth NMOS transistor MN is connected with GND; the drain terminal of the fifth NMOS transistor MN5 is connected to the drain terminal of the fifth PMOS transistor MP5, the gate terminal thereof is connected to the source terminal (S) of the seventh PMOS transistor MP7, and the source terminal (S) thereof is connected to GND; the drain terminal of the sixth NMOS transistor MN6 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the source terminal (S) of the sixth PMOS transistor MP6, and the source terminal (S) thereof is connected to the drain terminal of the fourth NMOS transistor MN 4; the drain terminal of the seventh NMOS transistor MN7 is connected to the drain terminal of the fourth PMOS transistor MP4, the gate terminal thereof is connected to the upper end of the first capacitor C1, and the source terminal (S) thereof is connected to the upper end of the first resistor R1; the drain terminal of the eighth NMOS transistor MN8 is connected to the drain terminal of the second PMOS transistor MP2, the gate terminal thereof is connected to the drain terminal of the fourth PMOS transistor MP4, and the source terminal (S) thereof is connected to the upper end of the first resistor R1; the upper end of the first capacitor C1 is connected with the drain terminal of the third PMOS tube MP3, and the lower end thereof is connected with GND; the upper end of the first resistor R1 is connected with the source end (S) of the seventh NMOS tube MN7, and the lower end thereof is connected with GND; the input end of the first inverter INV1 is connected to the drain end of the fifth PMOS transistor MP5, and the output end thereof is connected to VOUT; the drain terminal of the first PMOS transistor MP1 is connected to the drain terminal of the second NMOS transistor MN2, the gate terminal thereof is connected to the drain terminal thereof, and the source terminal (S) thereof is connected to VDD; the drain terminal of the second PMOS transistor MP2 is connected to the source terminal (S) of the sixth PMOS transistor MP6, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the third PMOS transistor MP3 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the fourth PMOS transistor MP4 is connected to the drain terminal of the seventh NMOS transistor MN7, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the fifth PMOS transistor MP5 is connected to the drain terminal of the fifth NMOS transistor MN5, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD; the drain terminal of the sixth PMOS transistor MP6 is connected to the drain terminal of the third NMOS transistor MN3, the gate terminal thereof is connected to the upper end of the first resistor R1, and the source terminal (S) thereof is connected to the gate terminal of the sixth NMOS transistor MN 6; the drain terminal of the seventh PMOS transistor MP7 is connected to GND, the gate terminal thereof is connected to the drain terminal of the second PMOS transistor MP2, and the source terminal (S) thereof is connected to the gate terminal of the fifth NMOS transistor MN 5.
FIG. 2 is a diagram illustrating waveforms of key nodes when the circuit of the present invention is operating normally. It can be seen from the figure that the voltage V at the upper end of the first capacitor C1C1And a voltage V at the upper end A of R1AWhen the circuit is switched to the charge-discharge state, the circuit is suddenly changed through the eighth NMOS transistor MN 8.
The working principle of the present invention is further explained as follows:
in the charging state, the voltage V at the upper end of the first capacitor C1 is initiallyC1If the voltage is low, the seventh NMOS transistor MN7 is turned off; then the voltage V at CCThe fourth PMOS transistor MP4 is pulled high, the eighth NMOS transistor MN8 is turned on, and the current flowing through the resistor R1 is IMP2。
Assuming that the MOS transistor is to be turned on, its gate-source voltage V is requiredgs≥Vth. Then the initial state of charge can be obtained:
VC1＝IMP4×R1+Vth(MN7) (1)
VA＝IMP2×R1 (2)
wherein IMP2Represents the current, V, flowing through the second PMOS transistor MP2th(MN7)Representing the threshold voltage of the seventh NMOS transistor MN 7.
The charging branch MP3 charges C1 with VC1The seventh NMOS transistor MN7 begins to turn on gradually, VC1The maximum value of (d) is:
VC1＝(IMP2+IMP4)×R1+Vth(MN7) (3)
at this time:
IMN7＝IMP2+IMP4 (4)
wherein IMP4Represents the current, I, flowing through the fourth PMOS transistor MP4MN7Representing the current flowing through the seventh NMOS transistor MN 7.
Then enters a discharge phase, VC1And begins to fall.
At the beginning of the discharge phase, the voltage V at CCWhen the voltage is low, the eighth NMOS transistor MN8 is turned off, and the current flowing through the resistor R1 is IMP4。
The voltage at point a in the discharge phase is therefore approximately maintained as:
VA＝IMP4×R1 (5)
the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 of the discharge branch discharge the first capacitor C1 when V isC1When the NMOS transistor MN7 is gradually turned off, VC1The minimum value of (d) is:
VC1＝IMP4×R1+Vth(MN7) (6)
at this time:
IMN7＝IMP4 (7)
then enters a charging phase, VC1And starts to rise.
Repeating the first and second processes to obtain the required oscillation waveform.
For charging time t1Comprises the following steps:
Figure GDA0003200741790000061
for discharge time t2Comprises the following steps:
Figure GDA0003200741790000062
for duty cycle D there are:
Figure GDA0003200741790000063
in summary, the following steps: 1. according to the invention, the first capacitor C1 is charged and discharged by using two independent branches (the third PMOS transistor MP3 of the charging branch, the fourth NMOS transistor MN4 of the discharging branch and the sixth NMOS transistor MN6), so that any required duty ratio can be obtained. 2. Through seventh NMOS pipe MN7 and eighth NMOS pipe MN8, the upper and lower upset point of circuit charge-discharge has accurately been set up, has reduced circuit complexity and consumption. Meanwhile, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 introduce hysteresis to the upper and lower turning points of the circuit, so that the anti-interference capability of the circuit is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.

Claims (4)

1. The single-capacitor duty ratio controllable oscillator is characterized by comprising a first current source I1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first capacitor C1, a first resistor R1, a first inverter INV1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a seventh PMOS transistor MP 7;
the first capacitor C1 is a charge-discharge capacitor, the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 form a discharge branch, the third PMOS transistor MP3 forms a charge branch, and the duty ratio of the output voltage can be controlled by adjusting the proportion of mirror current sources of the third PMOS transistor MP3 and the fourth NMOS transistor MN 4;
the eighth NMOS transistor MN8 is matched with the second PMOS transistor MP2 and the fourth NMOS transistor MP4 to form a mirror current source, the proportion of the mirror current source is greater than that of the second PMOS transistor MP2, and the mirror current source is used for introducing a hysteresis effect when the first capacitor C1 is switched between a charging state and a discharging state, so that the anti-jamming capability of the circuit is improved;
the seventh PMOS transistor MP7 is used to ensure that the voltage at C is low when the circuit is initially powered on, to prevent logic errors, where C is the connection between the source terminal (S) of the seventh PMOS transistor MP7 and the gate terminal of the eighth NMOS transistor MN 8;
the upper end of the first current source I1 is connected with a power supply, and the lower end thereof is connected with the drain end of a first NMOS transistor MN 1;
the drain terminal of the first NMOS transistor MN1 is connected to the gate terminal thereof, the gate terminal thereof is connected to the lower terminal of the first current source I1, and the source terminal (S) thereof is connected to GND;
the drain terminal of the second NMOS transistor MN2 is connected to the source terminal (S) of the first PMOS transistor MP1, the gate terminal thereof is connected to the gate terminal of the first NMOS transistor MN1, and the source terminal (S) thereof is connected to GND;
the drain end of the third NMOS tube MN3 is connected with the gate end thereof, the gate end thereof is connected with the gate end of the fourth NMOS tube MN4, and the source end (S) thereof is connected with GND;
the drain terminal of the fourth NMOS transistor MN4 is connected with the source terminal (S) of the sixth NMOS transistor MN6, the gate terminal of the fourth NMOS transistor MN4 is connected with the drain terminal of the third NMOS transistor MN3, and the source terminal (S) of the fourth NMOS transistor MN is connected with GND;
the drain terminal of the fifth NMOS transistor MN5 is connected to the drain terminal of the fifth PMOS transistor MP5, the gate terminal thereof is connected to the source terminal (S) of the seventh PMOS transistor MP7, and the source terminal (S) thereof is connected to GND;
the drain terminal of the sixth NMOS transistor MN6 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the source terminal (S) of the sixth PMOS transistor MP6, and the source terminal (S) thereof is connected to the drain terminal of the fourth NMOS transistor MN 4;
the drain terminal of the seventh NMOS transistor MN7 is connected to the drain terminal of the fourth PMOS transistor MP4, the gate terminal thereof is connected to the upper end of the first capacitor C1, and the source terminal (S) thereof is connected to the upper end of the first resistor R1;
the drain terminal of the eighth NMOS transistor MN8 is connected to the drain terminal of the second PMOS transistor MP2, the gate terminal thereof is connected to the drain terminal of the fourth PMOS transistor MP4, and the source terminal (S) thereof is connected to the upper end of the first resistor R1;
the upper end of the first capacitor C1 is connected with the drain terminal of the third PMOS tube MP3, and the lower end thereof is connected with GND;
the upper end of the first resistor R1 is connected with the source end (S) of the seventh NMOS tube MN7, and the lower end thereof is connected with GND;
the input end of the first inverter INV1 is connected to the drain end of the fifth PMOS transistor MP5, and the output end thereof is connected to VOUT;
the source end (S) of the first PMOS tube MP1 is connected with the drain end of the second NMOS tube MN2, the grid end thereof is connected with the source end (S) thereof, and the drain end thereof is connected with VDD;
the drain terminal of the second PMOS transistor MP2 is connected to the source terminal (S) of the sixth PMOS transistor MP6, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD;
the drain terminal of the third PMOS transistor MP3 is connected to the upper end of the first capacitor C1, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD;
the drain terminal of the fourth PMOS transistor MP4 is connected to the drain terminal of the seventh NMOS transistor MN7, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD;
the drain terminal of the fifth PMOS transistor MP5 is connected to the drain terminal of the fifth NMOS transistor MN5, the gate terminal thereof is connected to the gate terminal of the first PMOS transistor MP1, and the source terminal (S) thereof is connected to VDD;
the drain terminal of the sixth PMOS transistor MP6 is connected to the drain terminal of the third NMOS transistor MN3, the gate terminal thereof is connected to the upper end of the first resistor R1, and the source terminal (S) thereof is connected to the gate terminal of the sixth NMOS transistor MN 6;
the drain terminal of the seventh PMOS transistor MP7 is connected to GND, the gate terminal thereof is connected to the drain terminal of the second PMOS transistor MP2, and the source terminal (S) thereof is connected to the gate terminal of the fifth NMOS transistor MN 5.
2. The single-capacitor duty-cycle controllable oscillator as claimed in claim 1, wherein the voltage V at the upper end of the first capacitor C1C1And a voltage V at the connection A of the upper end of the R1 and the source end (S) of the eighth NMOS tube MN8AWhen the circuit is switched to the charge-discharge state, the circuit is suddenly changed through the eighth NMOS transistor MN 8.
3. The single-capacitor duty-cycle controllable oscillator as claimed in claim 2, wherein in the charging state, the voltage V at the upper end of the initial first capacitor C1C1If the voltage is low, the seventh NMOS transistor MN7 is turned off; then the voltage V at CCThe fourth PMOS transistor MP4 is pulled high, the eighth NMOS transistor MN8 is turned on, and the current flowing through the resistor R1 is IMP2。
4. The single capacitor duty cycle controlled oscillator of claim 3, wherein at the beginning of the discharge phase, the voltage V at C isCWhen the voltage is low, the eighth NMOS transistor MN8 is turned off, and the current flowing through the resistor R1 is IMP4。
CN201810376609.7A 2018-04-25 2018-04-25 Single-capacitor duty ratio controllable oscillator Active CN108599745B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810376609.7A CN108599745B (en) 2018-04-25 2018-04-25 Single-capacitor duty ratio controllable oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810376609.7A CN108599745B (en) 2018-04-25 2018-04-25 Single-capacitor duty ratio controllable oscillator

Publications (2)

Publication Number Publication Date
CN108599745A CN108599745A (en) 2018-09-28
CN108599745B true CN108599745B (en) 2022-01-25

Family

ID=63609664

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810376609.7A Active CN108599745B (en) 2018-04-25 2018-04-25 Single-capacitor duty ratio controllable oscillator

Country Status (1)

Country Link
CN (1) CN108599745B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110190814A (en) * 2019-06-04 2019-08-30 中国电子科技集团公司第二十四研究所 A kind of oscillating circuit and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324912A (en) * 2011-08-13 2012-01-18 中科芯集成电路股份有限公司 Current control oscillator
CN102594299A (en) * 2012-02-03 2012-07-18 深圳创维－Rgb电子有限公司 Square-wave generator circuit
CN104901652A (en) * 2015-06-24 2015-09-09 深圳市富满电子集团股份有限公司 Oscillator circuit precisely controlled in duty ratio
CN104124921B (en) * 2014-07-02 2017-02-15 浙江大学 Current mode comparator based low voltage low power consumption CMOS (Complementary Metal Oxide Semiconductors) relaxation oscillator and method
CN107276566A (en) * 2016-04-07 2017-10-20 中芯国际集成电路制造(上海)有限公司 Annular oscillation circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103856186B (en) * 2012-12-05 2016-12-21 戴泺格集成电路（天津）有限公司 Duty ratio adjusting circuit and control method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324912A (en) * 2011-08-13 2012-01-18 中科芯集成电路股份有限公司 Current control oscillator
CN102594299A (en) * 2012-02-03 2012-07-18 深圳创维－Rgb电子有限公司 Square-wave generator circuit
CN104124921B (en) * 2014-07-02 2017-02-15 浙江大学 Current mode comparator based low voltage low power consumption CMOS (Complementary Metal Oxide Semiconductors) relaxation oscillator and method
CN104901652A (en) * 2015-06-24 2015-09-09 深圳市富满电子集团股份有限公司 Oscillator circuit precisely controlled in duty ratio
CN107276566A (en) * 2016-04-07 2017-10-20 中芯国际集成电路制造(上海)有限公司 Annular oscillation circuit

Also Published As

Publication number Publication date
CN108599745A (en) 2018-09-28

Similar Documents

Publication Publication Date Title
CN108390556B (en) Charge pump circuit
US7427889B2 (en) Voltage regulator outputting positive and negative voltages with the same offsets
EP3477860B1 (en) Comparator and relaxation oscillator
CN108563275B (en) Trimming switch circuit without static power consumption
CN110837267B (en) High-reliability power-on reset circuit
CN108667443B (en) Power-on reset circuit
CN108494384B (en) Trimming circuit for oscillator
CN108599745B (en) Single-capacitor duty ratio controllable oscillator
CN111934657B (en) Low-power-consumption power-on reset and power-off reset circuit
CN112583355A (en) High-precision relaxation oscillator
CN115173835A (en) Schmitt trigger circuit and related electronic circuit and electronic device
CN115800683A (en) Current detection circuit and DC-DC voltage reduction converter
CN115622548A (en) High-side NMOS floating drive circuit
CN115102384A (en) Soft start control circuit, control method thereof and power supply circuit
US10879858B2 (en) Oscillator circuit using comparator
KR100845780B1 (en) Circuit for Generating Clock of Semiconductor Memory Apparatus
JP2003283307A (en) Cr oscillation circuit
CN107565935B (en) Circuit for reducing power consumption of oscillator
TWI418137B (en) Voltage control oscillator
CN107070437B (en) Pulse width stabilizing circuit
CN111277249A (en) Low-power-consumption relaxation oscillator circuit
CN110739942A (en) kinds of power-on reset circuit
CN113258878B (en) Oscillator
CN112994671B (en) Low-power-consumption small-area high-precision power-on reset circuit
CN117254775B (en) Self-bias oscillating circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant