CN115800683A - Current detection circuit and DC-DC voltage reduction converter - Google Patents
Current detection circuit and DC-DC voltage reduction converter Download PDFInfo
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- CN115800683A CN115800683A CN202211559510.3A CN202211559510A CN115800683A CN 115800683 A CN115800683 A CN 115800683A CN 202211559510 A CN202211559510 A CN 202211559510A CN 115800683 A CN115800683 A CN 115800683A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a current detection circuit and a DC-DC buck converter, wherein the current detection circuit comprises: the bias current unit is used for generating a first bias current and transmitting the first bias current to a connection node of a main power tube and a secondary power tube of the DC-DC buck converter; the first starting unit is used for improving the establishing speed of the bias current unit; the comparator is used for comparing the voltage of the connection node with the ground voltage and outputting a control signal to the grid electrode of the secondary power tube. According to the device current detection circuit and the DC-DC buck converter, the bias current unit is quickly established through the first starting unit, and the comparator is quickly established through the second starting unit, so that the detection circuit can operate more efficiently. The circuit structure of the first starting unit and the second starting unit is simple, the performance of the circuit is greatly improved under the condition of small occupied area, and the cost of the chip is ignored.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a current detection circuit and a DC-DC buck converter.
Background
The BUCK converter is a kind of DC-DC converter, and the efficiency is an important measure of the performance. One important issue of the BUCK circuit in terms of energy loss is the return loss of the secondary power transistor. As shown in fig. 1, that is, when the inductor current of the sub power transistor M2 is reduced to zero under light load, the current on the output capacitor flows back to ground through the inductor and the sub power transistor M2, which results in low efficiency. At this time, current zero-crossing detection is performed on the connection node SW, and the general method is as follows: when the sub-power transistor M2 is turned on, the voltage of the connection node SW gradually increases from a negative voltage to 0V, and when the voltage of the connection node SW is greater than 0V, the sub-power transistor M2 is turned off. The common current zero-crossing detection mode is as follows: the accuracy and speed of the detection are particularly important for improving efficiency by flowing a bias current through a resistor and sinking it to the connection node SW, which turns off the secondary power transistor M2 by comparing the voltage at the connection node SW with the ground voltage.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a current detection circuit and a DC-DC buck converter, which can improve the response speed of a bias current unit and a comparator, further improve the efficiency of the whole system and improve the suppression capability of ground noise.
To achieve the above object, an embodiment of the present invention provides a current detection circuit for a DC-DC buck converter, where the DC-DC buck converter includes a primary power transistor and a secondary power transistor, a source of the primary power transistor and a drain of the secondary power transistor are connected to form a connection node SW, the drain of the primary power transistor is configured to receive a power supply voltage, a source of the secondary power transistor is connected to a ground voltage, and gates of the primary power transistor and the secondary power transistor are configured to receive a control signal, the current detection circuit including: the circuit comprises a bias current unit, a first starting unit and a comparator.
The bias current unit is used for generating a first bias current and transmitting the first bias current to the connection node SW, and comprises a first current mirror, a first MOS (metal oxide semiconductor) transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MP4, a first resistor R1 and a second resistor R2;
the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MP3, the source of the first MOS transistor MP1 and the source of the third MOS transistor MP3 are connected to a supply voltage AVDD, the gate of the second MOS transistor MP2 is connected to the gate of the fourth MOS transistor MP4, the source of the second MOS transistor MP2 is connected to the drain of the first MOS transistor MP1, the source of the fourth MOS transistor MP4 is connected to the drain of the third MOS transistor MP3, the first end of the first resistor R1 is connected to the drain of the second MOS transistor MP2 and the gate of the first MOS transistor MP1 to form a first node A1, the second end of the first resistor R1 is connected to the first current mirror and the gate of the second MOS transistor MP2 to form a second node A2, the first current mirror is simultaneously used for receiving an input current, the first end of the second resistor R2 is connected to the drain of the fourth MOS transistor MP4, and the second end of the second resistor R2 is connected to the connection node SW;
the first starting unit is connected with the first node A1 and the second node A2 and is used for increasing the speed of establishing the voltage on the first node A1 and the second node A2;
the comparator is used for comparing the voltage of the connection node SW with the ground voltage and outputting a control signal to the grid electrode of the secondary power tube.
In one or more embodiments of the present invention, the first start-up unit includes a first capacitor, a fifteenth MOS transistor, and a twenty-fifth MOS transistor, a first end of the first capacitor is connected to a power supply voltage, a second end of the first capacitor is connected to a drain of the twenty-fifth MOS transistor and a source of the fifteenth MOS transistor, the source of the twenty-fifth MOS transistor is connected to a ground voltage, the drain of the fifteenth MOS transistor is connected to the first node, and a gate of the fifteenth MOS transistor and a gate of the twenty-fifth MOS transistor are configured to receive the second control signal.
In one or more embodiments of the present invention, the first starting unit further includes a fourteenth MOS transistor and a sixteenth MOS transistor, a source of the fourteenth MOS transistor and a source of the sixteenth MOS transistor are connected to a power supply voltage, a drain of the fourteenth MOS transistor is connected to the second node, a drain of the sixteenth MOS transistor is connected to the first node, and a gate of the fourteenth MOS transistor and a gate of the sixteenth MOS transistor are configured to receive the third control signal.
In one or more embodiments of the present invention, the bias current unit further includes a twentieth MOS transistor, a drain of the twentieth MOS transistor is connected to the second node, a source of the twentieth MOS transistor is connected to the first current mirror, and a gate of the twentieth MOS transistor is configured to receive the first control signal.
In one or more embodiments of the present invention, the comparator includes a second current mirror, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a third current mirror, a twenty-fourth MOS transistor, a third resistor, a fourth resistor, and a fifth resistor;
the first end of the third resistor is connected with the second current mirror, the second end of the third resistor is connected with ground voltage, the source electrode of the tenth MOS tube is connected with the source electrode of the eleventh MOS tube and is simultaneously connected with the second current mirror, the grid electrode of the tenth MOS tube is connected with a connection node, the grid electrode of the eleventh MOS tube is connected with the ground voltage, the first end of the fourth resistor is connected with the drain electrode of the tenth MOS tube, the second end of the fourth resistor is connected with the ground voltage, the first end of the fifth resistor is connected with the drain electrode of the eleventh MOS tube, the second end of the fifth resistor is connected with the ground voltage, the source electrode of the twelfth MOS tube and the source electrode of the thirteenth MOS tube are connected with the second current mirror, the grid electrode of the twelfth MOS tube is connected with the drain electrode of the eleventh MOS tube, the grid electrode of the thirteenth MOS tube is connected with the drain electrode of the tenth MOS tube, the drain electrode of the twelfth MOS tube and the drain electrode of the thirteenth MOS tube are connected with the third current mirror, the drain electrode of the twenty-fourth MOS tube is connected with the drain electrode of the twenty-fourth MOS tube, and the drain electrode of the twenty-fourth MOS tube are connected with the drain electrode of the twenty-ground voltage.
In one or more embodiments of the present invention, the comparator further includes a twenty-first MOS transistor, a drain of the twenty-first MOS transistor is connected to the second terminal of the third resistor, a gate of the twenty-first MOS transistor is configured to receive the first control signal, and a source of the twenty-first MOS transistor is connected to the ground voltage.
In one or more embodiments of the present invention, the current detection circuit further includes a second start-up unit connected to the gate of each MOS transistor of the second current mirror, where the second start-up unit is configured to increase the setup speed of the comparator.
In one or more embodiments of the present invention, the second starting unit includes a second capacitor, a seventeenth MOS transistor, and a twenty-sixth MOS transistor, a first end of the second capacitor is connected to a power supply voltage, a source of the seventeenth MOS transistor and a drain of the twenty-sixth MOS transistor are connected to a second end of the second capacitor, a gate of the seventeenth MOS transistor and a gate of the twenty-sixth MOS transistor are configured to receive a second control signal, a source of the twenty-sixth MOS transistor is connected to a ground voltage, and a drain of the seventeenth MOS transistor is connected to a gate of each MOS transistor of the second current mirror.
In one or more embodiments of the present invention, the comparator further includes a seventh MOS transistor, a source of the seventh MOS transistor is connected to the power supply voltage, a gate of the seventh MOS transistor is configured to receive the third control voltage, and a drain of the seventh MOS transistor is connected to a gate of each MOS transistor of the second current mirror.
The invention also discloses a DC-DC buck converter, comprising: the current detection circuit.
Compared with the prior art, according to the current detection circuit and the DC-DC buck converter provided by the embodiment of the invention, the bias current unit is quickly established through the first starting unit, and the comparator is quickly established through the second starting unit, so that the detection circuit can operate more efficiently. The circuit structure of the first starting unit and the second starting unit is simple, the performance of the circuit is greatly improved under the condition that the occupied area is small, and the cost of the chip is ignored.
Drawings
Fig. 1 is a circuit schematic diagram of a DC-DC converter in the prior art.
Fig. 2 is a circuit schematic of a current sensing circuit according to an embodiment of the present invention.
Fig. 3 is a circuit schematic of a signal generating circuit according to an embodiment of the present invention.
Fig. 4 is a first waveform diagram of control signals and nodes according to an embodiment of the invention.
FIG. 5 is a second waveform diagram of control signals and nodes according to an embodiment of the invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations such as "comprises" or "comprising", etc., will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 1, the DC-DC buck converter includes a main power transistor M1 and a sub power transistor M2. The source electrode of the main power tube M1 is connected with the drain electrode of the secondary power tube M2 to form a connection node SW, the drain electrode of the main power tube M1 is used for receiving a power supply voltage AVDD, the source electrode of the secondary power tube M2 is connected with a ground voltage, the grid electrode of the main power tube M1 is used for receiving a control signal K1, and the grid electrode of the secondary power tube M2 is used for receiving the control signal K2.
As shown in fig. 2, a current detection circuit for a DC-DC buck converter includes: a bias current unit 10, a first start-up unit 20, a comparator 30 and a second start-up unit 40.
The bias current unit 10 is configured to generate a first bias current I1 and supply the first bias current I1 to the node SW.
As shown in fig. 2, the bias current unit 10 includes a first current mirror, a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MP4, a twentieth MOS transistor MN3, a first resistor R1, and a second resistor R2.
Specifically, the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MP3, the source of the first MOS transistor MP1 and the source of the third MOS transistor MP3 are connected to the power supply voltage AVDD, the gate of the second MOS transistor MP2 is connected to the gate of the fourth MOS transistor MP4, the source of the second MOS transistor MP2 is connected to the drain of the first MOS transistor MP1, the source of the fourth MOS transistor MP4 is connected to the drain of the third MOS transistor MP3, the first end of the first resistor R1 is connected to the drain of the second MOS transistor MP2 and the gate of the first MOS transistor MP1 to form a first node A1, the second end of the first resistor R1 is connected to the drain of the twentieth MOS transistor MN3 and the gate of the second MOS transistor MP2 to form a second node A2, the source of the twentieth MOS transistor MN3 is connected to the first current mirror, and the gate of the twentieth MOS transistor MN3 is configured to receive the first control signal s1. The first current mirror is also used for receiving input current, a first end of the second resistor R2 is connected with the drain electrode of the fourth MOS transistor MP4, and a second end of the second resistor R2 is connected with the connection node SW.
In addition, the first current mirror includes an eighteenth MOS transistor MN1 and a nineteenth MOS transistor MN2. The gate of the eighteenth MOS transistor MN1 is connected to the drain and is also connected to the constant current source a to receive the input current I0. The grid electrode of the eighteenth MOS tube MN1 is connected with the grid electrode of the nineteenth MOS tube MN2, and the source electrode of the eighteenth MOS tube MN1 and the source electrode of the nineteenth MOS tube MN2 are connected with the ground voltage.
In the present embodiment, the first enabling unit 20 is connected to the first node A1 and the second node A2, and the first enabling unit 20 is configured to increase the speed of establishing the voltages at the first node A1 and the second node A2.
As shown in fig. 2, the first start unit 20 includes a first capacitor C1, a fourteenth MOS transistor MP14, a fifteenth MOS transistor MP15, a sixteenth MOS transistor MP16, and a twenty-fifth MOS transistor MN8.
A first end of the first capacitor C1 is connected to the power supply voltage AVDD, and a second end of the first capacitor C1 is connected to a drain of the twenty-fifth MOS transistor MN8 and a source of the fifteenth MOS transistor MP 15. The source of the twenty-fifth MOS transistor MN8 is connected to the ground voltage, the drain of the fifteenth MOS transistor MP15 is connected to the first node A1, and the gate of the fifteenth MOS transistor MP15 and the gate of the twenty-fifth MOS transistor MN8 are configured to receive the second control signal s2.
A source of the fourteenth MOS transistor MP14 and a source of the sixteenth MOS transistor MP16 are connected to the power supply voltage AVDD, a drain of the fourteenth MOS transistor MP14 is connected to the second node A2, a drain of the sixteenth MOS transistor MP16 is connected to the first node A1, and a gate of the fourteenth MOS transistor MP14 and a gate of the sixteenth MOS transistor MP16 are configured to receive the third control signal s3.
In the present embodiment, the comparator 30 is used for comparing the voltage of the connection node SW with the ground voltage and outputting the control signal K2 to the gate of the secondary power transistor M2.
As shown in fig. 2, the comparator 30 includes a second current mirror, a seventh MOS transistor MP7, a tenth MOS transistor MP10, an eleventh MOS transistor MP11, a twelfth MOS transistor MP12, a thirteenth MOS transistor MP13, a third current mirror, a twenty-first MOS transistor MN4, a twenty-fourteen MOS transistor MN7, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.
The second current mirror is used to provide a plurality of bias currents to the comparator 30. The second current mirror includes a plurality of MOS transistors connected in common, and specifically, the second current mirror includes a fifth MOS transistor MP5, a sixth MOS transistor MP6, an eighth MOS transistor MP8, and a ninth MOS transistor MP9. The gate and the drain of the fifth MOS transistor MP5 are connected, and the sources of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the eighth MOS transistor MP8 and the ninth MOS transistor MP9 are connected and connected to the power supply voltage AVDD.
The first end of the third resistor R3 is connected with the drain electrode of the fifth MOS transistor MP5, the second end of the third resistor R3 is connected with the drain electrode of the twenty-first MOS transistor MN4, the grid electrode of the twenty-first MOS transistor MN4 is used for receiving the first control signal s1, and the source electrode of the twenty-first MOS transistor MN4 is connected with the ground voltage.
A source of the tenth MOS transistor MP10 is connected to a source of the eleventh MOS transistor MP11 and is also connected to a drain of the sixth MOS transistor MP6 of the second current mirror, a gate of the tenth MOS transistor MP10 is connected to the connection node SW, and a gate of the eleventh MOS transistor MP11 is connected to the ground voltage. A first terminal of the fourth resistor R4 is connected to the drain of the tenth MOS transistor MP10, a second terminal of the fourth resistor R4 is connected to the ground voltage, a first terminal of the fifth resistor R5 is connected to the drain of the eleventh MOS transistor MP11, and a second terminal of the fifth resistor R5 is connected to the ground voltage.
The source electrode of the twelfth MOS transistor MP12 is connected to the source electrode of the thirteenth MOS transistor MP13 and is simultaneously connected to the drain electrode of the eighth MOS transistor MP8 of the second current mirror, the gate electrode of the twelfth MOS transistor MP12 is connected to the drain electrode of the eleventh MOS transistor MP11, the gate electrode of the thirteenth MOS transistor MP13 is connected to the drain electrode of the tenth MOS transistor MP10, and the drain electrode of the twelfth MOS transistor MP12 and the drain electrode of the thirteenth MOS transistor MP13 are both connected to the third current mirror. The third current mirror comprises a twelfth MOS tube MN5 and a twenty-third MOS tube MN6. The gate of the twenty-second MOS transistor MN5 is connected to the gate of the twenty-third MOS transistor MN6, the gate and the drain of the twenty-second MOS transistor MN5 are connected to each other and are connected to the drain of the twelfth MOS transistor MP12, and the drain of the twenty-third MOS transistor MN6 is connected to the gate of the twenty-fourth MOS transistor MN7 and the drain of the thirteenth MOS transistor MP 13. The source electrode of the twenty-second MOS transistor MN5 and the source electrode of the twenty-third MOS transistor MN6 are connected to a ground voltage.
The drain of the twenty-fourth MOS transistor MN7 is connected to the drain of the ninth MOS transistor MP9 of the second current mirror, the gate of the twenty-fourth MOS transistor MN7 is connected to the drain of the thirteenth MOS transistor MP13, and the source of the twenty-fourth MOS transistor MN7 is connected to the ground voltage.
The source of the seventh MOS transistor MP7 is connected to the power supply voltage AVDD, the gate of the seventh MOS transistor MP7 is configured to receive the third control voltage s3, and the drain of the seventh MOS transistor MP7 is connected to the gates of the sixth MOS transistor MP6, the eighth MOS transistor MP8, and the ninth MOS transistor MP9 of the second current mirror.
In this embodiment, the second starting unit 40 is connected to the gate of each MOS transistor of the second current mirror, and the second starting unit 40 is configured to increase the speed of establishing the second current mirror.
As shown in fig. 2, the second start unit 40 includes a second capacitor C2, a seventeenth MOS transistor MP17, and a twenty-sixth MOS transistor MN9. A first end of the second capacitor C2 is connected to the power supply voltage AVDD, and a source of the seventeenth MOS transistor MP17 and a drain of the twenty-sixth MOS transistor MN9 are connected to a second end of the second capacitor C2. The gate of the seventeenth MOS transistor MP17 and the gate of the twenty sixth MOS transistor MN9 are configured to receive the second control signal s2, and the source of the twenty sixth MOS transistor MN9 is connected to the ground voltage. The drain of the seventeenth MOS transistor MP17 is connected to the gates of the sixth MOS transistor MP6, the eighth MOS transistor MP8, and the ninth MOS transistor MP9 of the second current mirror to form a third node A3.
As shown in fig. 3, the current detection circuit further includes a signal generation circuit 50. The signal generating circuit 50 includes a buffer 51 and an inverter 52. The buffer 51 is configured to receive the third control signal s3 and output the first control signal s1. The first control signal s1 is slightly delayed compared to the third control signal s3. The inverter 52 is used for receiving the first control signal s1 and delaying the output of the second control signal s2.
In this embodiment, the third control signal s3 is first inverted to a high level signal, the fourteenth MOS transistor MP14, the sixteenth MOS transistor MP16 and the seventh MOS transistor MP7 are all turned off, and at this time, the voltages of the first node A1, the second node A2 and the third node A3 are no longer controlled by the fourteenth MOS transistor MP14, the sixteenth MOS transistor MP16 and the seventh MOS transistor MP7 respectively and are released.
Next, the first control signal s1 is inverted to a high level signal, the twentieth MOS transistor MN3 and the twenty-first MOS transistor MN4 are both turned on, and the input bias voltage of the connection node SW and the bias voltage of the comparator 30 start to be established.
In addition, since the second control signal s2 is initially a high level signal, the twenty-fifth MOS transistor MN8 and the twenty-sixth MOS transistor MN9 are both turned on, and the first capacitor C1 and the second capacitor C2 perform charge storage based on the power supply voltage AVDD and the ground voltage. After the first control signal s1 is inverted to the high level signal, the voltages of the first node A1, the third node A3, and the second node A2 start to be slowly built up. When the second control signal s2 is inverted to a low level signal, the fifteenth MOS transistor MP15 and the seventeenth MOS transistor MP17 are both turned on, the charge stored by the first capacitor C1 at the initial time is C1 × AVDD, and at this time, all of the charges are released at the first node A1, a path is rapidly established between the power supply voltage AVDD, the first capacitor C1, and the first node A1 in a short time, the voltage at the first node A1 is rapidly pulled down, and the bias current unit 10 rapidly generates the first bias current I1. After the first node A1 is stably established, no current exists on the first capacitor C1, and normal operation is not affected. Similarly, the voltage at the third node A3 also changes as the voltage at the first node A1, so that the second current mirror also generates the bias current quickly, and the setup of the comparator 30 is accelerated.
The initial charge on the first capacitor C1 is C1 AVDD, and the stabilized charge on the first capacitor C1 is C1 (AVDD-V) A1 ) C1 is the capacitance of the first capacitor C1, AVDD is the voltage of the power supply voltage AVDD, V A1 Is the voltage of the first node A1. The amount of charge consumed on the first capacitor C1 is C1 x V A1 The time for establishing the voltage at the first node A1 is Δ T, and the sizes of the fifteenth MOS transistor MP15 and the first capacitor C1 are reasonably set to obtain the voltage at the first node A1
Δ I is the amount of change in the current across the first resistor R1. After the first node A1 and the second node A2 are quickly established, the first bias current I1 is established, and the voltage at the connection node SW is 0 when the sub-power transistor M2 is turned on and the sub-power transistor M2 reflows. Assuming that the internal resistance of the secondary power transistor M2 is Ron, and the current flowing from the ground voltage through the secondary power transistor M2 to the connection node SW is I, whether or not the backflow occurs can be determined based on Ron I = R2I 1, and R2 being the resistance value of the second resistor R2.
As can be seen from fig. 4 and 5, through the sequentially optimized control logic of the first control signal s1, the second control signal s2, and the third control signal s3, the voltage setting speed on the third node A3 and the first node A1 is within 10ns, and compared with a conventional detection circuit, the response speed is increased by more than ten times, so that the bias current unit and the comparator can be quickly set up, the detection sensitivity is provided, the circuit can operate more efficiently, and the efficiency of the whole chip is further provided.
The embodiment also discloses a DC-DC buck converter, which comprises the current detection circuit.
The embodiment also discloses a chip comprising the current detection circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A current detection circuit for a DC-DC buck converter, the DC-DC buck converter including a primary power transistor and a secondary power transistor, a source of the primary power transistor and a drain of the secondary power transistor being connected to form a connection node, the drain of the primary power transistor being configured to receive a supply voltage, the source of the secondary power transistor being connected to a ground voltage, and gates of the primary power transistor and the secondary power transistor being configured to receive a control signal, the current detection circuit comprising:
the bias current unit is used for generating a first bias current and transmitting the first bias current to a connection node, and comprises a first current mirror, a first MOS (metal oxide semiconductor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor and a second resistor;
the grid electrode of the first MOS tube is connected with the grid electrode of the third MOS tube, the source electrode of the first MOS tube and the source electrode of the third MOS tube are connected with a power supply voltage, the grid electrode of the second MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the source electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, the first end of the first resistor is connected with the drain electrode of the second MOS tube and the grid electrode of the first MOS tube to form a first node, the second end of the first resistor is connected with the first current mirror and the grid electrode of the second MOS tube to form a second node, the first current mirror is used for receiving input current at the same time, the first end of the second resistor is connected with the drain electrode of the fourth MOS tube, and the second end of the second resistor is connected with a connection node;
the first starting unit is connected with the first node and the second node and used for increasing the speed of establishing the voltage on the first node and the second node; and
and the comparator is used for comparing the voltage of the connection node with the ground voltage and outputting a control signal to the grid electrode of the secondary power tube.
2. The current detection circuit of claim 1, wherein the first start-up unit comprises a first capacitor, a fifteenth MOS transistor and a twenty-fifth MOS transistor, a first end of the first capacitor is connected to a power supply voltage, a second end of the first capacitor is connected to a drain of the twenty-fifth MOS transistor and a source of the fifteenth MOS transistor, the source of the twenty-fifth MOS transistor is connected to a ground voltage, the drain of the fifteenth MOS transistor is connected to the first node, and a gate of the fifteenth MOS transistor and a gate of the twenty-fifth MOS transistor are configured to receive the second control signal.
3. The current detection circuit of claim 2, wherein the first start-up unit further comprises a fourteenth MOS transistor and a sixteenth MOS transistor, a source of the fourteenth MOS transistor and a source of the sixteenth MOS transistor are connected to the power supply voltage, a drain of the fourteenth MOS transistor is connected to the second node, a drain of the sixteenth MOS transistor is connected to the first node, and a gate of the fourteenth MOS transistor and a gate of the sixteenth MOS transistor are configured to receive the third control signal.
4. The current detection circuit of claim 1, wherein the bias current unit further comprises a twentieth MOS transistor, a drain of the twentieth MOS transistor is connected to the second node, a source of the twentieth MOS transistor is connected to the first current mirror, and a gate of the twentieth MOS transistor is configured to receive the first control signal.
5. The current detection circuit of claim 1, wherein the comparator comprises a second current mirror, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a third current mirror, a twenty-fourth MOS transistor, a third resistor, a fourth resistor, and a fifth resistor;
the first end of the third resistor is connected with the second current mirror, the second end of the third resistor is connected with the ground voltage, the source electrode of the tenth MOS tube is connected with the source electrode of the eleventh MOS tube and is simultaneously connected with the second current mirror, the gate electrode of the tenth MOS tube is connected with the connection node, the gate electrode of the eleventh MOS tube is connected with the ground voltage, the first end of the fourth resistor is connected with the drain electrode of the tenth MOS tube, the second end of the fourth resistor is connected with the ground voltage, the first end of the fifth resistor is connected with the drain electrode of the eleventh MOS tube, the second end of the fifth resistor is connected with the ground voltage, the source electrode of the twelfth MOS tube and the source electrode of the thirteenth MOS tube are connected with the second current mirror, the gate electrode of the twelfth MOS tube is connected with the drain electrode of the eleventh MOS tube, the gate electrode of the thirteenth MOS tube is connected with the drain electrode of the tenth MOS tube, the drain electrode of the twelfth MOS tube and the drain electrode of the thirteenth MOS tube are both connected with the third current mirror, the drain electrode of the twenty-fourth MOS tube is connected with the drain electrode of the twenty-fourth MOS tube, and the drain electrode of the thirteenth MOS tube are connected with the ground voltage.
6. The current sensing circuit of claim 5, wherein the comparator further comprises a twenty-first MOS transistor, a drain of the twenty-first MOS transistor is connected to the second terminal of the third resistor, a gate of the twenty-first MOS transistor is configured to receive the first control signal, and a source of the twenty-first MOS transistor is connected to a ground voltage.
7. The current sensing circuit of claim 5, further comprising a second enable unit coupled to the gate of each MOS transistor of the second current mirror, the second enable unit configured to increase the settling speed of the comparator.
8. The current detection circuit according to claim 7, wherein the second start-up unit includes a second capacitor, a seventeenth MOS transistor and a twenty-sixth MOS transistor, a first end of the second capacitor is connected to a power supply voltage, a source of the seventeenth MOS transistor and a drain of the twenty-sixth MOS transistor are connected to a second end of the second capacitor, a gate of the seventeenth MOS transistor and a gate of the twenty-sixth MOS transistor are configured to receive the second control signal, a source of the twenty-sixth MOS transistor is connected to a ground voltage, and a drain of the seventeenth MOS transistor is connected to gates of the MOS transistors of the second current mirror.
9. The current sensing circuit of claim 5, wherein the comparator further comprises a seventh MOS transistor, a source of the seventh MOS transistor is connected to the supply voltage, a gate of the seventh MOS transistor is configured to receive the third control voltage, and a drain of the seventh MOS transistor is connected to the gates of the MOS transistors of the second current mirror.
10. A DC-DC buck converter, comprising: a current sensing circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211559510.3A CN115800683A (en) | 2022-12-06 | 2022-12-06 | Current detection circuit and DC-DC voltage reduction converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211559510.3A CN115800683A (en) | 2022-12-06 | 2022-12-06 | Current detection circuit and DC-DC voltage reduction converter |
Publications (1)
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| CN115800683A true CN115800683A (en) | 2023-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211559510.3A Pending CN115800683A (en) | 2022-12-06 | 2022-12-06 | Current detection circuit and DC-DC voltage reduction converter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117420347A (en) * | 2023-12-19 | 2024-01-19 | 西安航天民芯科技有限公司 | Zero-crossing current detection circuit of DC-DC converter |
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2022
- 2022-12-06 CN CN202211559510.3A patent/CN115800683A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117420347A (en) * | 2023-12-19 | 2024-01-19 | 西安航天民芯科技有限公司 | Zero-crossing current detection circuit of DC-DC converter |
| CN117420347B (en) * | 2023-12-19 | 2024-02-20 | 西安航天民芯科技有限公司 | Zero-crossing current detection circuit of DC-DC converter |
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