JP2011223130A - Comparison circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparison circuit in which a charging time of capacitance can be shortened easily without substantially increasing current consumption and circuit scale.SOLUTION: An output from a single-phase amplifier circuit 20, to which an output from a differential amplifier circuit 10 is input, is input to a clamp circuit 41 using a source follower consisting of an N channel MOS transistor MN5, and the charging time of the capacitance Cp can be shortened narrowing a necessary charging voltage width without providing a new constant voltage source, by limiting an input of the single-phase amplifier circuit 20 using the clamp circuit 41. Furthermore, since the input of the single-phase amplifier circuit 20 is limited depending on the output from the single-phase amplifier circuit 20, variation in a threshold voltage of the single-phase amplifier circuit 20 and influence of power supply voltage are negligible.

Description

  The present invention relates to a comparison circuit capable of shortening a response time to an input change.

  FIG. 7 shows a configuration of a conventional comparison circuit. This comparison circuit includes a differential amplifier circuit 10, a single-phase amplifier circuit 20, and a waveform shaping circuit 30. The differential amplifier circuit 10 includes a constant current source 11 for supplying a bias current Ib1, P channel MOS transistors MP1 and MP2 constituting a differential pair, and N channel MOS transistors MN1 and MN2 constituting a current mirror circuit. An output terminal of the differential amplifier circuit 10, which is a connection point between the P-channel MOS transistor MP2 and the N-channel MOS transistor MN2, supplies a current corresponding to the difference between the input voltages Vinp and Vinm input to the gates of the channel MOS transistors MP1 and MP2 respectively. Output from.

  The single-phase amplifier circuit 20 is composed of a series circuit in which a constant current source 21 for supplying a bias current Ib2 and an N-channel MOS transistor MN3 are connected in series, and the gate terminal of the N-channel MOS transistor MN3 is used as its input terminal. A connection point between the node 21 and the N-channel MOS transistor MN3 is used as an output terminal. The input terminal of the single phase amplifier circuit 20 is connected to the output terminal of the differential amplifier circuit 10. The single-phase amplifier circuit 20 generates a signal Vo2 obtained by amplifying the output voltage Vo1 of the differential amplifier circuit 10 and inputs the signal Vo2 to the waveform shaping circuit 30 at the next stage. The waveform shaping circuit 30 includes a P-channel MOS transistor MP3 and an N-channel MOS transistor MN4 connected in series. The waveform shaping circuit 30 further amplifies the output signal Vo2 of the single-phase amplifier circuit 20 and shapes it into a binary signal Vo3. The comparison circuit is supplied with power of a high potential side potential VDD and a low potential side potential 0 V (ground potential).

  Note that the capacitor Cp is a sum of all the capacitors (such as the gate capacitance of the N-channel MOS transistor MN3 and other parasitic capacitances) associated with the line connecting the output of the differential amplifier circuit 10 and the input of the single-phase amplifier circuit 20. is there.

  FIG. 8 shows a transient response operation when the relationship between the two input signals in the comparison circuit changes from Vinp << Vinm to Vinp> Vinm. In the initial state of Vinp << Vinm, the output voltage Vo1 of the differential amplifier circuit 10 is the lower limit of 0 V (ground potential). Assuming that the transconductance of the differential amplifier circuit 10 is gm, a current of (Vinp−Vinm) · gm is output from the output terminal of the differential amplifier circuit 10 from the time ta when Vinp> Vinm is changed. Charge the battery. The charging voltage of the capacitor Cp is the output voltage Vo1 of the differential amplifier circuit 10, and this output voltage Vo1 increases as the charging of the capacitor Cp proceeds. When voltage Vo1 exceeds threshold voltage Vth1 of N-channel MOS transistor MN3 at time tb and enters the operation region of single-phase amplifier circuit 20, output signal Vo2 of single-phase amplifier circuit 20 starts to decrease. When the output signal Vo2 of the single-phase amplifier circuit 20 becomes equal to or lower than the threshold voltage Vth2 of the waveform shaping circuit 30 at time tc, the output Vo3 of the waveform shaping circuit 30 that is the output of the comparison circuit changes from L (Low) level to H (High) level. Invert.

Here, there is a problem that a delay (tc−ta) mainly due to the charging time of the capacitor Cp occurs until the output Vo3 of the comparison circuit changes to the H level after changing from Vinp> Vinm.

  To solve this problem, an amplifier has been proposed in which the bias current of the comparison circuit is switched depending on the ratio of the current flowing through the differential pair of the differential amplifier circuit, and the bias current is increased when the input voltage changes. (For example, refer to Patent Document 1). If the bias current of the differential amplifier circuit is increased, the charging time of the capacitor Cp can be shortened.

  In addition, a comparator circuit has been proposed in which a clamp circuit is connected to the output terminal of the differential amplifier circuit to limit the voltage change range corresponding to the voltage Vo1 in FIG. 7 (see, for example, Patent Document 2). If the voltage change range corresponding to the voltage Vo1 is limited, the value of the charge / discharge voltage of the capacitor Cp required until the output of the comparison circuit is inverted can be reduced, and the charging time of the capacitor Cp can be shortened. it can. The clamp circuit disclosed in Patent Document 2 will be further described. FIG. 9 shows an embodiment of the clamp circuit disclosed in Patent Document 2. In FIG. 9, a clamp circuit composed of diodes D <b> 1 and D <b> 2 is connected to the line of the output voltage Vo <b> 1 of the differential amplifier circuit 10. The anode of the diode D1 is connected to the output voltage Vo1, and the cathode is connected to the constant voltage V1. The anode of the diode D2 is connected to the constant voltage V2, and the cathode is connected to the output voltage Vo1. If the forward voltages of the diodes D1 and D2 are ignored, the change range of the output voltage Vo1 is limited to V2 to V1 by this configuration.

  FIG. 10 shows another embodiment of the clamp circuit disclosed in Patent Document 2. In FIG. 10, a clamp circuit comprising a PNP transistor Tr1 is connected to the line of the output voltage Vo1 of the differential amplifier circuit 10. A constant voltage Vr is applied to the base of the PNP transistor Tr1, and if the base-emitter voltage of the PNP transistor Tr1 is ignored, the maximum voltage of the output voltage Vo1 is thereby limited to Vr.

JP 2006-174035 A JP 61-16612 (Figs. 2 and 4)

  The amplifier of Patent Document 1 increases the bias current to shorten the charge / discharge time of the capacitor Cp. However, if the charge voltage required to invert the output Vo3 of the waveform shaping circuit 30 is high, the speed is increased. However, it is necessary to increase the increase amount of the bias current, and there is a problem that the current consumption increases. Further, if the bias current is increased only when the input signal is switched, there is a problem that an appropriate circuit scale is required.

  The comparator of Patent Document 2 is to reduce the charge / discharge voltage width by shortening the charge / discharge voltage width by setting the initial charge / discharge value of the capacitor Cp to a non-zero value. However, the constant voltage V1, V2, or Vr is reduced. It is necessary to provide a circuit to be generated, which causes a problem of an increase in circuit scale and an increase in current consumption. Further, in consideration of the variation in threshold voltage of the next-stage single-phase amplifier circuit 20 and the influence of the power supply voltage, the difference between the constant voltages V1, V2, and Vr and the threshold voltage of the single-phase amplifier circuit 20 needs to be increased to some extent. There is.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and to provide a comparison circuit that can easily shorten the charging time of the capacitor Cp without substantially increasing the current consumption and the circuit scale.

  Therefore, in order to solve the above problem, the invention according to claim 1 includes a differential amplifier circuit that outputs an output current corresponding to a difference between the first input voltage and the second input voltage from the output terminal, and the input terminal. A single-phase amplifier circuit connected to the output terminal of the differential amplifier circuit, and a clamp circuit that limits the input voltage of the single-phase amplifier circuit using the output of the single-phase amplifier circuit as an input, The clamp circuit includes a current source element that outputs a current when the output of the single-phase amplifier circuit exceeds a first predetermined voltage, and a current when the output of the single-phase amplifier circuit decreases beyond a second predetermined voltage. And a comparison circuit having at least one of current sink elements for pulling out current.

  The invention according to claim 2 is the invention according to claim 1, wherein the current source element is a source follower circuit by an N-channel MOS transistor or an emitter follower circuit by an NPN transistor, which receives the output of the single-phase amplifier circuit. The current sink element is a source follower circuit using a P-channel MOS transistor or an emitter follower circuit using a PNP transistor that receives the output of the single-phase amplifier circuit.

  The invention according to claim 3 is the invention according to claim 1 or 2, further comprising a waveform shaping circuit that receives the output of the single-phase amplifier circuit, the waveform shaping circuit being lower than the first predetermined voltage, A third predetermined voltage higher than the second predetermined voltage is set as a threshold voltage.

  According to the comparison circuit of the present invention, the output of the single phase amplifier circuit to which the output of the differential amplifier circuit is input is input to a clamp circuit such as a source follower or an emitter follower, and the input of the single phase amplifier circuit is input by the clamp circuit. By limiting, the required charging voltage width can be narrowed and the charging time of the capacitor Cp can be shortened without newly providing a constant voltage source. In addition, since the input of the single-phase amplifier circuit is limited according to the output of the single-phase amplifier circuit, variations in the threshold voltage of the single-phase amplifier circuit and the influence of the power supply voltage are not a problem.

It is a figure which shows the basic composition of this invention. It is a figure which shows the 1st Example of the comparison circuit which concerns on this invention. FIG. 7 is a diagram showing a time chart showing a response when the input voltage Vinm is fixed and the input voltage Vinp is changed from the H level to the L level at time t1 in the first embodiment of the comparison circuit according to the present invention. FIG. 7 is a diagram showing a time chart showing a response when the input voltage Vinm is fixed and the input voltage Vinp is changed from the L level to the H level at time t4 in the first embodiment of the comparison circuit according to the present invention. It is a figure which shows the 2nd Example of the comparison circuit which concerns on this invention. It is a figure which shows the 3rd Example of the comparison circuit which concerns on this invention. It is a figure which shows the structure of the conventional comparison circuit. It is a figure which shows the transient response operation when the relationship of the two input signals with respect to the conventional comparison circuit changes from Vinp << Vinm to Vinp> Vinm. It is a figure which shows the Example of the clamp circuit currently disclosed by patent document 2. FIG. It is a figure which shows another Example of the clamp circuit currently disclosed by patent document 2. FIG.

  FIG. 1 shows the basic configuration of the present invention. The differential amplifier circuit 10, the single phase amplifier circuit 20, and the waveform shaping circuit 30 are connected in series as in the conventional circuit of FIG. 7, but the output Vo2 of the single phase amplifier circuit 20 is input and the output is The difference is that a clamp circuit 40 connected to the input Vo1 of the single-phase amplifier circuit 20 is provided. The point that the clamp circuit is provided is similar to the comparator of Patent Document 2, but the constant voltages V1, V2, and Vr required for the clamp circuit of Patent Document 2 and the circuit for generating them are not necessary. The effects of the invention can be achieved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 shows a first embodiment of a comparison circuit according to the present invention. The parts common to those in FIG. The clamp circuit 41 of FIG. 2 is configured by configuring the clamp circuit 40 of FIG. 1 with a source follower circuit including an N-channel MOS transistor MN5. The gate terminal of the N-channel MOS transistor MN5 is the input terminal of the clamp circuit 41, and the output signal Vo2 of the single-phase amplifier circuit 20 is input here. The source terminal of the N-channel MOS transistor MN5, which is the output terminal of the clamp circuit 41, is connected to the input terminal of the single-phase amplifier circuit 20. With this configuration, it is possible to prevent the voltage of the signal Vo1 from becoming lower than ((voltage of the signal Vo2) − (gate / source voltage of the N-channel MOS transistor MN5)).

  The operation of the clamp circuit of this embodiment will be described with reference to FIGS. FIG. 3 is a time chart showing a response when the input voltage Vinm is fixed and the input voltage Vinp is changed from the H (High) level to the L (Low) level at time t1. Prior to time t1, Vinp> Vinm continued, so that the signals Vo1 and Vol3 are at the H level and the signal Vo2 is at the L level. Since Vinp> Vinm after time t1, the current of (Vinp−Vinm) · gm is drawn from the capacitor Cp by the differential amplifier circuit 10, and thereby the signal Vo1 decreases. When the signal Vo1 reaches the vicinity of the threshold voltage Vth1 of the N-channel MOS transistor MN3 at time t2 and the current flowing through the N-channel MOS transistor MN3 becomes smaller than the bias current Ib2, the signal Vo2 starts increasing. When the signal Vo2 rises above the sum of the signal Vo1 and the threshold voltage of the N-channel MOS transistor MN5, that is, when the gate-source voltage of the N-channel MOS transistor MN5 exceeds the threshold voltage of the transistor, the N-channel MOS transistor The source follower circuit composed of MN5 functions as a current source element, current flows into the capacitor Cp, and a decrease in the signal Vo1 is suppressed. The final magnitude of the signal Vo1 is a gate-source voltage necessary for the N-channel MOS transistor MN3 to pass the bias current Ib2. The final magnitude of the signal voltage Vo2 depends on the signal Vo1 and the N-channel MOS transistor MN5. A current equal to (Vinp−Vinm) · gm is supplied (current equal to the current drawn by the differential amplifier circuit 10 is supplied to the capacitor Cp, and the signal Vo1 becomes stable. The maximum value of the current value is This is a voltage obtained by adding a gate-source voltage necessary for the bias current Ib1. When the signal Vo2 increases and reaches the threshold voltage Vth2 of the waveform shaping circuit 30 at time t3, the output signal Vo3 of the waveform shaping circuit is inverted from H to L.

  FIG. 4 is a time chart showing a response when the input voltage Vinm is fixed and the input voltage Vinp is changed from the L level to the H level at time t4. Before time t4, the state is the same as after time t3 in FIG. From time t4 when Vinp> Vinm changes, a current of (Vinp−Vinm) · gm is output from the output terminal of the differential amplifier circuit 10, and this current charges the capacitor Cp, and the signal Vo1 rises accordingly. Go. The initial value of the signal Vo1 is a gate-source voltage necessary for the N-channel MOS transistor MN3 to pass the bias current Ib2 as described above, and this already exceeds the threshold voltage Vth1 of the N-channel MOS transistor MN3. The signal Vo2 starts to decrease immediately from time t4. When the signal Vo2 falls below the threshold voltage Vth2 of the waveform shaping circuit 30 at time t5, the output Vo3 of the waveform shaping circuit 30 that is the output of the comparison circuit is inverted from L level to H level. . Comparing this operation with that of FIG. 8, it is not necessary to charge the capacitor Cp to the threshold voltage Vth1 of the N-channel MOS transistor MN3 (tb-ta), and the initial value of the signal Vo2 is more waveform than that of FIG. Since it is close to the threshold voltage Vth2 of the shaping circuit 30, the response time of the comparison circuit can be greatly shortened. Further, only a source follower circuit composed of an N-channel MOS transistor MN5 is added to the conventional comparison circuit, a constant voltage source is unnecessary, and an increase in circuit scale and current consumption can be suppressed.

  The first embodiment limits the lower limit of the signal Vo1 and the upper limit of the signal Vo2 when Vinp> Vinm, but the second embodiment shown in FIG. 5 further limits the upper limit of the signal Vo1 and the signal Vo2 when Vinp <Vinm. The lower limit is also limited. In the second embodiment shown in FIG. 5, the same reference numerals are given to the portions common to the first embodiment in FIG. 2, and detailed description thereof is omitted.

  In the second embodiment shown in FIG. 5, a source follower circuit made up of a P-channel MOS transistor MP4 is added to the first embodiment shown in FIG. 2, and this source follower circuit and a source follower circuit made up of an N-channel MOS transistor MN5 are shown. The clamp circuit 42 corresponding to one clamp circuit 40 is configured. The gate terminals of the N-channel MOS transistor MN5 and the P-channel MOS transistor MP4 are input terminals of the clamp circuit 42, and the output signal Vo2 of the single-phase amplifier circuit 20 is input thereto. The source terminals of the N-channel MOS transistor MN5 and the P-channel MOS transistor MP4, which are output terminals of the clamp circuit 42, are connected to the input terminal of the single-phase amplifier circuit 20. With this configuration, the voltage of the signal Vo1 is ((the voltage of the signal Vo2) + (the gate-source voltage of the P-channel MOS transistor MP4)) or more, or ((the voltage of the signal Vo2) − (the gate / source voltage of the N-channel MOS transistor MN5). Source voltage)) or less can be avoided.

  The operation of the source follower circuit composed of the P-channel MOS transistor MP4 limiting the upper limit of the signal Vo1 and the lower limit of the signal Vo2 is the same as the operation of the source follower circuit using the N-channel MOS transistor MN5 described in the first embodiment of the signal Vo1 and the signal Vo2 Since the operation is the same as that for limiting the upper limit, detailed description thereof is omitted. When the signal Vo1 decreases by exceeding the voltage obtained by subtracting the threshold voltage of the P-channel MOS transistor MP4 from the signal Vo1, that is, when the gate-source voltage of the P-channel MOS transistor MP4 exceeds the threshold voltage of the transistor due to the rise of the signal Vo1. The source follower circuit composed of the P-channel MOS transistor MP4 functions as a current sink element, draws charges from the capacitor Cp, and suppresses an increase in the signal Vo1. When Vinp <Vinm and the upper limit of the signal Vo1 and the lower limit of the signal Vo2 are limited, the magnitude of the final signal Vo1 becomes a gate-source voltage necessary for the N-channel MOS transistor MN3 to pass the bias current Ib2, and the signal The magnitude of the voltage Vo2 is that the P-channel MOS transistor MP4 passes a current of (Vinm−Vinp) · gm from this signal Vo1 (a current equal to the current supplied from the differential amplifier circuit 10 is extracted from the capacitor Cp, and the signal Vo1 Is a voltage obtained by subtracting the gate-source voltage necessary for the above.

  From the above, when both the N-channel MOS transistor MN5 and the P-channel MOS transistor MP4 are connected, the magnitude of the signal Vo1 is in the vicinity of the gate-source voltage necessary for the N-channel MOS transistor MN3 to pass the bias current Ib2, and the signal Vo2 Is substantially in the range of ((signal Vo1 + threshold voltage of the N-channel MOS transistor MN5) to (threshold voltage of the signal Vo1-P-channel MOS transistor MP4). The threshold voltage Vth2 of the waveform shaping circuit 30 falls within this range. In addition, the clamp circuit 42 may be configured only by a source follower circuit using a P-channel MOS transistor MP4.

  In the third embodiment shown in FIG. 6, the roles of the P channel MOS transistor and the N channel MOS transistor in the differential amplifier circuit 10 and the single phase amplifier circuit 20 shown in FIG. 20a is constituted. That is, the P channel MOS transistors MP1 and MP2, the N channel MOS transistors MN1 and MN2 and the constant current source 11 of the differential amplifier circuit 10 are replaced with the N channel MOS transistors MN6 and MN7, the P channel MOS transistors MP5 and MP6 and the constant current source, respectively. The differential amplifier circuit 10a is configured by replacing with 11a. Further, the single-phase amplifier circuit 20a is configured by replacing the N-channel MOS transistor MN3 and the constant current source 21 of the single-phase amplifier circuit 20 with the P-channel MOS transistor MP7 and the constant current source 21a, respectively. Since the operation of the present embodiment is the same as that of the second embodiment, description thereof is omitted.

  In the above-described embodiment, the source follower circuit using the N-channel MOS transistor MN5 may be replaced with an emitter follower circuit using an NPN transistor circuit. Further, the source follower circuit using the P-channel MOS transistor MP4 may be replaced with an emitter follower circuit using a PNP transistor circuit.

10, 10a Differential amplifier circuit 11, 11a, 21, 21a Constant current source 20, 20a Single phase amplifier circuit 30 Waveform shaping circuit 40, 41, 42 Clamp circuit Cp Capacitance MN1-MN7 N-channel MOS transistor MP1-MP7 P-channel MOS Transistor

Claims (3)

A differential amplifier circuit that outputs an output current corresponding to a difference between the first input voltage and the second input voltage from an output terminal;
A single-phase amplifier circuit whose input terminal is connected to the output terminal of the differential amplifier circuit;
A clamp circuit that limits the input voltage of the single-phase amplifier circuit using the output of the single-phase amplifier circuit as an input, and
The clamp circuit includes a current source element that outputs a current when the output of the single-phase amplifier circuit exceeds a first predetermined voltage, and the output of the single-phase amplifier circuit decreases when the output of the single-phase amplifier circuit exceeds a second predetermined voltage. A comparison circuit comprising at least one of current sink elements for extracting current.   The current source element is a source follower circuit using an N-channel MOS transistor or an emitter follower circuit using an NPN transistor that receives the output of the single-phase amplifier circuit, and the current sink element receives the output of the single-phase amplifier circuit. 2. The comparison circuit according to claim 1, wherein the comparison circuit is a source follower circuit using a P-channel MOS transistor or an emitter follower circuit using a PNP transistor. A waveform shaping circuit that receives the output of the single-phase amplifier circuit, and the waveform shaping circuit uses a third predetermined voltage that is lower than the first predetermined voltage and higher than the second predetermined voltage as a threshold voltage; The comparison circuit according to claim 1, wherein:

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