CN110320953B - Output voltage adjustable reference voltage source - Google Patents
Output voltage adjustable reference voltage source Download PDFInfo
- Publication number
- CN110320953B CN110320953B CN201910731326.4A CN201910731326A CN110320953B CN 110320953 B CN110320953 B CN 110320953B CN 201910731326 A CN201910731326 A CN 201910731326A CN 110320953 B CN110320953 B CN 110320953B
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- pmos tube
- resistor
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- 239000003990 capacitor Substances 0.000 claims description 5
- 101710084464 Purine nucleoside phosphorylase DeoD-type 2 Proteins 0.000 claims 2
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a reference voltage source with adjustable output voltage, which comprises a starting circuit, a biasing circuit, an operational amplifier and a band gap circuit, wherein the starting circuit is connected with the biasing circuit, the biasing circuit is connected with the operational amplifier and the band gap circuit, and two input ends of the operational amplifier are connected with the band gap circuit. The output voltage of the reference voltage source is realized through the voltage drop of the sum of the two currents on the resistor, and the output reference voltage is determined by changing the load resistor, so that the voltage value required to be generated is conveniently changed; the starting circuit can automatically enter a normal working state when the circuit node is in a degenerated state; the operational amplifier ensures that the band gap circuit can still stably output when the power supply voltage changes; the operational amplifier employs miller compensation to increase system stability.
Description
Technical Field
The invention relates to a reference voltage source with adjustable output voltage, belonging to the technical field of semiconductor integrated circuits.
Background
Reference voltage sources are an extremely important component of analog and digital integrated circuits and are widely used in switching power supplies, dynamic storage, flash memory, and other analog devices. At present, the requirements of consumer electronic products are higher and higher, and with the increase of the requirements of low voltage and low power consumption, especially portable electronic devices, such as mobile phones, tablet computers, notebook computers, bluetooth devices and the like, new requirements are also put on a reference voltage source, because the output voltage of the traditional band-gap reference voltage source is 1.25V, if the power source per se is lower than 1.25V, the structure cannot be realized, and the circuit must be improved to continue to be used.
The conventional bandgap reference voltage source output voltage is not adjustable, about 1.25V (see fig. 2). The voltage irrelevant to temperature is obtained by superposition of a negative temperature coefficient of the base-emitter voltage Vbe of a triode and a positive temperature coefficient of the base-emitter voltage difference delta Vbe in a certain proportion. The disadvantages of this structure are: when the output voltage of the switching power supply is less than 1.25V, it will not be able to provide a reference voltage; when the supply voltage is below 1.25V, it will not be able to output a zero temperature coefficient voltage.
Disclosure of Invention
The invention aims to solve the technical problems that: the reference voltage source with the adjustable output voltage is provided to solve the technical problems that the output voltage of the traditional band-gap reference voltage source is not adjustable, the reference voltage cannot be provided when the output voltage of the switching power supply is smaller than 1.25V, and the zero temperature coefficient voltage cannot be output when the power supply voltage is smaller than 1.25V.
The technical scheme adopted by the invention is as follows: the reference voltage source with adjustable output voltage comprises a starting circuit, a biasing circuit, an operational amplifier and a band gap circuit, wherein the starting circuit is connected with the biasing circuit, the biasing circuit is connected with the operational amplifier and the band gap circuit, and two input ends of the operational amplifier are connected with the band gap circuit.
Preferably, the starting circuit comprises a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2 and an NMOS transistor N3, wherein the drain electrode of the PMOS transistor P1 is connected with the gate electrode of the NMOS transistor N2 and the drain electrode of the NMOS transistor N1 respectively, the gate electrode of the PMOS transistor P2 is connected with the gate electrode of the PMOS transistor P3 and the drain electrode of the NMOS transistor N2 respectively, the drain electrode of the PMOS transistor P2 is connected with the drain electrode of the NMOS transistor N3, and the gate electrode of the NMOS transistor N3 is connected with the drain electrode of the NMOS transistor N3 and the gate electrode of the NMOS transistor N1 respectively.
Preferably, the bias circuit includes a PMOS transistor P3 and an NMOS transistor N4, where the drain of the PMOS transistor P3 is connected to the gate of the PMOS transistor P3 and the drain of the NMOS transistor N4, and the gate of the NMOS transistor N4 is connected to the gate of the NMOS transistor N3.
Preferably, the operational amplifier includes a PMOS transistor P4, a PMOS transistor P5, a PMOS transistor P9, a PMOS transistor P10, an NMOS transistor N5, an NMOS transistor N6, and an NMOS transistor N7, where the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P3 and the gate of the PMOS transistor P5, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P9 and the source of the PMOS transistor P10, the drain of the PMOS transistor P9 is connected to the drain of the NMOS transistor N5, the drain of the PMOS transistor P10 is connected to the drain of the NMOS transistor N6, the gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N5 and the gate of the NMOS transistor N6, the gate of the NMOS transistor N7 is connected to the drain of the NMOS transistor N6, and the capacitor C is connected between the gate and the drain of the NMOS transistor N7.
Preferably, the bandgap circuit includes a PMOS transistor P6, a PMOS transistor P7, a PMOS transistor P8, a resistor R1, a resistor R2, a resistor R3, and a resistor R4, where the gates of the PMOS transistor P6 are connected to the gate of the PMOS transistor P5 and the gate of the PMOS transistor P7, the drain of the PMOS transistor P6 is connected to the gate of the PMOS transistor P9 and the emitter of the PNP transistor Q1, the resistor R1 is connected in parallel with the PNP transistor Q1, the gate of the PMOS transistor P7 is connected to the gate of the PMOS transistor P8, the drain of the PMOS transistor P7 is connected to the gate of the PMOS transistor P10 and the resistor R3, the resistor R3 is connected to the emitter of the PNP transistor Q2, the base of the PNP transistor Q2 is connected to the base of the PNP transistor Q1, the resistor R2 is connected to the drain of the PMOS transistor P7, the drain of the PMOS transistor P8 is connected to the resistor R4, the drain of the PMOS transistor P8 is the output voltage terminal VOUT, and the output voltage VOUT is the voltage across the resistor R4.
The invention has the beneficial effects that: compared with the prior art, the reference voltage source output voltage is realized through the voltage drop of the sum of two currents on the resistor, and the output reference voltage is determined by changing the load resistor, so that the voltage value required to be generated is changed conveniently; the starting circuit can automatically enter a normal working state when the circuit node is in a degenerated state; the operational amplifier ensures that the band gap circuit can still stably output when the power supply voltage changes; the operational amplifier employs miller compensation to increase system stability.
Drawings
FIG. 1 is a block diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a conventional bandgap reference voltage source.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific examples.
Examples: as shown in figure 1, the reference voltage source with adjustable output voltage comprises a starting circuit, a biasing circuit, an operational amplifier and a band gap circuit, wherein the starting circuit is connected with the biasing circuit, the biasing circuit is connected with the operational amplifier and the band gap circuit, and two input ends of the operational amplifier are connected with the band gap circuit.
Preferably, the starting circuit includes a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2, and an NMOS transistor N3, where the drain of the PMOS transistor P1 is connected to the gate of the NMOS transistor N2 and the drain of the NMOS transistor N1, respectively, the gate of the PMOS transistor P2 is connected to the gate of the PMOS transistor P3 and the drain of the NMOS transistor N2, the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the drain of the NMOS transistor N1, respectively, the gate of the PMOS transistor P1 is grounded, the sources of the PMOS transistor P1 and the PMOS transistor P2 are connected to the power source Vin, the sources of the NMOS transistor N1, the NMOS transistor N2, and the NMOS transistor N3 are all grounded, so that the NMOS transistor N2 is turned on and the drain potential of the NMOS transistor N2 is reduced, and the bias circuit is started, the NMOS transistor N2 is turned off, and the NMOS transistor P1 is turned on all the time, and the width ratio of the PMOS transistor P1 is reduced due to low power consumption.
Preferably, the bias circuit comprises a PMOS transistor P3 and an NMOS transistor N4, wherein the drain electrode of the PMOS transistor P3 is connected with the gate electrode of the PMOS transistor P3 and the drain electrode of the NMOS transistor N4 respectively, the gate electrode of the NMOS transistor N4 is connected with the gate electrode of the NMOS transistor N3, the source electrode of the PMOS transistor P3 is connected to the power Vin, the source electrode of the NMOS transistor N4 is grounded, the current of the bias circuit influences the bias currents of the operational amplifier and the bandgap circuit, and the bias currents are not excessively large in consideration of low voltage and low power consumption.
Preferably, the operational amplifier includes a PMOS transistor P4, a PMOS transistor P5, a PMOS transistor P9, a PMOS transistor P10, an NMOS transistor N5, an NMOS transistor N6, and an NMOS transistor N7, wherein the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P3 and the gate of the PMOS transistor P5, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P9 and the source of the PMOS transistor P10, the drain of the PMOS transistor P9 is connected to the drain of the NMOS transistor N5, the drain of the PMOS transistor P10 is connected to the drain of the NMOS transistor N6, the gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N7, the gate of the NMOS transistor N7 is connected to the drain of the NMOS transistor N6, a capacitor C is connected between the gate of the NMOS transistor N7 and the drain of the PMOS transistor P4, the source of the PMOS transistor P5 is connected to the source of the NMOS transistor N5, the source of the NMOS transistor N6 and the NMOS transistor N7 is grounded, and the reference voltage source is mainly used to make the two gain-phase margin of the two transistors have enough phase-to be equal to prevent the phase-oscillation from being satisfied, and the phase margin of the phase-oscillation is also sufficient to be satisfied, and the phase-oscillation is sufficient to be 60. The PMOS tube P9 and the PMOS tube P10 are in first-stage differential amplification, and the NMOS tube N7 is in second-stage common-source amplification. The PMOS transistor P4 and the PMOS transistor P5 respectively provide bias currents for the two-stage amplifying circuit. The capacitor C is a Miller capacitor compensation, the main pole and the secondary pole are separated, and the phase margin is increased.
Preferably, the bandgap circuit comprises a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the grid electrode of the PMOS tube P6 is respectively connected with the grid electrode of the PMOS tube P5 and the grid electrode of the PMOS tube P7, the drain electrode of the PMOS tube P6 is respectively connected with the grid electrode of the PMOS tube P9 and the emitter electrode of the PNP tube Q1, the resistor R1 is connected with the PNP tube Q1 in parallel, the grid electrode of the PMOS tube P7 is connected with the grid electrode of the PMOS tube P8, the drain electrode of the PMOS tube P7 is respectively connected with the grid electrode of the PMOS tube P10 and the resistor R3, the resistor R3 is connected with the emitter electrode of the PNP tube Q2, the base electrode of the PNP tube Q2 is connected with the base electrode of the PNP tube Q1 and grounded, the resistor R2 is connected with the drain electrode of the PMOS tube P7, the drain electrode of the PMOS tube P8 is connected with the resistor R4, the drain electrode of the PMOS tube P8 is used as an output voltage end VOUT, the output voltage VOUT is the voltage at two ends of the resistor R4, the collector and the base of the resistor R1, the collector and the base of the PNP tube Q2, the resistor R2 and the resistor R4 are grounded, the potentials at the X point and the Y point in the graph 1 are equal due to the operational amplifier, the voltages at the two ends of the resistor R2 are Vbe, the width-to-length ratio of the PMOS tube P6, the PMOS tube P7 and the PMOS tube P8 is the same, so that the currents flowing through the PNP tube Q1 and the PNP tube Q2 are equal, when the resistor R1 and the resistor R2 are equal, the voltages at the two ends of the resistor R3 are delta Vbe, so that the drain current of the PMOS tube P7 is the sum of the current flowing through the resistor R2 and the current flowing through the resistor R3, one current is in direct proportion to the Vbe of the triode, the other current is in direct proportion to delta Vbe, the generated reference current is mirrored to the output current through the PMOS tube P8, the output reference voltage is determined through the output load resistor R4, and the voltage value required to be generated is convenient to change.
The foregoing is merely illustrative of the present invention, and the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the scope of the present invention, and therefore, the scope of the present invention shall be defined by the scope of the appended claims.
Claims (1)
1. An output voltage adjustable reference voltage source, characterized in that: the circuit comprises a starting circuit, a bias circuit, an operational amplifier and a band gap circuit, wherein the starting circuit is connected with the bias circuit, the bias circuit is connected with the operational amplifier and the band gap circuit, and two input ends of the operational amplifier are connected with the band gap circuit;
the starting circuit comprises a PMOS tube P1, a PMOS tube P2, an NMOS tube N1, an NMOS tube N2 and an NMOS tube N3, wherein the drain electrode of the PMOS tube P1 is respectively connected with the grid electrode of the NMOS tube N2 and the drain electrode of the NMOS tube N1, the grid electrode of the PMOS tube P2 is respectively connected with the grid electrode of the PMOS tube P3 and the drain electrode of the NMOS tube N2, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N3, the grid electrode of the NMOS tube N3 is respectively connected with the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube N1, the source electrodes of the NMOS tube N1, the NMOS tube N2 and the source electrode of the NMOS tube N3 are grounded, and the source electrodes of the PMOS tube P1 and the PMOS tube P2 are respectively connected with an input voltage end Vin;
the bias circuit comprises a PMOS tube P3 and an NMOS tube N4, wherein the drain electrode of the PMOS tube P3 is respectively connected with the grid electrode of the PMOS tube P3 and the drain electrode of the NMOS tube N4, the grid electrode of the NMOS tube N4 is connected with the grid electrode of the NMOS tube N3, the source electrode of the PMOS tube P3 is connected with an input voltage end Vin, and the source electrode of the NMOS tube N4 is grounded;
the operational amplifier comprises a PMOS tube P4, a PMOS tube P5, a PMOS tube P9, a PMOS tube P10, an NMOS tube N5, an NMOS tube N6 and an NMOS tube N7, wherein the grid electrode of the PMOS tube P4 is respectively connected with the grid electrode of the PMOS tube P3 and the grid electrode of the PMOS tube P5, the drain electrode of the PMOS tube P4 is respectively connected with the source electrodes of the PMOS tube P9 and the PMOS tube P10, the drain electrode of the PMOS tube P9 is connected with the drain electrode of the NMOS tube N5, the drain electrode of the PMOS tube P10 is connected with the drain electrode of the NMOS tube N6, the grid electrode of the NMOS tube N5 is respectively connected with the drain electrode of the NMOS tube N5 and the grid electrode of the NMOS tube N7, the grid electrode of the NMOS tube N7 is connected with the drain electrode of the NMOS tube N6, a capacitor C is connected between the grid electrode of the NMOS tube N7 and the drain electrode, the source electrodes of the PMOS tube P4 and the PMOS tube P5 are both connected with an input voltage end Vin, and the source electrodes of the NMOS tube N5 and the NMOS tube N6 are grounded;
the band gap circuit comprises a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the grid electrode of the PMOS tube P6 is respectively connected with the grid electrode of the PMOS tube P5 and the grid electrode of the PMOS tube P7, the drain electrode of the PMOS tube P6 is respectively connected with the grid electrode of the PMOS tube P9 and the emitting electrode of the PNP tube Q1, the sources of the PMOS tube P6, the PMOS tube P7 and the PMOS tube P8 are connected to an input voltage end Vin, one end of the resistor R1 is connected with the emitting electrode of the PNP tube Q1, the other end of the resistor R1 is connected with the collector of the PNP tube Q1, the grid electrode of the PMOS tube P7 is connected with the grid electrode of the PMOS tube P8, the drain electrode of the PMOS tube P7 is respectively connected with the grid electrode of the PMOS tube P10 and one end of the resistor R3, the other end of the resistor R3 is connected with the emitting electrode of the PNP tube Q2, the base electrode of the PNP tube Q2 is connected with the base electrode of the PNP tube Q1, one end of the resistor R2 is connected with the drain electrode of the PMOS tube P7, one end of the other end of the resistor P8 is connected with the drain electrode of the resistor R4 is connected with the other end of the resistor R2 is connected with the drain electrode of the PNP 2, the other end of the resistor R2 is connected with the drain electrode of the PNP 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910731326.4A CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910731326.4A CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
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| CN110320953A CN110320953A (en) | 2019-10-11 |
| CN110320953B true CN110320953B (en) | 2024-03-01 |
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| CN201910731326.4A Active CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
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| CN110716606B (en) * | 2019-11-23 | 2020-10-09 | 许昌学院 | Low-power-consumption anti-electromagnetic interference reference current source |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205942498U (en) * | 2016-08-18 | 2017-02-08 | 成都信息工程大学 | Output voltage adjustable band gap reference voltage source |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN210005943U (en) * | 2019-08-08 | 2020-01-31 | 贵州辰矽电子科技有限公司 | reference voltage source with adjustable output voltage |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8552707B2 (en) * | 2011-02-23 | 2013-10-08 | Himax Technologies Limited | Bandgap circuit and complementary start-up circuit for bandgap circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205942498U (en) * | 2016-08-18 | 2017-02-08 | 成都信息工程大学 | Output voltage adjustable band gap reference voltage source |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN210005943U (en) * | 2019-08-08 | 2020-01-31 | 贵州辰矽电子科技有限公司 | reference voltage source with adjustable output voltage |
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| CN110320953A (en) | 2019-10-11 |
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