CN110320953A - A kind of adjustable reference voltage source of output voltage - Google Patents
A kind of adjustable reference voltage source of output voltage Download PDFInfo
- Publication number
- CN110320953A CN110320953A CN201910731326.4A CN201910731326A CN110320953A CN 110320953 A CN110320953 A CN 110320953A CN 201910731326 A CN201910731326 A CN 201910731326A CN 110320953 A CN110320953 A CN 110320953A
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- pmos tube
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- grid
- drain electrode
- nmos tube
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- 239000003990 capacitor Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a kind of adjustable reference voltage sources of output voltage, including start-up circuit, biasing circuit, operational amplifier and band-gap circuit, start-up circuit is connected with biasing circuit, and biasing circuit is connected with operational amplifier, band-gap circuit, and two input terminal of operational amplifier is connected with band-gap circuit.Reference voltage source output voltage of the invention is realized by the sum of two electric currents in ohmically pressure drop, is determined output reference voltage by changing load resistance, is facilitated the voltage value generated needed for changing；Start-up circuit makes circuit node can also be automatically into normal operating conditions when being in degeneracy state；Operational amplifier ensures that band-gap circuit remains to stablize output in mains voltage variations；Operational amplifier increases system stability using miller compensation.
Description
Technical field
The present invention relates to a kind of adjustable reference voltage sources of output voltage, belong to semiconductor integrated circuit technology field.
Background technique
Reference voltage source is Analogous Integrated Electronic Circuits and the particularly important component part of digital integrated electronic circuit, it is widely used
In Switching Power Supply, dynamic memory, flash memory and other analog devices.Currently, demand of the people to consumer electronics product is got over
Come it is higher, with the increase that low-voltage and low-power dissipation requires, especially portable electronic device, such as mobile phone, tablet computer, notebook electricity
Brain, bluetooth equipment etc., also put forward new requirements reference voltage source, because traditional bandgap voltage reference output voltage is
1.25V, if power supply itself is lower than 1.25V, this structure is impossible to realize, it is necessary to which being improved circuit could continue to make
With.
Traditional bandgap voltage reference output voltage is non-adjustable, and about 1.25V(is shown in Fig. 2).It utilizes transistor base-
The negative temperature coefficient of emitter voltage Vbe and the positive temperature coefficient of base-emitter voltage difference value △ Vbe, pass through certain proportion
Superposition obtains temperature independent voltage.The shortcomings that this structure, is: when Switching Power Supply output voltage be less than 1.25V, then
It cannot provide reference voltage；When supply voltage is lower than 1.25V, then it will be unable to the voltage of output zero-temperature coefficient.
Summary of the invention
The technical problem to be solved by the present invention is a kind of adjustable reference voltage source of output voltage is provided, to solve tradition
Bandgap voltage reference output voltage it is non-adjustable, when Switching Power Supply output voltage be less than 1.25V cannot provide with reference to electricity
Pressure will be unable to the technical issues of exporting the voltage of zero-temperature coefficient when supply voltage is lower than 1.25V.
The technical scheme adopted by the invention is as follows: a kind of adjustable reference voltage source of output voltage, including start-up circuit, biasing
Circuit, operational amplifier and band-gap circuit, start-up circuit are connected with biasing circuit, biasing circuit and operational amplifier, band gap electricity
Road is connected, and two input terminal of operational amplifier is connected with band-gap circuit.
Preferably, above-mentioned start-up circuit includes PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube N2 and NMOS tube N3,
The drain electrode of PMOS tube P1 is connected with the drain electrode of the grid of NMOS tube N2 and NMOS tube N1 respectively, the grid of PMOS tube P2 respectively with
The grid of PMOS tube P3 is connected with the drain electrode of NMOS tube N2, and the drain electrode of PMOS tube P2 is connected with the drain electrode of NMOS tube N3, NMOS tube
The grid of N3 is connected with the grid of the drain electrode of NMOS tube N3 and NMOS tube N1 respectively.
Preferably, above-mentioned biasing circuit includes PMOS tube P3 and NMOS tube N4, the drain electrode of PMOS tube P3 respectively with PMOS tube
The grid of P3 is connected with the drain electrode of NMOS tube N4, and the grid of NMOS tube N4 is connected with the grid of NMOS tube N3.
Preferably, above-mentioned operational amplifier includes PMOS tube P4, PMOS tube P5, PMOS tube P9, PMOS tube P10, NMOS tube
N5, NMOS tube N6 and NMOS tube N7, the grid of PMOS tube P4 are connected with the grid of the grid of PMOS tube P3 and PMOS tube P5 respectively,
The drain electrode of PMOS tube P4 is connected with the source electrode of PMOS tube P9 and PMOS tube P10 respectively, and the drain electrode of PMOS tube P9 is with NMOS tube N5's
Drain electrode is connected, and the drain electrode of PMOS tube P10 is connected with the drain electrode of NMOS tube N6, the leakage with NMOS tube N5 respectively of the grid of NMOS tube N5
Pole is connected with the grid of NMOS tube N6, and the drain electrode of PMOS tube P5 is connected with the drain electrode of NMOS tube N7, the grid of NMOS tube N7 with
The drain electrode of NMOS tube N6 is connected, and is connected with capacitor C between the grid and drain electrode of NMOS tube N7.
Preferably, above-mentioned band-gap circuit includes PMOS tube P6, PMOS tube P7, PMOS tube P8, resistance R1, resistance R2, resistance
R3, resistance R4, PNP pipe Q1 and PNP pipe Q2, the grid of the PMOS tube P6 grid with the grid of PMOS tube P5 and PMOS tube P7 respectively
It is connected, the drain electrode of PMOS tube P6 is connected with the emitter of the grid of PMOS tube P9 and PNP pipe Q1 respectively, resistance R1 and PNP pipe Q1
The grid of parallel connection, PMOS tube P7 is connected with the grid of PMOS tube P8, PMOS tube P7 drain electrode respectively with the grid of PMOS tube P10 and
Resistance R3 is connected, and resistance R3 is connected with the emitter of PNP pipe Q2, and the base stage of PNP pipe Q2 is connected with the base stage of PNP pipe Q1, resistance
R2 is connected with the drain electrode of PMOS tube P7, and the drain electrode of PMOS tube P8 is connected with resistance R4, and the drain electrode of PMOS tube P8 is as output voltage
Holding VOUT, output voltage VO UT is resistance R4 both end voltage.
Beneficial effects of the present invention: compared with prior art, reference voltage source output voltage of the invention passes through two electricity
The sum of stream is realized in ohmically pressure drop, is determined output reference voltage by changing load resistance, is facilitated and generate needed for change
Voltage value；Start-up circuit makes circuit node can also be automatically into normal operating conditions when being in degeneracy state；Operation amplifier
Device ensures that band-gap circuit remains to stablize output in mains voltage variations；Operational amplifier increases system using miller compensation and stablizes
Property.
Detailed description of the invention
Fig. 1 is structural block diagram of the invention；
Fig. 2 is existing traditional bandgap reference voltage source structural schematic diagram.
Specific embodiment
With reference to the accompanying drawing and the present invention is described further in specific embodiment.
Embodiment: as shown in Figure 1, a kind of adjustable reference voltage source of output voltage, including start-up circuit, biasing circuit,
Operational amplifier and band-gap circuit, start-up circuit are connected with biasing circuit, biasing circuit and operational amplifier, band-gap circuit phase
Even, two input terminal of operational amplifier is connected with band-gap circuit.
Preferably, above-mentioned start-up circuit includes PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube N2 and NMOS tube N3,
The drain electrode of PMOS tube P1 is connected with the drain electrode of the grid of NMOS tube N2 and NMOS tube N1 respectively, the grid of PMOS tube P2 respectively with
The grid of PMOS tube P3 is connected with the drain electrode of NMOS tube N2, and the drain electrode of PMOS tube P2 is connected with the drain electrode of NMOS tube N3, NMOS tube
The grid of N3 is connected with the grid of the drain electrode of NMOS tube N3 and NMOS tube N1 respectively, the grounded-grid of PMOS tube P1, PMOS tube P1
Power supply Vin, the source grounding of NMOS tube N1, NMOS tube N2 and NMOS tube N3, PMOS tube are connected to the source electrode of PMOS tube P2
P1 is connected always, so that the drain potential of NMOS tube N2 conducting and NMOS tube N2 reduce, therefore PMOS tube P2 is connected, biased electrical
Road starting, NMOS tube N1 conducting, therefore NMOS tube N2 is turned off, because PMOS tube P1 is connected always, is considered for low-power consumption, is reduced
PMOS tube P1 breadth length ratio is to reduce electric current.
Preferably, above-mentioned biasing circuit includes PMOS tube P3 and NMOS tube N4, the drain electrode of PMOS tube P3 respectively with PMOS tube
The grid of P3 is connected with the drain electrode of NMOS tube N4, and the grid of NMOS tube N4 is connected with the grid of NMOS tube N3, the source of PMOS tube P3
Pole is connected to power supply Vin, the source electrode ground connection of NMOS tube N4, and the size of current of biasing circuit influences operational amplifier and band-gap circuit
Bias current, consider that electric current should not be too large in low-voltage and low-power dissipation.
Preferably, above-mentioned operational amplifier includes PMOS tube P4, PMOS tube P5, PMOS tube P9, PMOS tube P10, NMOS tube
N5, NMOS tube N6 and NMOS tube N7, the grid of PMOS tube P4 are connected with the grid of the grid of PMOS tube P3 and PMOS tube P5 respectively,
The drain electrode of PMOS tube P4 is connected with the source electrode of PMOS tube P9 and PMOS tube P10 respectively, and the drain electrode of PMOS tube P9 is with NMOS tube N5's
Drain electrode is connected, and the drain electrode of PMOS tube P10 is connected with the drain electrode of NMOS tube N6, the leakage with NMOS tube N5 respectively of the grid of NMOS tube N5
Pole is connected with the grid of NMOS tube N6, and the drain electrode of PMOS tube P5 is connected with the drain electrode of NMOS tube N7, the grid of NMOS tube N7 with
The drain electrode of NMOS tube N6 is connected, and capacitor C, the source electrode of PMOS tube P4 and PMOS tube P5 are connected between the grid and drain electrode of NMOS tube N7
It is connected to power supply Vin, the source electrode of NMOS tube N5, NMOS tube N6 and NMOS tube N7 are grounded, operational amplifier master in reference voltage source
Act on be keep the current potential of two input terminals equal, as long as so gain enough, in addition to preventing from vibrating, phase is abundant
Degree will also meet 45 ° -60 °.PMOS tube P9 and PMOS tube P10 is first order differential amplification, and NMOS tube N7 is that second level common source is put
Greatly.PMOS tube P4 and PMOS tube P5 is respectively that two-stage amplifying circuit provides bias current.Capacitor C is Muller capacitance compensation, will be led
Secondary pole separation, increases phase margin.
Preferably, above-mentioned band-gap circuit includes PMOS tube P6, PMOS tube P7, PMOS tube P8, resistance R1, resistance R2, resistance
R3, resistance R4, PNP pipe Q1 and PNP pipe Q2, the grid of the PMOS tube P6 grid with the grid of PMOS tube P5 and PMOS tube P7 respectively
It is connected, the drain electrode of PMOS tube P6 is connected with the emitter of the grid of PMOS tube P9 and PNP pipe Q1 respectively, resistance R1 and PNP pipe Q1
The grid of parallel connection, PMOS tube P7 is connected with the grid of PMOS tube P8, PMOS tube P7 drain electrode respectively with the grid of PMOS tube P10 and
Resistance R3 is connected, and resistance R3 is connected with the emitter of PNP pipe Q2, and the base stage of PNP pipe Q2 is connected and connects with the base stage of PNP pipe Q1
Ground, resistance R2 are connected with the drain electrode of PMOS tube P7, and the drain electrode of PMOS tube P8 is connected with resistance R4, and the drain electrode of PMOS tube P8 is as defeated
Voltage end VOUT out, output voltage VO UT are resistance R4 both end voltage, and the source electrode of PMOS tube P6, PMOS tube P7 and PMOS tube P8 connect
It is connected to power supply Vin, resistance R1, the collector of PNP pipe Q2 and base stage, the collector of PNP pipe Q2 and base stage, resistance R2 and resistance R4
Ground connection, due to operational amplifier, the current potential of X point and Y point is equal in Fig. 1, and the voltage at the both ends resistance R2 is Vbe, PMOS
Pipe P6, PMOS tube P7 are identical with the breadth length ratio of PMOS tube P8 three, so the electric current for flowing through PNP pipe Q1 and PNP pipe Q2 is equal, when
When resistance R1 and resistance R2 equal, the voltage at the both ends resistance R3 is just △ Vbe, so the drain current of PMOS tube P7 is to flow through electricity
It hinders the electric current of R2 and flows through the sum of the electric current of resistance R3, an electric current is directly proportional to the Vbe of triode, another electric current and △
Vbe is directly proportional, and the reference current of generation is mirrored to output electric current by PMOS tube P8, then defeated by output load resistance R4 decision
Reference voltage out facilitates the voltage value generated needed for changing.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Within protection scope of the present invention, therefore, protection scope of the present invention should be based on the protection scope of the described claims lid.
Claims (5)
1. a kind of adjustable reference voltage source of output voltage, it is characterised in that: including start-up circuit, biasing circuit, operation amplifier
Device and band-gap circuit, start-up circuit are connected with biasing circuit, and biasing circuit is connected with operational amplifier, band-gap circuit, and operation is put
Big two input terminal of device is connected with band-gap circuit.
2. the adjustable reference voltage source of a kind of output voltage according to claim 1, it is characterised in that: start-up circuit includes
PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube N2 and NMOS tube N3, the drain electrode of PMOS tube P1 is respectively with NMOS tube N2's
Grid is connected with the drain electrode of NMOS tube N1, the grid of the PMOS tube P2 drain electrode phase with the grid of PMOS tube P3 and NMOS tube N2 respectively
Even, the drain electrode of PMOS tube P2 is connected with the drain electrode of NMOS tube N3, the grid of NMOS tube N3 respectively with the drain electrode of NMOS tube N3 and
The grid of NMOS tube N1 is connected.
3. the adjustable reference voltage source of a kind of output voltage according to claim 2, it is characterised in that: biasing circuit includes
The drain electrode of PMOS tube P3 and NMOS tube N4, PMOS tube P3 are connected with the drain electrode of the grid of PMOS tube P3 and NMOS tube N4 respectively,
The grid of NMOS tube N4 is connected with the grid of NMOS tube N3.
4. the adjustable reference voltage source of a kind of output voltage according to claim 1, it is characterised in that: operational amplifier packet
PMOS tube P4, PMOS tube P5, PMOS tube P9, PMOS tube P10, NMOS tube N5, NMOS tube N6 and NMOS tube N7 are included, PMOS tube P4's
Grid is connected with the grid of the grid of PMOS tube P3 and PMOS tube P5 respectively, the drain electrode of PMOS tube P4 respectively with PMOS tube P9 and
The source electrode of PMOS tube P10 is connected, and the drain electrode of PMOS tube P9 is connected with the drain electrode of NMOS tube N5, the drain electrode of PMOS tube P10 and NMOS
The drain electrode of pipe N6 is connected, and the grid of NMOS tube N5 is connected with the grid of the drain electrode of NMOS tube N5 and NMOS tube N6 respectively, PMOS tube
The drain electrode of P5 is connected with the drain electrode of NMOS tube N7, and the grid of NMOS tube N7 is connected with the drain electrode of NMOS tube N6, the grid of NMOS tube N7
Capacitor C is connected between pole and drain electrode.
5. the adjustable reference voltage source of a kind of output voltage according to claim 1, it is characterised in that: band-gap circuit includes
PMOS tube P6, PMOS tube P7, PMOS tube P8, resistance R1, resistance R2, resistance R3, resistance R4, PNP pipe Q1 and PNP pipe Q2, PMOS
The grid of pipe P6 is connected with the grid of the grid of PMOS tube P5 and PMOS tube P7 respectively, the drain electrode of PMOS tube P6 respectively with PMOS tube
The grid of P9 is connected with the emitter of PNP pipe Q1, and resistance R1 is in parallel with PNP pipe Q1, and the grid of PMOS tube P7 is with PMOS tube P8's
Grid is connected, and the drain electrode of PMOS tube P7 is connected with the grid of PMOS tube P10 and resistance R3 respectively, the hair of resistance R3 and PNP pipe Q2
Emitter-base bandgap grading is connected, and the base stage of PNP pipe Q2 is connected with the base stage of PNP pipe Q1, and resistance R2 is connected with the drain electrode of PMOS tube P7, PMOS tube P8
Drain electrode be connected with resistance R4, the drain electrode of PMOS tube P8 is as output voltage terminal VOUT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910731326.4A CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910731326.4A CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
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| Publication Number | Publication Date |
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| CN110320953A true CN110320953A (en) | 2019-10-11 |
| CN110320953B CN110320953B (en) | 2024-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910731326.4A Active CN110320953B (en) | 2019-08-08 | 2019-08-08 | Output voltage adjustable reference voltage source |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110716606A (en) * | 2019-11-23 | 2020-01-21 | 许昌学院 | Low-power-consumption anti-electromagnetic interference reference current source |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120212207A1 (en) * | 2011-02-23 | 2012-08-23 | Himax Technologies Limited | Bandgap Circuit and Complementary Start-Up Circuit for Bandgap Circuit |
| CN205942498U (en) * | 2016-08-18 | 2017-02-08 | 成都信息工程大学 | Output voltage adjustable band gap reference voltage source |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN210005943U (en) * | 2019-08-08 | 2020-01-31 | 贵州辰矽电子科技有限公司 | reference voltage source with adjustable output voltage |
-
2019
- 2019-08-08 CN CN201910731326.4A patent/CN110320953B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120212207A1 (en) * | 2011-02-23 | 2012-08-23 | Himax Technologies Limited | Bandgap Circuit and Complementary Start-Up Circuit for Bandgap Circuit |
| CN205942498U (en) * | 2016-08-18 | 2017-02-08 | 成都信息工程大学 | Output voltage adjustable band gap reference voltage source |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN210005943U (en) * | 2019-08-08 | 2020-01-31 | 贵州辰矽电子科技有限公司 | reference voltage source with adjustable output voltage |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110716606A (en) * | 2019-11-23 | 2020-01-21 | 许昌学院 | Low-power-consumption anti-electromagnetic interference reference current source |
| CN110716606B (en) * | 2019-11-23 | 2020-10-09 | 许昌学院 | Low-power-consumption anti-electromagnetic interference reference current source |
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| Publication number | Publication date |
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| CN110320953B (en) | 2024-03-01 |
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