CN217388659U - Differential operational amplifier and chip - Google Patents

Abstract

The utility model discloses a differential operational amplifier and a chip, wherein the differential operational amplifier comprises a current mirror circuit, a first-stage amplifying circuit, a second-stage amplifying circuit and a common-mode feedback circuit; the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit support differential input and differential output. The differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier; the output end of the current mirror circuit is connected with the power supply end of the first-stage amplifying circuit; the input end of the current mirror circuit is used for receiving signals input into the differential operational amplifier from the outside.

Description

Differential operational amplifier and chip

Technical Field

The utility model belongs to the technical field of differential amplifier, especially, relate to a differential operational amplifier and chip.

Background

At present, the common techniques for designing amplifiers mainly include an active follower structure, a common source amplifier structure, a resistance negative feedback structure, and the like, wherein the active follower structure and the resistance negative feedback structure are commonly used for driving analog small signals, low-resistance loads, capacitive loads, and the like due to high linearity and low output resistance, and the common source amplifier is commonly used for driving large-power signals and full-swing large signals. When the common source amplifier structure is at a high frequency, the linearity of the driving circuit is deteriorated due to the parasitic capacitance of the common source amplifier structure, and the amplified signal is unstable. In a multistage operational amplifier, the output stage of the operational amplifier is generally required to be able to provide a large output range, but as the power supply voltage is gradually reduced, a large number of MOS transistors are cascaded, and thus the voltage output is unstable.

SUMMERY OF THE UTILITY MODEL

To the technical defect, the utility model discloses a design two-stage amplifier circuit and the working loop between the common mode feedback circuit, propose a difference operational amplifier, specific technical scheme is as follows:

the differential operational amplifier comprises a current mirror circuit, a first-stage amplifying circuit, a second-stage amplifying circuit and a common-mode feedback circuit; the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit all support differential input and differential output; the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier; the output end of the current mirror circuit is connected with the power supply end of the first-stage amplifying circuit; the input end of the current mirror circuit is used for receiving signals input into the differential operational amplifier from the outside.

Further, the common mode feedback circuit comprises a first common mode feedback circuit and a second common mode feedback circuit; the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a first common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a second common-mode feedback circuit; and the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier.

Further, the differential operational amplifier is a four-input operational amplifier, wherein the positive input end of the differential operational amplifier comprises a first positive input end of the differential operational amplifier and a second positive input end of the differential operational amplifier, and the negative input end of the differential operational amplifier comprises a first negative input end of the differential operational amplifier and a second negative input end of the differential operational amplifier; the first positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are used for accessing a pair of differential signals to be processed; the first negative input end of the differential operational amplifier and the second positive input end of the differential operational amplifier are both connected with a common-mode reference voltage; the first positive input end of the differential operational amplifier, the first negative input end of the differential operational amplifier, the second positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are input ends of a current mirror circuit; the power supply accessed by the power supply end of the second-stage amplifying circuit is equal to the power supply accessed by the power supply end of the current mirror circuit; the ground terminal of the second-stage amplification circuit and the ground terminal of the first-stage amplification circuit share a ground line.

Further, the current mirror circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; the grid electrode of the third PMOS tube is the first positive input end of the differential operational amplifier, the grid electrode of the fifth PMOS tube is the second positive input end of the differential operational amplifier, the grid electrode of the fourth PMOS tube is the first negative input end of the differential operational amplifier, and the grid electrode of the sixth PMOS tube is the second negative input end of the differential operational amplifier; the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the connection node of the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube is the first output end of the current mirror circuit; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the connection node of the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube is the second output end of the current mirror circuit; the output end of the current mirror circuit comprises a first output end of the current mirror circuit and a second output end of the current mirror circuit; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are both connected to the drain electrode of the first PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected to the drain electrode of the second PMOS tube; the grid electrode of the first PMOS tube is a first feedback end of the current mirror circuit, the grid electrode of the second PMOS tube is a second feedback end of the current mirror circuit, and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with the output end of the first common mode feedback circuit; the feedback end of the current mirror circuit comprises a first feedback end of the current mirror circuit and a second feedback end of the current mirror circuit; the source electrode of the first PMOS tube is a first power supply end of the current mirror circuit, and the source electrode of the second PMOS tube is a second power supply end of the current mirror circuit; the power supply terminal of the current mirror circuit comprises a first power supply terminal of the current mirror circuit and a second power supply terminal of the current mirror circuit.

Furthermore, the first-stage amplifying circuit comprises a seventh PMOS tube, an eighth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the source electrode of the seventh PMOS tube is a first power supply end of the first-stage amplifying circuit, and the first power supply end of the first-stage amplifying circuit is connected with the first output end of the current mirror circuit; the source electrode of the eighth PMOS tube is a second power supply end of the first-stage amplifying circuit, and the second power supply end of the first-stage amplifying circuit is connected with the second output end of the current mirror circuit; the grid electrode of the seventh PMOS tube is connected with a first bias voltage provided by the outside; the grid electrode of the eighth PMOS tube is connected with a first bias voltage provided by the outside; the power supply end of the first-stage amplifying circuit comprises a first power supply end of the first-stage amplifying circuit and a second power supply end of the first-stage amplifying circuit; the output end of the current mirror circuit comprises a first output end of the current mirror circuit and a second output end of the current mirror circuit; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with second bias voltage provided by the outside, the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with third bias voltage provided by the outside, and the source electrode of the third NMOS tube is grounded; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with second bias voltage provided by the outside, the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with third bias voltage provided by the outside, and the source electrode of the fourth NMOS tube is grounded; the connection node of the drain electrode of the seventh PMOS tube and the drain electrode of the first NMOS tube is the positive output end of the first-stage amplification circuit, and the connection node of the drain electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube is the negative output end of the first-stage amplification circuit; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit; the positive output end of the first-stage amplifying circuit and the negative output end of the first-stage amplifying circuit are respectively connected with the differential input end of the first common-mode feedback circuit, and the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit are both connected with the output end of the first common-mode feedback circuit so as to adjust the differential output result of the first-stage amplifying circuit; the feedback end of the current mirror circuit comprises a first feedback end of the current mirror circuit and a second feedback end of the current mirror circuit.

Further, the second-stage amplification circuit comprises a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; a source electrode of the ninth PMOS tube is connected with the first power supply end of the current mirror circuit, a drain electrode of the ninth PMOS tube is connected with a drain electrode of the fifth NMOS tube, a grid electrode of the ninth PMOS tube is a positive input end of the second-stage amplification circuit, the grid electrode of the ninth PMOS tube is connected with a positive output end of the first-stage amplification circuit, and a source electrode of the fifth NMOS tube is grounded; the connection node of the drain electrode of the ninth PMOS tube and the drain electrode of the fifth NMOS tube is the positive output end of the second-stage amplification circuit; the source electrode of the tenth PMOS tube is connected with the second power supply end of the current mirror circuit, the drain electrode of the tenth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the tenth PMOS tube is the negative input end of the second-stage amplification circuit, the grid electrode of the tenth PMOS tube is connected with the negative output end of the first-stage amplification circuit, and the source electrode of the sixth NMOS tube is grounded; the connection node of the drain electrode of the tenth PMOS tube and the drain electrode of the sixth NMOS tube is the negative output end of the second-stage amplification circuit; the positive output end of the second-stage amplifying circuit and the negative output end of the second-stage amplifying circuit are respectively connected with the differential input end of the second common-mode feedback circuit; the grid electrode of the fifth NMOS tube is a first feedback end of the second-stage amplification circuit, the grid electrode of the fourth NMOS tube is a second feedback end of the second-stage amplification circuit, and the first feedback end of the second-stage amplification circuit and the second feedback end of the second-stage amplification circuit are both connected with the output end of the second common-mode feedback circuit so as to adjust the differential output result of the second-stage amplification circuit; the differential input end of the second-stage amplification circuit comprises a positive input end of the second-stage amplification circuit and a negative input end of the second-stage amplification circuit; the differential output end of the second-stage amplifying circuit comprises a positive output end of the second-stage amplifying circuit and a negative output end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit; the power supply end of the current mirror circuit comprises a first power supply end of the current mirror circuit and a second power supply end of the current mirror circuit; the feedback end of the second-stage amplifying circuit comprises a first feedback end of the second-stage amplifying circuit and a second feedback end of the second-stage amplifying circuit.

Further, the first bias voltage, the second bias voltage and the third bias voltage are different from each other, so that voltage differences are formed between different pairs of MOS tubes; wherein a voltage difference of any two bias voltages among the first bias voltage, the second bias voltage, and the third bias voltage is kept constant; the first bias voltage, the second bias voltage, and the third bias voltage are all provided by respective bias voltage sources.

Further, the first common mode feedback circuit and the second common mode feedback circuit belong to the same type of common mode feedback structure, and the first common mode feedback circuit and the second common mode feedback circuit are connected to the same common mode reference voltage, so that the output of the differential operational amplifier is stabilized to the same common mode level.

Further, the first common-mode feedback circuit is configured to generate a feedback control signal to a feedback end of the current mirror circuit, so as to adjust a voltage average of the differential signal output by the first-stage amplification circuit to be equal to the common-mode reference voltage; the second common mode feedback circuit is used for generating a feedback control signal to a feedback end of the second-stage amplifying circuit so as to regulate the voltage average value of the differential signal output by the second-stage amplifying circuit to be equal to the common mode reference voltage.

A chip with the differential operational amplifier inside.

Compared with the prior art, the utility model designs the operational amplifier into the operational amplifier with four input ends, and supports two pairs of differential inputs and a pair of differential outputs, and has a current mirror load structure and a common mode feedback circuit, and can form a working loop of a first-stage amplification circuit, a second-stage amplification circuit and the common mode feedback circuit; because only two-stage amplification circuits are designed, the driving capability of the operational amplifier is improved on the premise of ensuring that the complexity of the circuit is not high, the stability of amplified signals is ensured, and the generated common-mode voltage is not easy to deviate from the common-mode reference voltage.

Drawings

Fig. 1 is a schematic structural diagram of a differential operational amplifier according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a connection structure of the first common mode feedback circuit CMFB1 and the second common mode feedback circuit CMFB 2.

Detailed Description

The technical solution in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

As an embodiment, the present invention discloses a differential operational amplifier, which comprises a current mirror circuit, a first-stage amplification circuit, a second-stage amplification circuit and a common-mode feedback circuit; the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit support differential input and differential output; the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit, so that the first-stage amplifying circuit and the second-stage amplifying circuit are connected in a cascade manner; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through the common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier; the output end of the current mirror circuit is connected with the power supply end of the first-stage amplifying circuit to provide a driving signal source for the first-stage amplifying circuit. The input end of the current mirror circuit is used for receiving signals input into the differential operational amplifier from the outside, and the current mirror circuit comprises at least one pair of differential input signals so as to adapt to the differential amplification requirement of the two-stage amplification circuit.

In some embodiments, the first-stage amplification circuit and the second-stage amplification circuit are connected to the same common-mode feedback circuit, so that the complexity of the circuit structure is reduced compared with a common-mode feedback circuit of two-stage operational amplifier; in other embodiments, the same common-mode feedback circuit may be equivalent to two independent conventional common-mode feedback structures, which serve as the first-stage amplification circuit and the second-stage amplification circuit, respectively, and do not involve the problem of port multiplexing of the differential input terminal and the differential output terminal.

Preferably, a differential interface between the common mode feedback circuit and the differential output end of the first-stage amplification circuit is different from a differential interface between the common mode feedback circuit and the differential output end of the second-stage amplification circuit; the differential input end of the common mode feedback circuit connected with the differential output end of the first-stage amplification circuit is different from the differential input end of the common mode feedback circuit connected with the differential output end of the second-stage amplification circuit; the output terminal to which the common mode feedback circuit is connected to the feedback terminal of the current mirror circuit is different from the output terminal to which the common mode feedback circuit is connected to the feedback terminal of the current mirror circuit, and the common mode feedback circuit is configured as a circuit in which there are four differential input terminals and two output terminals.

As an embodiment, as shown in fig. 1, the differential operational amplifier includes a current mirror circuit, a first stage amplification circuit, a second stage amplification circuit, a first common mode feedback circuit, and a second common mode feedback circuit; the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit all support differential input and differential output; the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit, so that the first-stage amplifying circuit and the second-stage amplifying circuit are connected in a cascade manner; the differential output end of the first-stage amplifying circuit is further connected to the feedback end of the current mirror circuit through the first common mode feedback circuit to stabilize the level of the current-stage output, and then the current mirror circuit and the first-stage amplifying circuit preferably form a complete amplifier. The differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a second common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier; the first positive input end of the differential operational amplifier, the first negative input end of the differential operational amplifier, the second positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are input ends of a current mirror circuit, and are correspondingly two pairs of differential input ends; the output end of the current mirror circuit is connected with the power supply end of the first-stage amplifying circuit and provides a driving signal source for the first-stage amplifying circuit; therefore, a first loop of the first-stage amplifying circuit and the first common-mode feedback circuit and a second loop of the second-stage amplifying circuit and the second common-mode feedback circuit are formed, the first loop and the second loop maintain the stability of the differential signal output by the differential operational amplifier together, and the differential output of the first-stage amplifying circuit and the differential output of the second-stage amplifying circuit can be stabilized to a reasonable and same common-mode level.

Compared with the prior art, the operational amplifier is designed into the operational amplifier with four input ends, and supports two pairs of differential inputs and one pair of differential outputs, so that a current mirror load structure exists, and a common mode feedback circuit is connected, so that a working loop of a first-stage amplification circuit, a second-stage amplification circuit and the common mode feedback circuit can be formed; because only two-stage amplification circuits are designed, the driving capability of the operational amplifier is improved on the premise of ensuring that the complexity of the circuit is not high, the stability of amplified signals is ensured, and the generated common-mode voltage is not easy to deviate from the common-mode reference voltage.

It should be noted that the differential operational amplifier is a four-input operational amplifier, wherein the positive input end of the differential operational amplifier includes a first positive input end of the differential operational amplifier and a second positive input end of the differential operational amplifier, and the negative input end of the differential operational amplifier includes a first negative input end of the differential operational amplifier and a second negative input end of the differential operational amplifier; optionally, a first positive input terminal of the differential operational amplifier and a second negative input terminal of the differential operational amplifier are used for accessing a pair of differential signals to be processed, and corresponding to fig. 1, the first positive input terminal of the differential operational amplifier is used for receiving a differential signal VIP1, and the second negative input terminal of the differential operational amplifier is used for receiving a differential signal VIN 2; the first negative input end of the differential operational amplifier and the second positive input end of the differential operational amplifier are both connected with a common-mode reference voltage. The power supply accessed by the power supply end of the second-stage amplifying circuit is equal to the power supply VDD accessed by the power supply end of the current mirror circuit; the ground terminal of the second-stage amplification circuit and the ground terminal of the first-stage amplification circuit share a ground GND. In the embodiment, the differential operational amplifier is designed as an operational amplifier with four input ends, and supports two pairs of differential inputs and one pair of differential outputs so as to adapt to the stability requirement of the differential input and output; therefore, the input impedance of the differential operational amplifier is improved on the premise of ensuring that the circuit complexity is not high.

Preferably, the first common-mode feedback circuit and the second common-mode feedback circuit can be regarded as two independent common-mode feedback circuits, wherein the two common-mode feedback circuits support a differential input and a single-ended output; the first common mode feedback circuit and the second common mode feedback circuit can also be combined into a whole circuit module, namely, one common mode feedback circuit is formed; the differential input end of the first common mode feedback circuit is connected with the differential output end of the first amplifying circuit, and the output end of the first common mode feedback circuit is connected with the current mirror circuit to form the first loop; the differential input end of the second common mode feedback circuit is connected with the differential output end of the second amplifying circuit, and the output end of the second common mode feedback circuit is connected with the second amplifying circuit to form the second loop circuit.

In some embodiments, the current mirror circuit may be an MOS type current mirror circuit, and accordingly, the first-stage amplification circuit and the second-stage amplification circuit are both connected by MOS transistors, and particularly, a two-stage amplification circuit is configured by an inverter structure; the current mirror circuit may also be a triode type current mirror, and accordingly, the first stage amplification circuit and the second stage amplification circuit are both connected by a triode. When the current mirror circuit is an MOS type current mirror circuit, the channel length modulation effect in the current mirror circuit is inhibited, wherein the substrates of the relevant PMOS tubes in the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit are all connected with a power supply VDD, and the substrates of the relevant NMOS tubes are all connected with a ground wire GND; in addition, when the current mirror circuit is a triode-type current mirror circuit, the early effect in the current mirror circuit is suppressed.

As an embodiment, as shown in fig. 1, the current mirror circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP 6; the gate of the third PMOS transistor MP3 is a first positive input terminal of the differential operational amplifier, and is used for inputting a differential analog signal VIP 1; the gate of the fifth PMOS transistor MP5 is the second positive input terminal of the differential operational amplifier, and is used for inputting a differential analog signal VIP 2; the gate of the fourth PMOS transistor MP4 is a first negative input terminal of the differential operational amplifier and is used for inputting the differential analog signal VIN1, and the gate of the sixth PMOS transistor is a second negative input terminal of the differential operational amplifier and is used for inputting the differential analog signal VIN 2. It should be noted that the source of the first PMOS transistor MP1 is the first power supply terminal of the current mirror circuit, and the source of the second PMOS transistor MP2 is the second power supply terminal of the current mirror circuit; the power supply end of the current mirror circuit comprises a first power supply end of the current mirror circuit and a second power supply end of the current mirror circuit. The drain electrode of the third PMOS transistor MP3 is connected to the drain electrode of the fifth PMOS transistor MP5, and the connection node between the drain electrode of the third PMOS transistor MP3 and the drain electrode of the fifth PMOS transistor MP5 is the first output end of the current mirror circuit, providing a current source for a pair of differential MOS transistors arranged inside the first-stage amplification circuit; the drain electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the sixth PMOS transistor MP6, and the connection node between the drain electrode of the fourth PMOS transistor MP4 and the drain electrode of the sixth PMOS transistor MP6 is the second output end of the current mirror circuit, and provides a current source for the other pair of differential MOS transistors of the first-stage amplification circuit, thereby forming a current mirror load structure and improving the driving capability of the first-stage amplification circuit; the output end of the current mirror circuit comprises a first output end of the current mirror circuit and a second output end of the current mirror circuit. A source electrode of the third PMOS transistor MP3 and a source electrode of the fourth PMOS transistor MP4 are both connected to a drain electrode of the first PMOS transistor MP1, and a source electrode of the fifth PMOS transistor MP5 and a source electrode of the sixth PMOS transistor MP6 are both connected to a drain electrode of the second PMOS transistor MP 2; the grid electrode of the first PMOS transistor MP1 is a first feedback end of the current mirror circuit and is used for receiving a common-mode feedback control signal Vfb 1; the gate of the second PMOS transistor MP2 is the second feedback terminal of the current mirror circuit, and is used for receiving the common mode feedback control signal Vfb 1. The grid electrode of the first PMOS transistor MP1 and the grid electrode of the second PMOS transistor MP2 are both connected to the output end of the first common mode feedback circuit, and the feedback end of the current mirror circuit includes the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit, so that a working loop of the current mirror circuit, the first-stage amplifying circuit and the first common mode feedback circuit is formed, and as long as the loop is ensured to be stable, the voltage average value (common mode voltage) of the differential signal output by the first-stage amplifying circuit is equal to the common mode reference voltage.

As an embodiment, as shown in fig. 1, the first-stage amplifying circuit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM 4; the source of the seventh PMOS transistor MP7 is the first power supply end of the first-stage amplifying circuit, and the first power supply end of the first-stage amplifying circuit is connected to the first output end of the current mirror circuit; the source electrode of the eighth PMOS transistor MP8 is the second power supply end of the first-stage amplifying circuit, and the second power supply end of the first-stage amplifying circuit is connected to the second output end of the current mirror circuit; the gate of the seventh PMOS transistor MP7 is connected to a first bias voltage Vb1 provided by the outside to provide a bias current for the seventh PMOS transistor MP7, wherein when the first bias voltage Vb1 is a constant voltage, a constant bias current is generated in the branch where the seventh PMOS transistor MP7 is located; the gate of the eighth PMOS transistor MP8 is connected to a first bias voltage Vb1 provided by the outside to provide a bias current for the eighth PMOS transistor MP8, wherein when the first bias voltage Vb1 is a constant voltage, a constant bias current is generated in the branch where the eighth PMOS transistor MP8 is located; the power supply end of the first-stage amplifying circuit comprises a first power supply end of the first-stage amplifying circuit and a second power supply end of the first-stage amplifying circuit; the output of the current mirror circuit includes a first output of the current mirror circuit and a second output of the current mirror circuit. The drain of the seventh PMOS transistor MP7 is connected to the drain of the first NMOS transistor NM1, and the gate of the first NMOS transistor NM1 is connected to a second bias voltage Vb2 provided by the outside world, so as to provide a bias current for the first NMOS transistor NM 1; the source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to a third bias voltage Vb3 provided by the outside world, so as to provide a bias current for the third NMOS transistor NM3, and the source of the third NMOS transistor NM3 is grounded to GND; necessarily, the substrate of the first NMOS transistor NM1 and the substrate of the third NMOS transistor NM3 are both grounded GND. The drain of the eighth PMOS transistor MP8 is connected to the drain of the second NMOS transistor NM 2; the gate of the second NMOS transistor NM2 is connected to a second bias voltage Vb2 provided by the outside world, so as to provide a bias current for the second NMOS transistor NM 2; the source of the second NMOS transistor NM2 is connected to the drain of the fourth NMOS transistor NM 4; the gate of the fourth NMOS transistor NM4 is connected to a third bias voltage Vb3 provided by the outside to provide a bias current for the fourth NMOS transistor NM 4; the source of the fourth NMOS transistor NM4 is grounded GND. Necessarily, the substrate of the second NMOS transistor NM2 and the substrate of the fourth NMOS transistor NM4 are both grounded GND. A connection node 41 between the drain of the seventh PMOS transistor MP7 and the drain of the first NMOS transistor NM1 is a positive output terminal of the first stage of the amplifying circuit, and is used for outputting a differential output signal VOP 1; a connection node 42 between the drain of the eighth PMOS transistor MP8 and the drain of the second NMOS transistor NM2 is a negative output terminal of the first stage of the amplifying circuit, and is used for outputting a differential output signal VON 1; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit. The average of the differential output signal VON1 and the differential output signal VOP1, i.e., the common-mode voltage of the differential output signal VON1 and the differential output signal VOP1, is regulated and stabilized to the common-mode reference voltage by the first common-mode feedback circuit.

In the foregoing embodiment, as shown in fig. 1, the first bias voltage Vb1, the second bias voltage Vb2 and the third bias voltage Vb3 are different from each other, so as to form a voltage difference between different pairs of MOS transistors; among the first bias voltage, the second bias voltage and the third bias voltage, the voltage difference between any two bias voltages is kept constant, so that the voltage difference is kept constant, and the channel length modulation effect is favorably inhibited. It should be noted that the first bias voltage, the second bias voltage, and the third bias voltage are all provided by corresponding bias voltage sources. It should be noted that the bias voltage source may also be implemented by a voltage regulator device or a voltage regulator circuit. This embodiment is not limited thereto. For the input power circuit, the bias voltage can be designed to be stable to the ground voltage.

As can be known from fig. 2, the positive output terminal of the first-stage amplifier circuit and the negative output terminal of the first-stage amplifier circuit are respectively connected to the differential input terminals (including the positive input terminal and the negative input terminal) of the first common-mode feedback circuit, the positive input terminal of the first common-mode feedback circuit CMFB1 is configured to receive the differential output signal VOP1 output by the positive output terminal of the first-stage amplifier circuit, and the negative input terminal of the first common-mode feedback circuit CMFB1 is configured to receive the differential output signal VON1 output by the negative output terminal of the first-stage amplifier circuit. The first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit are both connected to the output end of the first common mode feedback circuit CMFB1, and the first common mode feedback circuit CMFB1 provides a feedback control signal Vfb1 for the first feedback end and the second feedback end of the current mirror circuit to adjust the differential output result of the first-stage amplification circuit, specifically, to make the common mode voltage output by the first-stage amplification circuit equal to the common mode reference voltage Vcom. It should be noted that the feedback terminal of the current mirror circuit includes a first feedback terminal of the current mirror circuit and a second feedback terminal of the current mirror circuit. When the working loops of the current mirror circuit, the first-stage amplifying circuit and the first common-mode feedback circuit are stable, the differential output result of the first-stage amplifying circuit is stable to the common-mode reference voltage, so that the voltage of a differential output signal VOP1 is equal to the common-mode reference voltage, and the voltage of a differential output signal VON1 is equal to the common-mode reference voltage.

As an embodiment, as shown in fig. 1, the second-stage amplifying circuit includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM 6; the source electrode of the ninth PMOS transistor MP9 is connected to the first power supply terminal of the current mirror circuit, and is used for accessing a power supply VDD; the gate of the ninth PMOS transistor MP9 is a positive input terminal of the second-stage amplifier circuit, and the gate of the ninth PMOS transistor MP9 is connected to the positive output terminal of the first-stage amplifier circuit, and is configured to receive the differential signal VOP1 output by the positive output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit, so that the second-stage amplifier circuit is cascade-connected to the first-stage amplifier circuit, and the output of the first-stage amplifier circuit can be used as a bias signal of the second-stage amplifier circuit to control the second-stage amplifier circuit, and then the input impedance of the differential operational amplifier is improved due to the cascade structure of the multi-stage amplifier circuit. The source of the fifth NMOS transistor NM5 is grounded GND; the drain of the ninth PMOS transistor MP9 is connected to the drain of the fifth NMOS transistor NM5, and the connection node between the drain of the ninth PMOS transistor MP9 and the drain of the fifth NMOS transistor NM5 is the positive output terminal of the second stage amplification circuit, and is used for outputting a differential output signal VOP2 as a differential signal output by the positive output terminal of the differential operational amplifier. A source electrode of the tenth PMOS transistor MP10 is connected to the second power supply terminal of the current mirror circuit, and is connected to the power supply VDD; the gate of the tenth PMOS transistor MP10 is the negative input terminal of the second-stage amplifier circuit, and the gate of the tenth PMOS transistor MP10 is connected to the negative output terminal of the first-stage amplifier circuit, and is configured to receive the differential signal VON1 output by the negative output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit, so that the second-stage amplifier circuit is cascade-connected to the first-stage amplifier circuit, and the input impedance of the differential operational amplifier is improved due to the cascade structure of the multi-stage amplifier circuit. The source of the sixth NMOS transistor NM6 is grounded; the drain of the tenth PMOS transistor MP10 is connected to the drain of the sixth NMOS transistor NM6, and the connection node between the drain of the tenth PMOS transistor MP10 and the drain of the sixth NMOS transistor NM6 is the negative output terminal of the second stage amplifier circuit, and is used for outputting a differential output signal VON2 as the differential signal output by the negative output terminal of the differential operational amplifier. As can be seen from fig. 1 and fig. 2, the positive output terminal of the second-stage amplifier circuit and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminals (including the positive input terminal and the negative input terminal) of the second common-mode feedback circuit; a positive input terminal of the second common mode feedback circuit CMFB2 is configured to receive the differential output signal VOP2 output by the positive output terminal of the second stage amplifier circuit, and a negative input terminal of the second common mode feedback circuit CMFB2 is configured to receive the differential output signal VON2 output by the negative output terminal of the second stage amplifier circuit. The gate of the fifth NMOS 5 is the first feedback end of the second-stage amplification circuit, the gate of the fourth NMOS 4 is the second feedback end of the second-stage amplification circuit, the first feedback end of the second-stage amplification circuit and the second feedback end of the second-stage amplification circuit are both connected to the output end of the second common-mode feedback circuit, and the second common-mode feedback circuit CMFB2 provides a feedback control signal Vfb2 for the first feedback end and the second feedback end of the second-stage amplification circuit, so as to adjust the differential output result of the second-stage amplification circuit, and specifically, the common-mode voltage (the voltage average value of the differential output signal VON2 and the differential output signal VOP 2) output by the second-stage amplification circuit is equal to the common-mode reference voltage Vcom. When a working loop formed by the current mirror circuit, the first-stage amplifying circuit, the first common-mode feedback circuit, the second-stage amplifying circuit and the second common-mode feedback circuit is stable, a differential output result of the second-stage amplifying circuit is stable to the common-mode reference voltage, so that the voltage of a differential output signal VOP2 is equal to the common-mode reference voltage, and the voltage of a differential output signal VON2 is equal to the common-mode reference voltage. In summary, in the foregoing embodiment, the output of the first stage amplifier circuit provides a bias for the input of the second stage amplifier circuit, and the two stages of amplifier circuits have respective common mode feedback circuits connected in a matching manner to adjust the differential signal output by the present stage operational amplifier, so that the corresponding common mode voltage is equal to the common mode reference voltage, wherein the two stages of amplifier circuits can share the current of the current mirror circuit, thereby improving the input impedance of the differential operational amplifier, further improving the overall gain, and expanding the output range.

It should be noted that the feedback end of the current mirror circuit includes a first feedback end of the current mirror circuit and a second feedback end of the current mirror circuit; the differential input end of the second-stage amplification circuit comprises a positive input end of the second-stage amplification circuit and a negative input end of the second-stage amplification circuit; the differential output end of the second-stage amplifying circuit comprises a positive output end of the second-stage amplifying circuit and a negative output end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit; the power supply end of the current mirror circuit comprises a first power supply end of the current mirror circuit and a second power supply end of the current mirror circuit; the feedback end of the second-stage amplifying circuit comprises a first feedback end of the second-stage amplifying circuit and a second feedback end of the second-stage amplifying circuit, and the differential input end of the second-stage amplifying circuit respectively receives the output of the first-stage amplifying circuit and a feedback control signal Vfb2 provided by the second common-mode feedback circuit CMFB 2.

As can be known from fig. 2, the first common mode feedback circuit CMFB1 and the second common mode feedback circuit CMFB2 belong to the same type of common mode feedback structure, the first common mode feedback circuit CMFB1 and the second common mode feedback circuit CMFB2 both access the same common mode reference voltage Vcom, and the first common mode feedback circuit CMFB1 is used for comparing the differential signal output by the first stage amplification circuit with the common mode reference voltage to generate a feedback control signal to the feedback end of the current mirror circuit, so that the outputs of the differential operational amplifier are stabilized to the same common mode level, that is, the differential signal output by the first stage amplification circuit is stabilized at the common mode reference voltage Vcom, and at least the voltage average value (common mode voltage corresponding to the differential signal) of the differential signal output by the first stage amplification circuit is equal to the common mode reference voltage Vcom; the second common mode feedback circuit CMFB2 is configured to compare the differential signal output by the second stage amplification circuit with the common mode reference voltage, and generate a feedback control signal to the feedback end of the second stage amplification circuit, so that the differential signal output by the second stage amplification circuit is stabilized at the common mode reference voltage Vcom, and at least a voltage average value (common mode voltage corresponding to the differential signal) of the differential signal output by the second stage amplification circuit is equal to the common mode reference voltage Vcom.

It should be noted that the common mode feedback structure can be divided into a continuous time common mode feedback circuit and a switched capacitor common mode feedback circuit according to types; the calibration of the continuous-time common-mode feedback circuit to the output common-mode voltage offset is done continuously. However, the feedback control of the switched capacitor common mode feedback circuit to the output common mode voltage is discrete and is completed in half a clock cycle of each charge transfer, and the calibration is also completed in a repeated half clock cycle. The continuous-time common-mode feedback circuit is mainly applied to a continuous-time circuit, but has the defects of limiting the swing of a differential-mode output signal, increasing a differential-mode load, increasing static power consumption, detecting common-mode voltage nonlinearity and the like. Switched capacitor common mode feedback circuits have advantages in these respects but are not suitable for use in continuous time circuits because of the introduction of clock coupling and discrete operating states that can cause glitches in the differential output signal. Switched capacitor common mode feedback circuits have been successfully applied in data sampling systems, particularly in fully differential switched capacitor circuits. Specifically, the common mode feedback circuit is generally divided into two parts: the common mode detection circuit and the comparison amplifier circuit detect output common mode voltage through the common mode detection circuit, then the input comparison amplifier circuit is compared with the pre-specified common mode reference voltage, the difference value of the input comparison amplifier circuit and the pre-specified common mode reference voltage is amplified and returned to the original circuit to correct the offset of the output common mode voltage.

As an embodiment, when the voltage average value of the differential signal output by the differential output terminal of the first stage amplifying circuit is greater than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal, pulls down the voltage average value of the differential signal output by the first stage amplifying circuit to reach the common-mode reference voltage, and makes the voltage average value be stably equal to the common-mode reference voltage; when the average value of the differential signals output by the first-stage amplifying circuit is smaller than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal, the voltage average value of the differential signals output by the first-stage amplifying circuit is pulled high to reach the common-mode reference voltage, and the voltage average value is stably equal to the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input first-stage amplifying circuit cannot reach the expected voltage value in the production process due to process deviation or other factors, and the common-mode feedback circuit is required to adjust the average voltage value of the output differential signal, i.e. the common-mode voltage, to the expected voltage, i.e. the common-mode reference voltage.

As a second embodiment, when the voltage of the first differential signal output by the differential output terminal of the first stage amplifying circuit is greater than the common-mode reference voltage and the voltage of the second differential signal output by the first stage amplifying circuit is less than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal, pulls down the voltage of the first differential signal output by the first stage amplifying circuit to reach the common-mode reference voltage, simultaneously pulls up the voltage of the second differential signal output by the first stage amplifying circuit to reach the common-mode reference voltage, and makes the adjusted voltage of the first differential signal and the adjusted voltage of the second differential signal both equal to the common-mode reference voltage and keep stable to the common-mode reference voltage.

In one embodiment, the first common-mode feedback circuit is configured to generate a feedback control signal to a feedback end of the current mirror circuit, so as to adjust a voltage average of the differential signal output by the first stage of amplifying circuit to be equal to the common-mode reference voltage.

As a third implementation manner, when the voltage average value of the differential signal output by the differential output terminal of the second-stage amplification circuit is greater than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal, pulls down the voltage average value of the differential signal output by the second-stage amplification circuit to reach the common-mode reference voltage, and enables the voltage average value to be stably equal to the common-mode reference voltage; when the voltage average value of the differential signal output by the second-stage amplifying circuit is smaller than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal, the voltage average value of the differential signal output by the second-stage amplifying circuit is pulled high to reach the common-mode reference voltage, and the voltage average value can be stably equal to the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input second stage amplifying circuit usually cannot reach the expected voltage value during the production process due to process deviation or other factors, and the common mode feedback circuit is required to adjust the voltage average value of the output differential signal, i.e. the common mode voltage, to the expected voltage, i.e. the common mode reference voltage.

As an embodiment of the fourth aspect, when the voltage of the first differential signal output by the differential output terminal of the second stage amplification circuit is greater than the common-mode reference voltage, and the voltage of the second differential signal output by the second stage amplification circuit is less than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal, pulls down the voltage of the first differential signal output by the second stage amplification circuit to reach the common-mode reference voltage, and simultaneously pulls up the voltage of the second differential signal output by the second stage amplification circuit to reach the common-mode reference voltage, and then makes the adjusted voltage of the first differential signal and the adjusted voltage of the second differential signal both equal to the common-mode reference voltage and keep stable at the common-mode reference voltage.

In summary to the third and fourth embodiments, the second common mode feedback circuit is configured to generate a feedback control signal to the feedback end of the second stage amplification circuit, so as to adjust a voltage average value of the differential signal output by the second stage amplification circuit to be equal to the common mode reference voltage.

Based on the foregoing embodiment, the present invention also discloses a chip, the inside of which is provided with the differential operational amplifier of the foregoing embodiment, the differential operational amplifier can be applied to the front stage (or the input stage) of the chip as the first stage amplifier in the driving amplifier or the analog-to-digital converter (ADC), and at this time, the differential operational amplifier determines the signal gain of the chip and the signal stability of the chip at the output stage. Preferably, the differential input end and the output end of the differential operational amplifier can construct an adder, a subtracter, an integrator and an operational architecture suitable for the currently called operational function through an external resistor and a capacitor.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, it should be understood by those skilled in the art that: the invention can be modified or equivalent substituted for some technical features; without departing from the spirit of the present invention, it should be understood that the scope of the claims is intended to cover all such modifications and variations.

Claims (10)

1. The differential operational amplifier is characterized by comprising a current mirror circuit, a first-stage amplifying circuit, a second-stage amplifying circuit and a common-mode feedback circuit; the current mirror circuit, the first-stage amplifying circuit and the second-stage amplifying circuit all support differential input and differential output;

the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a common-mode feedback circuit;

the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a common-mode feedback circuit; the differential output end of the second-stage amplifying circuit is the output end of the differential operational amplifier;

the output end of the current mirror circuit is connected with the power supply end of the first-stage amplifying circuit; the input end of the current mirror circuit is used for receiving signals input into the differential operational amplifier from the outside.

2. The differential operational amplifier of claim 1, wherein the common mode feedback circuit comprises a first common mode feedback circuit and a second common mode feedback circuit;

the differential output end of the first-stage amplifying circuit is correspondingly connected with the differential input end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit is also connected to the feedback end of the current mirror circuit through a first common-mode feedback circuit;

the differential output end of the second-stage amplifying circuit is connected to the feedback end of the second-stage amplifying circuit through a second common-mode feedback circuit; the differential output end of the second stage amplifying circuit is the output end of the differential operational amplifier.

3. The differential operational amplifier of claim 2, wherein the differential operational amplifier is a four-input operational amplifier, wherein the positive input terminals of the differential operational amplifier comprise a first positive input terminal of the differential operational amplifier and a second positive input terminal of the differential operational amplifier, and wherein the negative input terminals of the differential operational amplifier comprise a first negative input terminal of the differential operational amplifier and a second negative input terminal of the differential operational amplifier;

the first positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are used for accessing a pair of differential signals to be processed;

the first negative input end of the differential operational amplifier and the second positive input end of the differential operational amplifier are both connected with a common-mode reference voltage;

the first positive input end of the differential operational amplifier, the first negative input end of the differential operational amplifier, the second positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are input ends of a current mirror circuit;

the power supply accessed by the power supply end of the second-stage amplifying circuit is equal to the power supply accessed by the power supply end of the current mirror circuit; the ground terminal of the second-stage amplification circuit and the ground terminal of the first-stage amplification circuit share a ground line.

4. The differential operational amplifier of claim 3, wherein the current mirror circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

the grid electrode of the third PMOS tube is the first positive input end of the differential operational amplifier, the grid electrode of the fifth PMOS tube is the second positive input end of the differential operational amplifier, the grid electrode of the fourth PMOS tube is the first negative input end of the differential operational amplifier, and the grid electrode of the sixth PMOS tube is the second negative input end of the differential operational amplifier;

the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the connection node of the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube is the first output end of the current mirror circuit; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the connection node of the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube is the second output end of the current mirror circuit; the output end of the current mirror circuit comprises a first output end of the current mirror circuit and a second output end of the current mirror circuit;

the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are both connected to the drain electrode of the first PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected to the drain electrode of the second PMOS tube;

the grid electrode of the first PMOS tube is a first feedback end of the current mirror circuit, the grid electrode of the second PMOS tube is a second feedback end of the current mirror circuit, and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with the output end of the first common mode feedback circuit; the feedback end of the current mirror circuit comprises a first feedback end of the current mirror circuit and a second feedback end of the current mirror circuit;

the source electrode of the first PMOS tube is a first power supply end of the current mirror circuit, and the source electrode of the second PMOS tube is a second power supply end of the current mirror circuit; the power supply terminal of the current mirror circuit comprises a first power supply terminal of the current mirror circuit and a second power supply terminal of the current mirror circuit.

5. The differential operational amplifier of claim 3, wherein the first stage amplifying circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the source electrode of the seventh PMOS tube is a first power supply end of the first-stage amplifying circuit, and the first power supply end of the first-stage amplifying circuit is connected with the first output end of the current mirror circuit; the source electrode of the eighth PMOS tube is a second power supply end of the first-stage amplifying circuit, and the second power supply end of the first-stage amplifying circuit is connected with the second output end of the current mirror circuit; the grid electrode of the seventh PMOS tube is connected with a first bias voltage provided by the outside; the grid electrode of the eighth PMOS tube is connected with a first bias voltage provided by the outside; the power supply end of the first-stage amplifying circuit comprises a first power supply end of the first-stage amplifying circuit and a second power supply end of the first-stage amplifying circuit; the output end of the current mirror circuit comprises a first output end of the current mirror circuit and a second output end of the current mirror circuit;

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with second bias voltage provided by the outside, the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with third bias voltage provided by the outside, and the source electrode of the third NMOS tube is grounded;

the drain electrode of the eighth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with second bias voltage provided by the outside, the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with third bias voltage provided by the outside, and the source electrode of the fourth NMOS tube is grounded;

the connection node of the drain electrode of the seventh PMOS tube and the drain electrode of the first NMOS tube is the positive output end of the first-stage amplification circuit, and the connection node of the drain electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube is the negative output end of the first-stage amplification circuit; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit;

the positive output end of the first-stage amplifying circuit and the negative output end of the first-stage amplifying circuit are respectively connected with the differential input end of the first common-mode feedback circuit, and the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit are both connected with the output end of the first common-mode feedback circuit so as to adjust the differential output result of the first-stage amplifying circuit; the feedback end of the current mirror circuit comprises a first feedback end of the current mirror circuit and a second feedback end of the current mirror circuit.

6. The differential operational amplifier of claim 3, wherein the second stage amplifying circuit comprises a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor;

the source electrode of the ninth PMOS tube is connected with the first power supply end of the current mirror circuit, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the ninth PMOS tube is the positive input end of the second-stage amplification circuit, the grid electrode of the ninth PMOS tube is connected with the positive output end of the first-stage amplification circuit, and the source electrode of the fifth NMOS tube is grounded; the connection node of the drain electrode of the ninth PMOS tube and the drain electrode of the fifth NMOS tube is the positive output end of the second-stage amplification circuit;

the source electrode of the tenth PMOS tube is connected with the second power supply end of the current mirror circuit, the drain electrode of the tenth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the tenth PMOS tube is the negative input end of the second-stage amplification circuit, the grid electrode of the tenth PMOS tube is connected with the negative output end of the first-stage amplification circuit, and the source electrode of the sixth NMOS tube is grounded; the connection node of the drain electrode of the tenth PMOS tube and the drain electrode of the sixth NMOS tube is the negative output end of the second-stage amplification circuit;

the positive output end of the second-stage amplifying circuit and the negative output end of the second-stage amplifying circuit are respectively connected with the differential input end of the second common-mode feedback circuit; the grid electrode of the fifth NMOS tube is a first feedback end of the second-stage amplification circuit, the grid electrode of the fourth NMOS tube is a second feedback end of the second-stage amplification circuit, and the first feedback end of the second-stage amplification circuit and the second feedback end of the second-stage amplification circuit are both connected with the output end of the second common-mode feedback circuit so as to adjust the differential output result of the second-stage amplification circuit;

the differential input end of the second-stage amplification circuit comprises a positive input end of the second-stage amplification circuit and a negative input end of the second-stage amplification circuit; the differential output end of the second-stage amplifying circuit comprises a positive output end of the second-stage amplifying circuit and a negative output end of the second-stage amplifying circuit; the differential output end of the first-stage amplifying circuit comprises a positive output end of the first-stage amplifying circuit and a negative output end of the first-stage amplifying circuit; the power supply end of the current mirror circuit comprises a first power supply end of the current mirror circuit and a second power supply end of the current mirror circuit; the feedback end of the second-stage amplifying circuit comprises a first feedback end of the second-stage amplifying circuit and a second feedback end of the second-stage amplifying circuit.

7. The differential operational amplifier of claim 5, wherein the first bias voltage, the second bias voltage, and the third bias voltage are mutually different to form a voltage difference between different pairs of MOS transistors;

wherein a voltage difference of any two bias voltages among the first bias voltage, the second bias voltage, and the third bias voltage is kept constant; the first bias voltage, the second bias voltage, and the third bias voltage are all provided by respective bias voltage sources.

8. The differential operational amplifier of claim 2, wherein the first common mode feedback circuit and the second common mode feedback circuit belong to the same type of common mode feedback structure, and the first common mode feedback circuit and the second common mode feedback circuit are connected to the same common mode reference voltage, so that the outputs of the differential operational amplifier are stabilized to the same common mode level.

9. The differential operational amplifier of claim 8, wherein the first common-mode feedback circuit is configured to generate a feedback control signal to a feedback terminal of the current mirror circuit to adjust a voltage average of the differential signal output from the first stage amplification circuit to be equal to the common-mode reference voltage;

the second common mode feedback circuit is used for generating a feedback control signal to a feedback end of the second-stage amplifying circuit so as to regulate the voltage average value of the differential signal output by the second-stage amplifying circuit to be equal to the common mode reference voltage.

10. A chip, characterized in that a differential operational amplifier according to any one of claims 1 to 9 is present inside the chip.

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