CN106026938A - Fully differential comparator - Google Patents
Fully differential comparator Download PDFInfo
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- CN106026938A CN106026938A CN201610345328.6A CN201610345328A CN106026938A CN 106026938 A CN106026938 A CN 106026938A CN 201610345328 A CN201610345328 A CN 201610345328A CN 106026938 A CN106026938 A CN 106026938A
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- field effect
- effect transistor
- drain electrode
- feedback path
- grid
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
Abstract
The invention discloses a fully differential comparator comprising a differential input stage and a differential output stage, wherein the differential input stage comprises a positive feedback path, a negative feedback path and a bias field effect transistor; the differential output stage comprises a positive output unit and a negative output unit; external differential signals are input into both the negative feedback path and the positive feedback path; the negative feedback path and the positive feedback path are respectively connected with the positive feedback path, a drain of the bias field effect transistor, the positive output unit and the negative output unit; an external fixed bias voltage is input into a grid of the bias field effect transistor; a source of the bias field effect transistor is grounded; the bias field effect transistor provides bias currents for the positive feedback path and the negative feedback path; the positive feedback path and the negative feedback path amplify the input differential signals and output the differential signals to the differential output stage; the positive output unit outputs a differentially amplified positive signal; and the negative output unit outputs a differentially amplified negative signal. According to the fully differential comparator of the invention, the power consumption and area of the circuit are reduced, the noise resistance capacity of the amplifier is enhanced, and the gain of the comparator is increased.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of fully differential comparator.
Background technology
Refer to the circuit structure diagram that Fig. 1, Fig. 1 are prior art fully differential comparator.As it can be seen, this electricity
Route dual-stage amplifier cascade forms, and the first order is that metal-oxide-semiconductor M1, M2, M3, M4, M5 are constituted
Difference amplifier, the second level is that the common source being made up of metal-oxide-semiconductor M6 and M7, M8 and M9 respectively amplifies
Device is constituted.In the middle of the first order, N-type metal-oxide-semiconductor M1, M2 are as inputting the difference of its gate node pipe
Voltage signal △ Vi (△ Vi=Vip-Vin), converts and flows through its drain electrode differential current signal △ I1 (△ I1=I1-I2), its
Middle △ I1 meets following relation:
The Δ I1=gm1* Δ Vi mutual conductance of metal-oxide-semiconductor M1 (gm1 be)
Differential current signal △ I1 is converted into its drain electrode as current mirror load and saves by p-type metal-oxide-semiconductor M3, M4
The differential voltage signal △ Vo1 (△ Vo1=Vd2-Vd1) of point.△ Vo1 meets following relation:
Δ Vo1=Δ I1* (ro1//ro3) the small-signal resistance of M1, M3 (ro1, the ro3 represent respectively)
N-type metal-oxide-semiconductor M5 provides direct current biasing for first order difference amplifier.P-type metal-oxide-semiconductor M3,
The drain node of M4 is respectively connecting to input p-type metal-oxide-semiconductor M7 and the p-type of second level common-source amplifier
On the grid of metal-oxide-semiconductor M9, differential voltage signal △ Vo1 is converted into the difference flowing through its drain terminal by M7 and M9
Divide electric current △ I2 (△ I2=I6-I7), and be again converted to differential voltage letter by current mirror load M6 and M8
Number △ Vo2 (△ Vo2=Vop-Von), and by the positive pole of outfan and negative pole difference output.Wherein △ Vo1,
△ Vo2, △ I2 meet following relation:
(ro1, ro3 represent the little letter of M6, M7 to Δ Vo2=Δ I2* (ro6//ro7)=Δ Vo1*gm7* (ro6//ro7) respectively
Number resistance, gm7 represents the mutual conductance of M7)
N-type metal-oxide-semiconductor M5, M6, M8 are biased on external voltage VBN, p-type metal-oxide-semiconductor M3,
M4 is biased on external voltage VBP.For ensureing the differential characteristic of this circuit, metal-oxide-semiconductor M1 and M2, M3
And M4, M7 and M9, the model of M6 with M8 is the most identical with size.Under DC state, this fully differential ratio
The gain of relatively device is
Av=gm1* (ro3//ro1) * gm7* (ro6//ro7)
But, the grid of current mirror load M3 and M4 of foregoing circuit first order difference amplifier needs external
Bias voltage VBP, this voltage swing must be by being total to of carrying out sampling to the meansigma methods of M1, M2 drain voltage
Cmfb circuit determines, otherwise the output common mode voltage of first order difference amplifier can be because flowing through the straight of M3
Not mating and cannot determine, so that compare between stream bias current and the DC bias current flowing through M1
Device cannot normally work；And the introducing of common mode feedback circuit can consume extra power consumption, increase the area of circuit
And reduce the gain of comparator.It addition, the Differential Input transform voltages of this comparator is 0, i.e. work as input
During differential voltage △ Vi>0, △ Vo2 is high level, when △ Vi<when 0, exports △ Vo2 low level.Work as △
When the size of Vi is near 0, if input node Vip or Vin are by circuit noise either internally or externally
Interference, cause △ Vi produce 0 near be equal to noise amplitude vibration, then this comparator will directly because of
Export the low and high level signal purely caused by noise for noise, cause the distortion of comparator output signal,
As in figure 2 it is shown, in fig. 2, V1 is low level, and V2 is high level, and V3 is level during △ Vi=0,
Fig. 2 A is the oscillogram being not affected by noise jamming, and Fig. 2 B is the oscillogram disturbed by noise as；Therefore,
It is more weak that this amplifier supports antimierophonic ability.When this circuit is not static work (i.e. having AC signal to input)
Under the conditions of, metal-oxide-semiconductor M6, the M8 in the circuit of the second level is acted on by external fixed voltage biasing VBN,
Fixed bias current can be produced, thus add certain power consumption.
Therefore, it is necessary to provide the fully differential comparator of a kind of improvement to overcome drawbacks described above.
Summary of the invention
It is an object of the invention to provide a kind of fully differential comparator, the fully differential comparator of the present invention, save
The power consumption of circuit and area, enhance amplifier and support antimierophonic ability, add the gain of comparator.
For achieving the above object, the invention provides a kind of fully differential comparator, including differential input stage and difference
Dividing output stage, described differential input stage includes positive feedback path, negative feedback path and biasing field effect transistor, institute
Stating differential output stage and include positive output unit and negative output unit, external difference signal all inputs described negative feedback
Path and positive feedback path, described negative feedback path, positive feedback path respectively with positive feedback path, biasing
The drain electrode of field effect transistor, positive output unit, negative output unit connect, and an outside fixed bias voltage inputs institute
Stating the grid of biasing field effect transistor, the source ground of described biasing field effect transistor, described biasing field effect transistor is
Described positive feedback path and negative feedback path provide bias current, described positive feedback path and negative feedback path pair
The differential signal of input is amplified and exports to described differential output stage, and described positive output unit exports through difference
Divide the positive signal after amplifying, described negative output unit output negative signal after differential amplification.
It is preferred that described positive feedback path includes the first field effect transistor, the second field effect transistor, the 3rd field effect
Guan Yu tetra-field effect transistor, outside forward signal inputs the grid of described first field effect transistor, outside negative sense letter
Number input the grid of described second field effect transistor, the source electrode of described first field effect transistor and the second field effect transistor
Source electrode jointly connects and is connected with the drain electrode of described biasing field effect transistor, and the drain electrode of described first field effect transistor divides
It is not connected with described negative feedback path, the drain electrode of the 4th field effect transistor, negative output unit, the second field effect transistor
Drain electrode be connected with described negative feedback path, the drain electrode of the 3rd field effect transistor, positive output unit respectively, described
The source electrode of the 3rd field effect transistor and the source electrode of the 4th field effect transistor are all connected with external power source, described 3rd effect
Should the grid of pipe and the grid of the 4th field effect transistor all be connected with described negative feedback path.
It is preferred that described negative feedback path includes, the first field effect transistor, the second field effect transistor, the 5th effect
Guan Yu six field effect transistor, the source electrode of described first field effect transistor and the source electrode of the second field effect transistor is answered jointly to connect
Connecing and be connected with the drain electrode of described biasing field effect transistor, the drain electrode of described first field effect transistor is respectively with described
The grid of five field effect transistor, the drain electrode of the 5th field effect transistor, the drain electrode of the 4th field effect transistor, negative output unit
Connect, the drain electrode of the second field effect transistor respectively with the grid of described 6th field effect transistor, the 6th field effect transistor
Drain electrode, the drain electrode of the 3rd field effect transistor, positive output unit connect, the source electrode of described 5th field effect transistor and the
The source electrode of six field effect transistor is all connected with external power source, and the grid of described 5th field effect transistor, drain electrode are all with the
The grid of three field effect transistor connects, the grid of described 6th field effect transistor, drain electrode all with the 4th field effect transistor
Grid connects.
It is preferred that described negative output unit includes the 7th field effect transistor, the 8th field effect transistor, the 9th field effect
Pipe and the tenth field effect transistor, the source electrode of described 7th field effect transistor and the source electrode of the 8th field effect transistor are all with outside
Power supply connects, and the grid of described 7th field effect transistor is connected with the drain electrode of described first field effect transistor, and described the
The drain electrode of seven field effect transistor is connected with drain electrode, the grid of described 9th field effect transistor；Described 8th field effect transistor
Grid be connected with the drain electrode of described second field effect transistor, the drain electrode and the described tenth of described 8th field effect transistor
The drain electrode of field effect transistor connects and exports negative signal；The grid of described 9th field effect transistor and the tenth field effect transistor
Grid connect, the source electrode of described 9th field effect transistor and the source grounding of the tenth field effect transistor.
It is preferred that described positive output unit include the 11st field effect transistor, the 12nd field effect transistor, the 13rd
Field effect transistor and the 14th field effect transistor, the source electrode of described 11st field effect transistor and the 12nd field effect transistor
Source electrode is all connected with external power source, the grid of described 11st field effect transistor and the leakage of described second field effect transistor
Pole connects, and the drain electrode of described 11st field effect transistor is connected with drain electrode, the grid of described 13rd field effect transistor；
The grid of described 12nd field effect transistor is connected with the grid of described first field effect transistor, described 12nd effect
The drain electrode of pipe should be connected with the drain electrode of described 14th field effect transistor and export positive signal；Described 13rd effect
Should the grid of the grid of pipe and the 14th field effect transistor connect, the source electrode and the tenth of described 13rd field effect transistor
The source grounding of four field effect transistor.
It is preferred that described first field effect transistor and the second field effect transistor have an identical architectural feature, described
Three field effect transistor and the 4th field effect transistor have identical architectural feature, described 5th field effect transistor and the 6th
Effect pipe has identical architectural feature, and described 7th field effect transistor and the 11st field effect transistor have identical
Architectural feature, described 8th field effect transistor and the 12nd field effect transistor have an identical architectural feature, and described
Nine field effect transistor and the 13rd field effect transistor have identical architectural feature, described tenth field effect transistor and the tenth
Four field effect transistor have identical architectural feature.
It is preferred that described first field effect transistor and the second field effect transistor are N-type field effect transistor, described 5th
Effect pipe, the 7th field effect transistor, the 8th field effect transistor, the 11st field effect transistor, the 12nd field effect transistor are P
Type field effect transistor.
Compared with prior art, connect except the fully differential comparator of the present invention beyond bias voltage VBN, no longer
Need other external bias voltage, it is not necessary to common mode feedback circuit, save power consumption and the area of circuit；Increase
Strong amplifier supports antimierophonic ability so that circuit output signal will not be because of the noise signal of input port
Change；And reduce the static working current in the circuit of the second level, increase the gain of comparator further.
By description below and combine accompanying drawing, the present invention will become more fully apparent, and these accompanying drawings are used for explaining
Embodiments of the invention.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the fully differential comparator of prior art.
Fig. 2 has the output waveform figure of the fully differential comparator of technology.
Fig. 3 is the circuit structure diagram of fully differential comparator of the present invention.
Fig. 4 is the fully differential comparator of the present invention output waveform figure by noise jamming.
Detailed description of the invention
With reference now to accompanying drawing, describing embodiments of the invention, element numbers similar in accompanying drawing represents similar unit
Part.As it has been described above, the invention provides a kind of fully differential comparator, save power consumption and the area of circuit,
Enhance amplifier and support antimierophonic ability, add the gain of comparator.
Refer to the circuit structure diagram that Fig. 3, Fig. 3 are fully differential comparator of the present invention.As it can be seen, the present invention
Fully differential comparator include that differential input stage and differential output stage, described differential input stage include positive and negative feedthrough
Road, negative feedback path and biasing field effect transistor Ms；Described differential output stage includes positive output unit and negative output
Unit.External difference signal (Vip, Vin) all inputs described negative feedback path and positive feedback path, described negative
Feedback network, positive feedback path respectively with positive feedback path, biasing the drain electrode of field effect transistor Ms, positive output
Unit, negative output unit connect, thus the difference that outside is inputted by described positive feedback path and negative feedback path
Signal (Vip, Vin) carries out differential amplification and exports to described differential output stage.An outside fixed bias voltage
VBN inputs the grid of described biasing field effect transistor Ms, the source ground of described biasing field effect transistor Ms, institute
State biasing field effect transistor Ms and provide bias current for described positive feedback path with negative feedback path, described to ensure
Positive feedback path works with the normal of negative feedback path.Described positive output unit output after differential amplification just
Signal outp, described negative output unit output negative signal outn after differential amplification.As it has been described above, this
Connect except bright fully differential comparator beyond bias voltage VBN, it is no longer necessary to other external bias voltage, no
Need common mode feedback circuit, save power consumption and the area of circuit；Boster supports antimierophonic ability,
Circuit output signal will not be changed because of the noise signal of input port；And reduce described difference
Divide the static working current in output-stage circuit, increase the gain of comparator further.
Specifically:
Described positive feedback path includes the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor
M3 and the 4th field effect transistor M4, outside forward signal Vip inputs the grid of described first field effect transistor M1,
Outside negative-going signal Vin inputs the grid of described second field effect transistor M2, described first field effect transistor M1
The source electrode of source electrode and the second field effect transistor M2 connects and with the drain electrode of described biasing field effect transistor Ms even jointly
Connect, the drain electrode of described first field effect transistor M1 respectively with described negative feedback path, the 4th field effect transistor M4
Drain electrode, negative output unit connect, the drain electrode of the second field effect transistor M2 respectively with described negative feedback path, the 3rd
The drain electrode of field effect transistor M3, positive output unit connect, the source electrode of described 3rd field effect transistor M3 and the 4th
The source electrode of effect pipe M4 is all connected with external power source VDD, the grid of described 3rd field effect transistor M3 and
The grid of four field effect transistor M4 is all connected with described negative feedback path.Described negative feedback path includes, first
Effect pipe M1, the second field effect transistor M2, the 5th field effect transistor M5 and the 6th field effect transistor M6, described
The source electrode of one field effect transistor M1 and the source electrode of the second field effect transistor M2 connects jointly and with described bias-field effect
The drain electrode of pipe Ms connects, the drain electrode of described first field effect transistor M1 respectively with described 5th field effect transistor M5
Grid, the drain electrode of the 5th field effect transistor M5, the drain electrode of the 4th field effect transistor M4, negative output unit connect,
The drain electrode of the second field effect transistor M2 respectively with grid, the 6th field effect transistor of described 6th field effect transistor M6
The drain electrode of M6, the drain electrode of the 3rd field effect transistor M3, positive output unit connect, described 5th field effect transistor
The source electrode of M5 and the source electrode of the 6th field effect transistor M6 are all connected with external power source VDD, described 5th effect
Should the grid of pipe M5, drain electrode all grids with the 3rd field effect transistor M3 be connected, described 6th field effect transistor
The grid of M6, drain electrode all grids with the 4th field effect transistor M4 are connected.
Described negative output unit includes the 7th field effect transistor M7, the 8th field effect transistor M8, the 9th field effect transistor
M9 and the tenth field effect transistor M10, the source electrode of described 7th field effect transistor M7 and the 8th field effect transistor M8
Source electrode is all connected with external power source VDD, the grid of described 7th field effect transistor M7 and described first field effect
The drain electrode of pipe M1 connects, the drain electrode of described 7th field effect transistor M7 and the leakage of described 9th field effect transistor M9
Pole, grid connect；The grid of described 8th field effect transistor M8 connects with the drain electrode of described second field effect transistor M2
Connecing, the drain electrode of described 8th field effect transistor M8 is connected with the drain electrode of described tenth field effect transistor M10 and exports
Negative signal outn；The grid of described 9th field effect transistor M9 and the grid of the tenth field effect transistor M10 connect,
The source electrode of described 9th field effect transistor M9 and the source grounding of the tenth field effect transistor M10.
Described positive output unit include the 11st field effect transistor M11, the 12nd field effect transistor M12, the 13rd
Field effect transistor M13 and the 14th field effect transistor M14, the source electrode and the tenth of described 11st field effect transistor M11
The source electrode of two field effect transistor M12 is all connected with external power source VDD, described 11st field effect transistor M11
Grid is connected with the drain electrode of described second field effect transistor M2, the drain electrode of described 11st field effect transistor M11 with
The drain electrode of described 13rd field effect transistor M12, grid connect；The grid of described 12nd field effect transistor M12
Being connected with the grid of described first field effect transistor M1, the drain electrode of described 12nd field effect transistor M12 is with described
The drain electrode of the 14th field effect transistor M14 connects and exports positive signal outp；Described 13rd field effect transistor M13
Grid and the 14th field effect transistor M14 grid connect, the source electrode of described 13rd field effect transistor M13 with
The source grounding of the 14th field effect transistor M14.
As the preferred embodiment of the present invention, described first field effect transistor M1 and the second field effect transistor M2 tool
Identical architectural feature, described 3rd field effect transistor M3 and the 4th field effect transistor M4 is had to have identical structure
Feature, described 5th field effect transistor M5 and the 6th field effect transistor M6 have an identical architectural feature, and described
Seven field effect transistor M7 and the 11st field effect transistor M11 have identical architectural feature, described 8th field effect
Pipe M8 and the 12nd field effect transistor M12 have an identical architectural feature, described 9th field effect transistor M9 and
13rd field effect transistor M13 has identical architectural feature, described tenth field effect transistor M10 and the 14th
Effect pipe M14 has identical architectural feature；So that the full-differential circuits of full invention is symmetrical, can
Effectively suppress common-mode signal, it is ensured that the precision of output signal.
Please in conjunction with reference to Fig. 3, the operation principle of fully differential comparator of the present invention described:
First field effect transistor M1 of N-type field effect transistor, the second field effect transistor M2 be the input of input stage to pipe,
By differential voltage input signal △ Vi, (△ Vi is the potential difference of input differential signal Vip and Vin, i.e. △
Vi=Vip-Vin) be converted into flow through its drain electrode differential current signal △ I1 (△ I1=I1-I2), and △ I1 meet below
Relation:
The Δ I1=gm1* Δ Vi mutual conductance of the first field effect transistor M1 (gm1 be)
5th field effect transistor M5 of p-type field effect transistor is the automatic biasing load transistor that grid is connected with drain electrode,
It provides biasing without external voltage, and differential current signal △ I1 can be converted to the difference output letter of the first order
Number △ Vo1 (△ Vo1=Vd2-Vd1),
△ Vo1 meets following relation:
Δ Vo1=Δ I1*Rk(RkFor by the first field effect transistor M1, the 3rd field effect transistor M3 and the 5th field effect transistor
The constant that the size of M5 and electrical characteristics together decide on)
The differential input stage of fully differential comparator of the present invention has lagging characteristics, and so-called lagging characteristics refers to that it is poor
Divide and input the function that transform voltages is input voltage.The most in the present invention, when △ Vi is more than 0, turn
Break voltage is a constant VTRP+ more than 0, i.e. during and if only if △ Vi > VTRP+, comparator is defeated
Go out and become high from low.When △ Vi is less than 0, transform voltages is a constant VTRP-less than 0, i.e.
< during VTRP-, comparator output is become low from height for and if only if △ Vi.In the present invention, have | VTRP+ |=
| VTRP-|=VTRP, during the size of the noise amplitude suffered when VTRP is positioned at 0 more than △ Vi, compares
Device output △ Vo2 (△ Vo2=outp-outn) will not change because of noise (as shown in Figure 4, V1
For low level, V2 is high level, and V3 is level during △ Vi=0, and as is noise).
From the foregoing, the differential input stage of the present invention has positive feedback path and negative feedback path: negative anti-
In feedthrough road, the existence of the 5th field effect transistor M5 and the 6th field effect transistor M6 pipe can suppress △ Vo1 with input
The change of △ Vi, making its degeneration factor is β 1, then have
β 1 ∝ gm5 (∝ represents direct proportion, and gm5 is the mutual conductance of the 5th field effect transistor M5)
In positive feedback path, the existence of the 3rd field effect transistor M3 and the 4th field effect transistor M4 can strengthen △ Vo1
With the change of input △ Vi, making its positive feedback coefficient is β 2, then have
The β 2 ∝ gm3 mutual conductance of the 3rd field effect transistor M3 (gm3 be)
When β 2 > β 1, circuit shows lagging characteristics, VTRP > 0, and the size of VTRP is proportional to
Gm3/gm5, i.e.
Therefore this circuit can change circuit for the resistance of noise by adjusting the ratio of gm3 and gm5,
Anti-interference with intensifier circuit.
P-type field effect transistor the 7th field effect transistor M7, the 8th field effect transistor M8, the 11st field effect transistor M11,
The input port that grid is differential output stage of the present invention of the 12nd field effect transistor M12.This differential output stage will
The differential voltage signal △ Vo1 of differential input stage output amplifies output further, forms the difference that comparator is final
Output signal △ Vo2 (△ Vo2=outp-outn).△ Vo2 meets following relation:
Δ Vo2=G* Δ Vo1 (G is the gain of differential output stage of the present invention, by the 7th field effect transistor M7, the 8th
Field effect transistor M8, the 11st field effect transistor M11, the size of the 12nd field effect transistor M12 and electrical characteristics are altogether
With uniquely determining).
In sum, the differential comparator of the present invention, it is not necessary to external voltage VBN is biased, it is not necessary to
Consuming fixing quiescent current, save power consumption, the most described differential output stage have employed push-pull configuration, adopts
During with same device, differential output stage has bigger gain.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in disclosed above
Embodiment, and amendment, the equivalent combinations that the various essence according to the present invention is carried out should be contained.
Claims (7)
1. a fully differential comparator, including differential input stage and differential output stage, it is characterised in that described
Differential input stage includes positive feedback path, negative feedback path and biasing field effect transistor, described differential output stage bag
Including positive output unit and negative output unit, external difference signal all inputs described negative feedback path and positive and negative feedthrough
Road, described negative feedback path, positive feedback path respectively with positive feedback path, biasing field effect transistor drain electrode,
Positive output unit, negative output unit connect, and an outside fixed bias voltage inputs described biasing field effect transistor
Grid, the source ground of described biasing field effect transistor, described biasing field effect transistor be described positive feedback path with
Negative feedback path provides bias current, described positive feedback path to enter the differential signal of input with negative feedback path
Row amplifies and exports to described differential output stage, and described positive output unit exports the positive signal after differential amplification,
Described negative output unit output negative signal after differential amplification.
2. fully differential comparator as claimed in claim 1, it is characterised in that described positive feedback path includes
First field effect transistor, the second field effect transistor, the 3rd field effect transistor and the 4th field effect transistor, outside forward signal
Inputting the grid of described first field effect transistor, outside negative-going signal inputs the grid of described second field effect transistor,
The source electrode of described first field effect transistor and the source electrode of the second field effect transistor connects jointly and with described bias-field effect
The drain electrode of pipe connects, the drain electrode of described first field effect transistor respectively with described negative feedback path, the 4th field effect
The drain electrode of pipe, negative output unit connect, the drain electrode of the second field effect transistor respectively with described negative feedback path, the
The drain electrode of three field effect transistor, positive output unit connect, the source electrode of described 3rd field effect transistor and the 4th field effect
The source electrode of pipe is all connected with external power source, the grid of described 3rd field effect transistor and the grid of the 4th field effect transistor
All it is connected with described negative feedback path.
3. fully differential comparator as claimed in claim 2, it is characterised in that described negative feedback path includes,
First field effect transistor, the second field effect transistor, the 5th field effect transistor and the 6th field effect transistor, described first effect
Should the source electrode of pipe and the source electrode of the second field effect transistor connects jointly and with the drain electrode of described biasing field effect transistor even
Connect, the drain electrode of described first field effect transistor respectively with grid, the 5th field effect transistor of described 5th field effect transistor
Drain electrode, the drain electrode of the 4th field effect transistor, negative output unit connect, the drain electrode of the second field effect transistor respectively with
The grid of described 6th field effect transistor, the drain electrode of the 6th field effect transistor, the drain electrode of the 3rd field effect transistor, the most defeated
Going out unit to connect, the source electrode of described 5th field effect transistor and the source electrode of the 6th field effect transistor are all with external power source even
Connecing, the grid of described 5th field effect transistor, drain electrode all grids with the 3rd field effect transistor are connected, and the described 6th
The grid of field effect transistor, drain electrode all grids with the 4th field effect transistor are connected.
4. fully differential comparator as claimed in claim 3, it is characterised in that described negative output unit includes
7th field effect transistor, the 8th field effect transistor, the 9th field effect transistor and the tenth field effect transistor, described 7th effect
Should the source electrode of pipe and the source electrode of the 8th field effect transistor all be connected with external power source, the grid of described 7th field effect transistor
Pole is connected with the drain electrode of described first field effect transistor, the drain electrode of described 7th field effect transistor and described 9th effect
Should the drain electrode of pipe, grid connection；The grid of described 8th field effect transistor and the drain electrode of described second field effect transistor
Connecting, the drain electrode of described 8th field effect transistor is connected with the drain electrode of described tenth field effect transistor and exports negative signal；
The grid of described 9th field effect transistor and the grid of the tenth field effect transistor connect, the source of described 9th field effect transistor
Pole and the source grounding of the tenth field effect transistor.
5. fully differential comparator as claimed in claim 4, it is characterised in that described positive output unit includes
11st field effect transistor, the 12nd field effect transistor, the 13rd field effect transistor and the 14th field effect transistor, described
The source electrode of the 11st field effect transistor and the source electrode of the 12nd field effect transistor are all connected with external power source, and the described tenth
The grid of one field effect transistor is connected with the drain electrode of described second field effect transistor, the leakage of described 11st field effect transistor
Pole is connected with drain electrode, the grid of described 13rd field effect transistor；The grid of described 12nd field effect transistor and institute
The grid stating the first field effect transistor connects, the drain electrode of described 12nd field effect transistor and described 14th field effect
The drain electrode of pipe connects and exports positive signal；The grid of described 13rd field effect transistor and the 14th field effect transistor
Grid connects, the source electrode of described 13rd field effect transistor and the source grounding of the 14th field effect transistor.
6. fully differential comparator as claimed in claim 5, it is characterised in that described first field effect transistor and
Second field effect transistor has identical architectural feature, and described 3rd field effect transistor and the 4th field effect transistor have phase
Same architectural feature, described 5th field effect transistor and the 6th field effect transistor have identical architectural feature, described
7th field effect transistor and the 11st field effect transistor have identical architectural feature, described 8th field effect transistor and
12 field effect transistor have identical architectural feature, and described 9th field effect transistor and the 13rd field effect transistor have
Identical architectural feature, described tenth field effect transistor and the 14th field effect transistor have identical architectural feature.
7. fully differential comparator as claimed in claim 6, it is characterised in that described first field effect transistor with
Second field effect transistor is N-type field effect transistor, described 5th field effect transistor, the 7th field effect transistor, the 8th effect
Ying Guan, the 11st field effect transistor, the 12nd field effect transistor are p-type field effect transistor.
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| CN201610345328.6A CN106026938A (en) | 2016-05-23 | 2016-05-23 | Fully differential comparator |
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| CN201610345328.6A CN106026938A (en) | 2016-05-23 | 2016-05-23 | Fully differential comparator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788279A (en) * | 2016-12-01 | 2017-05-31 | 北京航空航天大学 | A kind of low sensitivity substrate input amplifier |
| CN110568896A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(北京)有限公司 | Comparator, integrated circuit and method |
| CN113489462A (en) * | 2021-07-29 | 2021-10-08 | 北京京东方传感技术有限公司 | Voltage amplification circuit, sensor and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013884A (en) * | 2006-11-24 | 2007-08-08 | 华中科技大学 | Unilateral hysteresis comparator |
| CN101277095A (en) * | 2007-03-26 | 2008-10-01 | 三星电子株式会社 | Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier |
| CN102769447A (en) * | 2012-07-12 | 2012-11-07 | 东南大学 | Fully-differential high-speed low-power-consumption comparator |
| CN103973273A (en) * | 2013-01-24 | 2014-08-06 | 西安电子科技大学 | High-speed high-precision low-detuning fully differential dynamic comparator |
-
2016
- 2016-05-23 CN CN201610345328.6A patent/CN106026938A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013884A (en) * | 2006-11-24 | 2007-08-08 | 华中科技大学 | Unilateral hysteresis comparator |
| CN101277095A (en) * | 2007-03-26 | 2008-10-01 | 三星电子株式会社 | Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier |
| CN102769447A (en) * | 2012-07-12 | 2012-11-07 | 东南大学 | Fully-differential high-speed low-power-consumption comparator |
| CN103973273A (en) * | 2013-01-24 | 2014-08-06 | 西安电子科技大学 | High-speed high-precision low-detuning fully differential dynamic comparator |
Non-Patent Citations (1)
| Title |
|---|
| 冯楚华: "一种用于数字功放的低功耗宽输入电压比较器", 《微电子学与计算机》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788279A (en) * | 2016-12-01 | 2017-05-31 | 北京航空航天大学 | A kind of low sensitivity substrate input amplifier |
| CN106788279B (en) * | 2016-12-01 | 2020-02-14 | 北京航空航天大学 | Low-sensitivity substrate input amplifier |
| CN110568896A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(北京)有限公司 | Comparator, integrated circuit and method |
| CN110568896B (en) * | 2018-06-05 | 2021-01-05 | 中芯国际集成电路制造(北京)有限公司 | Comparator, integrated circuit and method |
| CN113489462A (en) * | 2021-07-29 | 2021-10-08 | 北京京东方传感技术有限公司 | Voltage amplification circuit, sensor and electronic equipment |
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