CN106788279A - A kind of low sensitivity substrate input amplifier - Google Patents
A kind of low sensitivity substrate input amplifier Download PDFInfo
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- CN106788279A CN106788279A CN201611095402.XA CN201611095402A CN106788279A CN 106788279 A CN106788279 A CN 106788279A CN 201611095402 A CN201611095402 A CN 201611095402A CN 106788279 A CN106788279 A CN 106788279A
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- 238000005457 optimization Methods 0.000 description 18
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/38—Positive-feedback circuit arrangements without negative feedback
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/114—Indexing scheme relating to amplifiers the amplifier comprising means for electro-magnetic interference [EMI] protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45116—Feedback coupled to the input of the differential amplifier
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Abstract
This application discloses a kind of low sensitivity substrate input amplifier, the electromagnetic performance defect that existing substrate input amplifier is present is solved.The present invention includes at least one positive feedback structure, and optimal enforcement example is improvement positive feedback structure, comprising the first positive feedback structure and filter circuit.Further, amplifier of the present invention includes the second positive feedback structure.Embodiments of the invention further comprise biasing circuit, filter circuit, symmetrical output-stage circuit.The present invention improves the anti-EMI filter performance of circuit.
Description
Technical field
The present invention relates to electronic circuit field, and in particular to a kind of amplifier with electromagnetism interference performance.
Background technology
In wearable intelligent electronic product, biomedical micro-nano device, implanted brain-machine interaction microsystem, low-voltage
Low dissipation amplifier is crucial.For prolonged periods continuation of the journey etc. is required, it is necessary to design the Low-voltage Low-power with superperformance
Amplifier.In current low voltage amplifier technology, substrate input technology is input into amplitude of oscillation because it is wide, is suitable to the work under extremely low voltage
The advantages of making is widely used by low voltage designs.
But, the equivalent transconductance of the substrate input mos transistor in traditional substrate input amplifier is generally than equal bar
The mutual conductance of grid driving transistor is much lower under part, and then causes the performance degradations such as low cut-off frequency, low DC gains, low signal-to-noise ratio.
Because electromagnetic susceptibility is high, when by electromagnetic interference, it is impossible to efficient operation, even cannot normal work.
The content of the invention
A kind of low sensitivity substrate input amplifier of disclosure, solves the electromagnetism that existing substrate input amplifier is present
Performance deficiency.
The embodiment of the present application provides a kind of low sensitivity substrate input amplifier, comprising at least one positive feedback structure；Institute
State positive feedback structure and include the 11st transistor, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor and the 23rd
Transistor；11st transistor, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor and the 23rd transistor
It is PMOS transistor；The substrate of the 11st transistor, the 12nd transistor and the 13rd transistor is connected, used as the first substrate
End；The substrate of the 21st transistor, the 22nd transistor and the 23rd transistor is connected, used as the second substrate terminal；Described 11st is brilliant
Body pipe, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor, the source electrode of the 23rd transistor are connected, used as total
Source terminal；The drain electrode of the 11st transistor, the 12nd transistor drain, the grid of the 12nd transistor, the grid of the 13rd transistor,
The grid of the 21st transistor is connected, extreme as the first grid；Drain electrode, the 22nd transistor drain, the 22nd of the 21st transistor
The grid of transistor, the grid of the 23rd transistor, the grid of the 11st transistor are connected, extreme as second gate；Described 13rd is brilliant
The drain electrode of body pipe is the first drain electrode end；The drain electrode of the 23rd transistor is the second drain electrode end.
Used as the embodiment of further optimization of the invention, the low sensitivity substrate input amplifier includes improvement positive feedback
Structure, the improvement positive feedback structure includes a filter circuit and first positive feedback structure (referred to as first positive feedback knot
Structure)；The filter circuit includes first resistor, second resistance, the first electric capacity, the second electric capacity, the first lining source electric capacity and the second lining
Source electric capacity；The terminating differential signal positive input terminal of the first resistor one, another termination the first substrate terminal of the first positive feedback structure；Institute
State the first capacitance cathode and connect first the first substrate terminal of positive feedback structure, negative pole ground connection；The first lining source electric capacity one terminates described
Total source terminal, another termination the first substrate terminal of the first positive feedback structure；The terminating differential signal negative input end of the second resistance one,
First the second substrate terminal of positive feedback structure of another termination；Second capacitance cathode connects first the second substrate terminal of positive feedback structure,
Negative pole is grounded；The second lining source electric capacity one terminates total source terminal, another termination the second substrate terminal of the first positive feedback structure.
Preferably, the value of the first resistor and the second resistance is 500k Ω；First electric capacity and the second electric capacity
Value be 200fF；The value of the first lining source electric capacity and the second lining source electric capacity is 3pF.
Used as the embodiment of further optimization of the invention, the low sensitivity substrate input amplifier is improved just comprising described
Feedback arrangement, also comprising second positive feedback structure (referred to as the second positive feedback structure)；First positive feedback structure
First drain electrode end of the first drain electrode end and the second positive feedback structure is connected；Second drain electrode end of first positive feedback structure and
Second drain electrode end of two positive feedback structures is connected；The first grid of first positive feedback structure is extreme and the second positive feedback structure
The first grid is extremely connected；Extreme and the second positive feedback structure the extreme phase of second gate of the second gate of first positive feedback structure
Even；The differential signal positive input terminates the first substrate terminal of the second positive feedback structure；Differential signal negative input termination the
Second substrate terminal of two positive feedback structures.
In the further embodiment of optimization of the invention, also comprising biasing circuit；The biasing circuit includes the 6th crystal
Pipe, the 14th transistor, the 24th transistor；6th transistor is PMOS transistor；14th transistor and the 24th transistor
It is nmos pass transistor；The source electrode of the 6th transistor connects operating voltage, and grid connects bias voltage, drain electrode and total source electrode
End is connected；The source ground of the 14th transistor, grid connects below-center offset voltage, and it is extreme that drain electrode connects the first grid；Described
The source ground of the 24th transistor, grid connects below-center offset voltage, and it is extreme that drain electrode connects the second gate.
As the embodiment of further optimization of the invention, also comprising symmetrical output-stage circuit；The symmetrical output-stage circuit
Comprising the 31st transistor, the 32nd transistor, the 41st transistor, the 42nd transistor；41st transistor, the 42nd transistor are
PMOS transistor；31st transistor, the 32nd transistor are nmos pass transistor；The drain electrode of the 31st transistor connects described
The drain electrode of 41 transistors, grid connects first drain electrode end, source ground；It is brilliant that the drain electrode of the 32nd transistor connects the described 42nd
The drain electrode of body pipe, grid connects second drain electrode end, source ground；The grid of the 41st transistor is connected with drain electrode, source electrode
Connect operating voltage；The grid of the 42nd transistor is connected with the grid of the 41st transistor, and source electrode connects operating voltage；It is described
The drain electrode of the 32nd transistor is used as output voltage terminal VO。
As the embodiment of further optimization of the invention, also comprising active pull-up circuit；The active pull-up circuit is included
15th transistor, the 25th transistor；15th transistor, the 25th transistor are nmos pass transistor；15th transistor
Grid is connected with drain electrode and connects first drain electrode end, source ground；The grid of the 25th transistor with drain electrode be connected,
And connect second drain electrode end, source ground.
Used as the embodiment of further optimization of the invention, the biasing circuit further includes the 7th transistor, the 8th crystal
Pipe, the 9th transistor, the 10th transistor, the 5th transistor, current source；7th transistor, the 9th transistor, the 10th transistor are
PMOS transistor；8th transistor, the 5th transistor are nmos pass transistor；The source electrode of the 6th transistor connects operating voltage,
Drain electrode connects total source terminal；7th transistor source connects total source terminal, and grid connects the drain electrode of the 9th transistor, drain electrode
Connect the drain electrode of the 8th transistor；The source ground of the 8th transistor, grid connects the grid of the 10th transistor；9th crystal
The source electrode of pipe connects operating voltage, and grid is connected with the drain electrode of itself；The source ground of the 10th transistor, grid and the 5th crystalline substance
Body pipe is connected, the drain electrode of drain electrode the 9th transistor of connection.The grid of the 5th transistor is connected with drain electrode, source ground；It is described
Current source positive pole connects operating voltage, and negative pole connects the drain electrode of the 5th transistor；The drain voltage of the 7th transistor, on described
Bias voltage；The grid voltage of the 5th transistor, as the below-center offset voltage.
Above-mentioned at least one technical scheme that the embodiment of the present application is used can reach following beneficial effect：The present invention is proposed
Amplifier be the low-voltage FET amplifier with anti-electromagnetic interference capability, improve former amplifier, use positive feedback knot
Structure improves equivalent transconductance, and while circuit direct performance is improved, when cut-off frequency is also improved the noise of circuit, resists
Electromagnetic interference (EMI) ability strengthens；Because amplifier uses symmetrical export structure so that the overall topology of circuit is highly
Symmetrically, the switching rate of high degree of symmetry is realized, the anti-EMI filter performance of circuit is improved comprehensively.
Brief description of the drawings
Accompanying drawing described herein is used for providing further understanding of the present application, constitutes the part of the application, this Shen
Schematic description and description please does not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 is traditional substrate input amplifier structure chart；
Fig. 2 is the substrate input amplifier structure chart with positive feedback structure of the invention；
Fig. 3 is the substrate input amplifier structure chart with positive feedback structure and filter circuit of the invention；
Fig. 4 is of the invention with positive feedback structure and filter circuit and dual input level substrate input amplifier structure chart；
Fig. 5 is the amplitude versus frequency characte figure of low sensitivity substrate input amplifier of the invention；
Fig. 6 is the DC transfer characteristic curve figures of low sensitivity substrate input amplifier of the invention；
Fig. 7 is the big signal time domain response simulation result figure of low sensitivity substrate input amplifier of the invention；
Fig. 8 is the equivalent offset voltage simulation result figure of input of low sensitivity substrate input amplifier of the invention；
Fig. 9 is the simulation result figure of the output spectrum density (PSD) of low sensitivity substrate input amplifier of the invention.
Specific embodiment
To make the purpose, technical scheme and advantage of the application clearer, below in conjunction with the application specific embodiment and
Corresponding accompanying drawing is clearly and completely described to technical scheme.Obviously, described embodiment is only the application one
Section Example, rather than whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under the premise of creative work, belong to the scope of the application protection.
A kind of some electromagnetic performance defects that the present invention exists for existing substrate input amplifier, it is proposed that low sensitivity
Substrate input amplifier.The structure improves the equivalent inpnt mutual conductance of substrate input stage using positive feedback structure, by being input into partial pressure
The DC characteristic of structural improvement substrate input structure is non-linear, and the good exchange of overall amplifier is ensured using dual input level structure
Characteristic, symmetrical topological structure ensure that the high symmetry of circuit, realize symmetrical switching rate.
Below in conjunction with accompanying drawing, the technical scheme that each embodiment of the application is provided is described in detail.
Fig. 1 is traditional substrate input amplifier structure chart, including the 1st transistor M1, the 2nd transistor M2 are used as main amplification
Device, the 3rd transistor M3 is used as active load；41st transistor M41 and the 42nd transistor M42 are used as symmetrical output stage device；
Vin+ and Vin- are respectively differential signal positive input terminal and differential signal negative input end；Vo is signal output part；IB be for
6th transistor M6 produces the current source of biasing；Operating voltage is VDD, circuit ground is Vss.In traditional substrate input amplifier
Substrate input mos transistor equivalent transconductance (gmb) generally than the mutual conductance (g of grid driving transistor under equal conditionsm) much lower
(such as 1/5~1/2gmb), and then cause low cut-off frequency, low DC current gain, low signal-to-noise ratio and other finiteness energy, so as to lead
Electromagnetic susceptibility higher is caused, when circuit is subject to electromagnetic interference, circuit will be unable to normal work or cannot efficiently work.
Fig. 2 is the substrate input amplifier structure chart with positive feedback structure of the invention.The input of low sensitivity substrate is put
Big device, comprising at least one positive feedback structure；The positive feedback structure includes the 11st transistor M11, the 21st transistor M21, the
12 transistor M12, the 22nd transistor M22, the 13rd transistor M13 and the 23rd transistor M23；11st transistor, the 12nd crystalline substance
Body pipe, the 13rd transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are PMOS transistor；11st crystal
The substrate of pipe, the 12nd transistor and the 13rd transistor is connected, used as the first substrate terminal；21st transistor, the 22nd transistor
Substrate with the 23rd transistor is connected, used as the second substrate terminal；11st transistor, the 12nd transistor, the 13rd transistor,
21 transistors, the 22nd transistor, the source electrode of the 23rd transistor are connected, used as total source terminal；The drain electrode of the 11st transistor,
12 transistor drains, the grid of the 12nd transistor, the grid of the 13rd transistor, the grid of the 21st transistor are connected, used as first
Gate terminal；The drain electrode of the 21st transistor, the 22nd transistor drain, the grid of the 22nd transistor, the grid of the 23rd transistor,
The grid of the 11st transistor is connected, extreme as second gate；The drain electrode of the 13rd transistor is the first drain electrode end；Described 23rd
The drain electrode of transistor is the second drain electrode end.
During for realizing amplifying, differential signal positive input terminal Vin+ connects the first substrate terminal of the positive feedback structure；Difference
Signal negative input end Vin- connects the second substrate terminal of the positive feedback structure.
It should be noted that the present embodiment realizes the principle of positive feedback.The drain voltage of the 12nd transistor feeds back to the 21st
The grid of transistor, the drain voltage of the 22nd transistor feeds back to the grid of the 11st transistor to change the 11st transistor and the 21st
The drain current of transistor, realizes that equivalent inpnt mutual conductance is improved.Analyzed according to small signal equivalent model, equivalent transconductance meets：
Wherein, gm1It is the grid mutual conductance of the 11st transistor (or the 21st transistor), gmb1It is the 11st transistor (or the 21st crystal
Pipe) body mutual conductance, gm2It is the grid mutual conductance of the 12nd transistor (or the 22nd transistor), gmb2It is the 12nd transistor (or the 22nd crystal
Pipe) body mutual conductance, if the ratio between grid mutual conductance of the 12nd transistor M12 and the 11st transistor M11 N, i.e.,ThenThat is the equivalent inpnt mutual conductance of circuit can rise to originalTimes.Equivalent transconductance is carried
Height can improve the DC performance of circuit, noise when cut-off frequency, therefore anti-EMI filter ability strengthens.Additionally, equivalent transconductance is carried
Height, also reduces the modulus value of transfer function to a certain extent, further enhances the Electro Magnetic Compatibility of overall amplifier.
It should be noted that because device mismatch, process variation and temperature change can all cause N values to offset, when N is close
When 1, too strong positive feedback can cause circuit unstable, accordingly, it would be desirable to suitably choosing feedback intensity ensures circuit stability.This
Embodiment takes N equal to 5/4, mutual conductance can be improved into about 10 times, and do not influence the stability of circuit.
In the further embodiment of optimization of the invention, also comprising biasing circuit；The biasing circuit includes the 6th transistor
M6, the 14th transistor M14, the 24th transistor M24；6th transistor is PMOS transistor；14th transistor and the 24th
Transistor is nmos pass transistor；The source electrode of the 6th transistor meets operating voltage VDD, grid connects bias voltage Vb0, drain electrode with
Total source terminal is connected；The source ground V of the 14th transistorSS, grid meets below-center offset voltage Vb, and drain electrode connects described first
Gate terminal；The source ground of the 24th described transistor, grid connects below-center offset voltage, and it is extreme that drain electrode connects the second gate.
As the embodiment of further optimization of the invention, also comprising symmetrical output-stage circuit；The symmetrical output-stage circuit
Comprising the 31st transistor M31, the 32nd transistor M32, the 41st transistor M41, the 42nd transistor M42；41st transistor,
42 transistors are PMOS transistor；31st transistor, the 32nd transistor are nmos pass transistor；The leakage of the 31st transistor
Pole connects the drain electrode of the 41st transistor, and grid connects first drain electrode end, source ground；The drain electrode of the 32nd transistor connects
The drain electrode of the 42nd transistor, grid connects second drain electrode end, source ground；The grid of the 41st transistor and drain electrode
It is connected, source electrode connects operating voltage；The grid of the 42nd transistor is connected with the grid of the 41st transistor, and source electrode connects work
Voltage；The drain electrode of the 32nd transistor is used as output voltage terminal.
As the embodiment of further optimization of the invention, also comprising active pull-up circuit；The active pull-up circuit is included
15th transistor M15, the 25th transistor M25；15th transistor, the 25th transistor are nmos pass transistor；Described 15th is brilliant
The grid of body pipe is connected with drain electrode and connects first drain electrode end, source ground；The grid of the 25th transistor and drain electrode
It is connected and connects second drain electrode end, source ground.
Fig. 3 is substrate input amplifier structure chart of the present invention with positive feedback structure and filter circuit.As the present invention
The embodiment for further optimizing, the low sensitivity substrate input amplifier is positive and negative comprising positive feedback structure, the improvement is improved
Feedback structure includes a filter circuit and first positive feedback structure (referred to as the first positive feedback structure)；First positive feedback
Structure is positive feedback structure as shown in Figure 2；The filter circuit includes first resistor R1, second resistance R2, the first electric capacity C1, the
Two electric capacity C1, the first lining source electric capacity Cbs1 and the second lining source electric capacity Cbs2；The terminating differential signal positive input of the first resistor one
End Vin+, another termination the first substrate terminal of the first positive feedback structure；First capacitance cathode connects the first positive feedback structure first
Substrate terminal, negative pole ground connection；The first lining source electric capacity one terminates total source terminal, the first positive feedback structure of another termination first
Substrate terminal；The terminating differential signal negative input end Vin- of the second resistance one, another termination the second substrate of the first positive feedback structure
End；Second capacitance cathode connects first the second substrate terminal of positive feedback structure, negative pole ground connection；The second lining source electric capacity one is terminated
Total source terminal, another termination the second substrate terminal of the first positive feedback structure.
It should be noted that be connected to the first resistor of differential input end, second resistance can reduce be applied directly to input it is right
Parasitic lining source triode on bias voltage, the resistance of appropriate selection first resistor and second resistance can ensure parasitic triode
All the time reverse-biased is maintained, is not influenceed by substrate input voltage, and then correct the non-linear of amp DC characteristic, improve it
Anti-electromagnetic interference capability.Meanwhile, first resistor, second resistance and circuit equivalent input capacitance CinLow-pass filter structure is constituted, can
Effectively suppress the influence of high-frequency electromagnetic interference.In addition, dropping electric capacity using input voltage, foregoing first lining source electric capacity is referred to
Cbs1, the second lining source electric capacity Cbs2, it is possible to decrease the offset voltage that parasitic capacitance causes, improve circuit in the electromagnetism of whole frequency band and
Capacitive energy.Preferably, the value of the first resistor and the second resistance is 500k Ω；First electric capacity and the second electric capacity
It is 200fF to be worth；The value of the first lining source electric capacity and the second lining source electric capacity is 3pF.
As the embodiment of further optimization, in the embodiment depicted in figure 3, comprising the active load described in Fig. 2 embodiments
Circuit, symmetrical output-stage circuit, biasing circuit.Concrete structure is not repeated.
Fig. 4 is substrate input amplifier structure chart of the present invention with positive feedback structure and filter circuit and dual input level.
It is to be appreciated that after using positive feedback structure and filter circuit, the offset voltage of amplifier is big compared to existing substrate input structure
It is big to reduce.But, due to the larger resistance of resistance and the use of capacitor element, some AC characteristics of amplifier are weakened, such as：
Phase margin and gain bandwidth product.Phase margin deficiency makes circuit produce voltage dithering or point under Transient Electromagnetic interference disturbance
Peak, due to conduction and coupling between circuit module, it in itself and the work of late-class circuit is produced and had a strong impact on, is limited to circuit
The Electro Magnetic Compatibility of integrated circuit or system.If taking such as extra compensation of miller compensation to arrange in foregoing circuit structure
Apply, on the one hand can largely increase area and power consumption, be on the other hand likely to result in circuit asymmetry and
It is non-linear, and then trigger corresponding electromagnetic susceptibility problem.Therefore, the AC characteristic good to ensure overall amplifier, can take
Dual input level structure realizes high electrical-magnetic compatibility.
Used as the embodiment of further optimization of the invention, the low sensitivity substrate input amplifier is improved just comprising described
Feedback arrangement, also comprising second positive feedback structure (referred to as the second positive feedback structure)；Second positive feedback structure is still
It is positive feedback structure as shown in Figure 2；Positive feedback structure is improved described in another embodiment and includes the first positive feedback structure；For this
In embodiment, the first drain electrode end of first positive feedback structure and the first drain electrode end of the second positive feedback structure are connected；It is described
Second drain electrode end of the first positive feedback structure and the second drain electrode end of the second positive feedback structure are connected；First positive feedback structure
The first grid be extremely extremely connected with the first grid of the second positive feedback structure；The second gate of first positive feedback structure it is extreme and
The second gate of the second positive feedback structure is extremely connected；The differential signal positive input terminates the first substrate of the second positive feedback structure
End；The differential signal negative input terminates the second substrate terminal of the second positive feedback structure.
In the present embodiment, first positive feedback structure is used as time input stage；Second positive feedback structure is with deciding
Input stage, forms dual input level structure.
In fig. 4, described input stage embodiment as shown in Figure 2, repeats no more here；Due to the first positive feedback knot
Structure is identical with the second positive feedback structure principle, in order to primary input level element is mutually distinguished with time input stage element, illustrates such as
Under：Second positive feedback structure as primary input level includes 11* transistors M11*, 21* transistors M21*, 12*
Transistor M12*, 22* transistors M22*, 13* transistors M13* and 23* transistors M23*；The 11* transistors,
12* transistors, 13* transistors, 21* transistors, 22* transistors and 23* transistors are PMOS transistor；Institute
The substrate for stating 11* transistors, 12* transistors and 13* transistors is connected, used as the first substrate of the second positive feedback structure
End；The substrate of the 21* transistors, 22* transistors and 23* transistors is connected, used as the of the second positive feedback structure
Two substrate terminals；The 11* transistors, 12* transistors, 13* transistors, 21* transistors, 22* transistors,
The source electrode of 23* transistors is connected, used as total source terminal of the second positive feedback structure；Drain electrode, the 12* of the 11* transistors
Transistor drain, the grid of 12* transistors, the grid of 13* transistors, the grid of 21* transistors are connected, used as second
The first grid of positive feedback structure is extreme；Drain electrode, 22* transistor drains, the grid of 22* transistors of the 21* transistors
Pole, the grid of 23* transistors, the grid of 11* transistors are connected, and the second gate as the second positive feedback structure is extreme；Institute
The drain electrode for stating 13* transistors is the first drain electrode end of the second positive feedback structure；The drain electrode of the 23* transistors is second just
Second drain electrode end of feedback arrangement.
As the embodiment of further optimization, in embodiment described in Fig. 4, comprising the active load described in Fig. 2 embodiments
Circuit, symmetrical output-stage circuit, biasing circuit.Illustrate one by one below.
As general embodiment of the present invention, in embodiment described in Fig. 4, when first positive feedback structure and second just
When sharing an active pull-up circuit of feedback arrangement, the active pull-up circuit includes the 15th transistor M15, the 25th transistor
M25；15th transistor, the 25th transistor are nmos pass transistor；The grid of the 15th transistor with drain electrode be connected and
Connect the first drain electrode end of first positive feedback structure and the second positive feedback structure, source ground；The grid of the 25th transistor
Pole is connected with drain electrode and connects the second drain electrode end of first positive feedback structure and the second positive feedback structure, source ground.
As the embodiment of further optimization of the invention, in embodiment described in Fig. 4, when first positive feedback structure and
When second positive feedback structure is connected to source load circuit, the active pull-up circuit includes the first active pull-up circuit and the
Two active pull-up circuits.
First active pull-up circuit includes the 15th transistor M15, the 25th transistor M25；15th transistor,
25 transistors are nmos pass transistor；The grid of the 15th transistor is connected with drain electrode and connects first positive feedback structure
The first drain electrode end, source ground；The grid of the 25th transistor is connected with drain electrode and connects first positive feedback structure
The second drain electrode end, source ground.
Second active pull-up circuit includes 15* transistors M15*, 25* transistors M25*；The 15* crystal
Pipe, 25* transistors are nmos pass transistor；The grid of the 15* transistors is connected with drain electrode and to connect described second positive and negative
Present the first drain electrode end of structure, source ground；The grid of the 25* transistors is connected and connects described second just with drain electrode
Second drain electrode end of feedback arrangement, source ground.
Comprising the first active pull-up circuit and during the second active pull-up circuit, it is preferable that first positive feedback structure
The first drain electrode end and second positive feedback structure the first drain electrode end connection；Second drain electrode of first positive feedback structure
Second drain electrode end of end and second positive feedback structure is connected.
As general embodiment of the present invention, in embodiment described in Fig. 4, when total source electrode of first positive feedback structure
When total source terminal of end and the second positive feedback structure shares a biasing circuit, the biasing circuit identical with embodiment illustrated in fig. 2
Comprising the 6th transistor M6, the 14th transistor M14, the 24th transistor M24；6th transistor is PMOS transistor；Described
14 transistors and the 24th transistor are nmos pass transistor；The source electrode of the 6th transistor connects operating voltage, and grid connects biased electrical
Pressure Vb0, drain electrode is connected with total source terminal；The source ground of the 14th transistor, grid meets below-center offset voltage Vb, drain electrode
Connect the first grid extreme；The source ground of the 24th described transistor, grid connects below-center offset voltage, and drain electrode connects the second gate
Extremely.
Used as the embodiment of further optimization of the invention, in the embodiment of Fig. 2~4, the biasing circuit is further wrapped
Containing the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the 10th transistor M10, the 5th transistor M5, current source IB；It is described
7th transistor, the 9th transistor, the 10th transistor are PMOS transistor；8th transistor, the 5th transistor are NMOS crystal
Pipe；The source electrode of the 6th transistor connects operating voltage, and drain electrode connects total source terminal；7th transistor source connects described total
Source terminal, grid connects the drain electrode of the 9th transistor, and drain electrode connects the drain electrode of the 8th transistor；The source ground of the 8th transistor, grid
Pole connects the grid of the 10th transistor；The source electrode of the 9th transistor connects operating voltage, and grid is connected with the drain electrode of itself；It is described
The source ground of the 10th transistor, grid is connected with the 5th transistor, the drain electrode of drain electrode the 9th transistor of connection.5th crystal
The grid of pipe is connected with drain electrode, source ground；The current source positive pole connects operating voltage, and negative pole connects the drain electrode of the 5th transistor；Institute
The drain voltage of the 7th transistor is stated, as the upper offset voltage；The grid voltage of the 5th transistor, as described lower inclined
Put voltage.
As the embodiment of further optimization, in embodiment described in Fig. 4, when total source electrode of first positive feedback structure
When total source terminal of end and the second positive feedback structure connects a biasing circuit respectively, in the embodiment of further optimization of the invention
In, the biasing circuit divides into the first biasing circuit and the second biasing circuit.
First biasing circuit includes the 6th transistor, the 14th transistor, the 24th transistor；6th transistor is
PMOS transistor；14th transistor and the 24th transistor are nmos pass transistor；The source electrode of the 6th transistor connects work electricity
Pressure, grid connects the upper offset voltage of the first biasing circuit, and drain electrode is connected with total source terminal of first positive feedback structure；It is described
The source ground of the 14th transistor, grid connects the below-center offset voltage of the first biasing circuit, and drain electrode connects first positive feedback structure
The first grid it is extreme；The source ground of the 24th described transistor, grid connects the below-center offset voltage of the first biasing circuit, and drain electrode connects
The second gate of first positive feedback structure is extreme.
Second biasing circuit includes 6* transistors M6*, 14* transistors M14*, 24* transistors M24*；Institute
6* transistors are stated for PMOS transistor；The 14* transistors and 24* transistors are nmos pass transistor；The 6* is brilliant
The source electrode of body pipe connects operating voltage, and grid connects the upper offset voltage of the second biasing circuit, drain electrode and second positive feedback structure
Total source terminal be connected；The source ground of the 14* transistors, grid connects the below-center offset voltage of the second biasing circuit, drain electrode
The first grid for connecing second positive feedback structure is extreme；The source ground of described 24* transistors, grid connects the second biased electrical
The below-center offset voltage on road, the second gate that drain electrode connects second positive feedback structure is extreme.
Used as the embodiment of further optimization of the invention, first biasing circuit further includes the 7th transistor, the 8th
Transistor, the 9th transistor, the 10th transistor, the 5th transistor, current source；7th transistor, the 9th transistor, the 10th crystal
It is PMOS transistor to manage；8th transistor, the 5th transistor are nmos pass transistor；The source electrode of the 6th transistor connects work
Voltage, drain electrode connects total source terminal of first positive feedback structure；7th transistor source connects first positive feedback structure
Total source terminal, grid connects the drain electrode of the 9th transistor, and drain electrode connects the drain electrode of the 8th transistor；The source electrode of the 8th transistor connects
Ground, grid connects the grid of the 10th transistor；The source electrode of the 9th transistor connects operating voltage, and grid is connected with the drain electrode of itself；
The source ground of the 10th transistor, grid is connected with the 5th transistor, the drain electrode of drain electrode the 9th transistor of connection.Described 5th
The grid of transistor is connected with drain electrode, source ground；The current source positive pole connects operating voltage, and negative pole connects the leakage of the 5th transistor
Pole；The drain voltage of the 7th transistor, the upper offset voltage as first biasing circuit；The grid of the 5th transistor
Pole tension, the below-center offset voltage as first biasing circuit.
As the embodiment of further optimization of the invention, second biasing circuit further comprising 7* transistors M7*,
8* transistors M8*, the 9th transistor, the 10th transistor, the 5th transistor, current source；The 7* transistors, the 9th transistor,
10th transistor is PMOS transistor；The 8* transistors, the 5th transistor are nmos pass transistor；The 6* transistors
Source electrode connects operating voltage, and drain electrode connects total source terminal of second positive feedback structure；The 7* transistor sources connect described
Total source terminal of two positive feedback structures, grid connects the drain electrode of the 9th transistor, and drain electrode connects the drain electrode of 8* transistors；The 8*
The source ground of transistor, grid connects the grid of the 10th transistor；The source electrode of the 9th transistor connects operating voltage, grid with
The drain electrode of itself is connected；The source ground of the 10th transistor, grid is connected with the 5th transistor, drain electrode the 9th transistor of connection
Drain electrode.The grid of the 5th transistor is connected with drain electrode, source ground；The current source positive pole connects operating voltage, and negative pole connects
The drain electrode of the 5th transistor；The drain voltage of the 7* transistors, the upper offset voltage as second biasing circuit；Institute
The grid voltage of the 5th transistor is stated, the below-center offset voltage as second biasing circuit.
Wherein, the 9th transistor, the 10th transistor, the 5th transistor, current source are first biasing circuit and
The shared device of two biasing circuits.
Comprising the first biasing circuit and during the second biasing circuit, it is preferable that the first grid of first positive feedback structure
The first grid of extreme and second positive feedback structure is extremely connected；The second gate of first positive feedback structure is extreme and described
The second gate of the second positive feedback structure is extremely connected.
It is to be appreciated that taken on secondary input stage circuit larger resistance and capacitor element (first resistor, the first electric capacity,
Second resistance, the second electric capacity), to improve the Electro Magnetic Compatibility of overall amplifier.Simultaneously as improved structure be applied to it is time defeated
Enter in level, it will not produce to primary input level circuit and have a strong impact on, and the AC characteristic of amplifier is good.By primary and secondary input stage
Use cooperatively, circuit has sufficient phase margin and suitable gain bandwidth product, without the extra of the forms such as such as miller compensation
Indemnifying measure, effectively prevent the circuit caused by collocation structure asymmetric and non-linear.Meanwhile, amplifier is using symmetrical output
Structure, the overall topology high degree of symmetry of circuit, realizes the switching rate of high degree of symmetry, and the electromagnetism that circuit is improved comprehensively is simultaneous
Hold reliability.In addition, primary and secondary input stage has identical structure composition and transistor size, it is easy to the global design of amplifier
Realize.
Also, it should be noted that in embodiment illustrated in fig. 4, when other characters are identical in mark, the crystal of band " * " mark
Pipe has duplicate parameter with the transistor without " * ", and such as the 11st transistor M11 and 11* transistors M11* has
Completely the same parameter；Mark " 1N " transistor AND gate " 2N " transistor has duplicate parameter (N=1~5), the such as the 11st
Transistor M11 and the 21st transistor M21 have duplicate parameter；Additionally, transistor M31, M32 have duplicate ginseng
Number；Transistor M41, M42 have duplicate parameter.
Also, it should be noted that in whole embodiments of the present invention, if without especially mark, acquiescence NMOS tube substrate connects minimum
Voltage, PMOS substrate connects ceiling voltage.
The main devices example of parameters such as following table of low sensitivity substrate input amplifier of the present invention.
| Device | Parameter | Device | Parameter |
| M11/M21/M11*/M21* | 40μm/1μm | M6 | 500μm/1μm |
| M12/M22/M12*/M22* | 50μm/1μm | M32/M31 | 40μm/2μm |
| M13/M23/M13*/M23* | 50μm/1μm | M42/M41 | 120μm/2μm |
| M14/M24/M14*/M24* | 40μm/2μm | R1/R2 | 500kΩ |
| M15/M25/M15*/M25* | 40μm/2μm | C1/C2 | 200fF |
| M5 | 40μm/2μm | Cbs1/Cbs2 | 3pF |
Fig. 5 is the amplitude versus frequency characte figure of low sensitivity substrate input amplifier of the invention；The low sensitivity lining of the present embodiment
The gain of bottom input amplifier is 51dB, and gain bandwidth product is 1.6MHz, and phase margin is 70 °, and its amplitude versus frequency characte is special with phase frequency
Property is as shown in Figure 5.
Fig. 6 is the simulation result of the direct current transfer characteristic of the low sensitivity substrate input amplifier of the present embodiment.Input letter
Number scope is 0V to 1V.Amplifier proposed by the present invention is compared with existing substrate input amplifier, hence it is evident that visible, tied herein
Structure has the linearity higher, the broader input signal amplitude of oscillation.
Fig. 7 is the big signal time domain response simulation result figure of low sensitivity substrate input amplifier of the invention.Big signal
Transient response is 1Vpp by amplitude, and the square wave that frequency is 100kHz is applied to voltage follow structure and obtains, proposed by the present invention
The transient response curve of electromagnetic compatibility high reliability low voltage amplifier and existing substrate input amplifier is as shown in the figure.It can be seen that,
Compared to existing substrate input amplifier, the amplifier architecture switching rate for designing herein is symmetrical, shakes very little, and transient response is good
It is good.
The equivalent offset voltage simulation result figure of input of the low sensitivity substrate input amplifier of Fig. 8 the present embodiment.Input
End exists for 1V, when frequency range is the electromagnetic interference of 1Hz~4GHz, the simulation result of equivalent offset voltage.Compared to existing
Substrate input amplifier, the imbalance of this paper structures declines about an order of magnitude：The mistake caused by electromagnetic interference in structure of the present invention
Voltage max is adjusted to be only about 50mV.
Fig. 9 is the simulation result figure of the output spectrum density (PSD) of the low sensitivity substrate input amplifier of the present embodiment.
There is 100kHz in amplifier in, during 1Vpp electromagnetic interferences, the simulation result of output spectrum density (PSD) is as shown in the figure.Can
See, the output PSD peak values of the low sensitivity substrate input amplifier of the present embodiment are compared under obvious with existing substrate input structure
The peak value of drop, its harmonic components and fundamental wave component declines about 60dBm compared to existing structure, special with lower electromagnetic radiation
Property, Electro Magnetic Compatibility lifting is obvious.
Also, it should be noted that term " including ", "comprising" or its any other variant be intended to nonexcludability
Comprising so that process, method, commodity or equipment including a series of key elements not only include those key elements, but also wrapping
Include other key elements being not expressly set out, or also include for this process, method, commodity or equipment is intrinsic wants
Element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that wanted including described
Also there is other identical element in process, method, commodity or the equipment of element.
Embodiments herein is the foregoing is only, the application is not limited to.For those skilled in the art
For, the application can have various modifications and variations.It is all any modifications made within spirit herein and principle, equivalent
Replace, improve etc., within the scope of should be included in claims hereof.
Claims (10)
1. a kind of low sensitivity substrate input amplifier, it is characterised in that comprising at least one positive feedback structure；
The positive feedback structure includes the 11st transistor, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor
With the 23rd transistor；
11st transistor, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are equal
It is PMOS transistor；
The substrate of the 11st transistor, the 12nd transistor and the 13rd transistor is connected, used as the first substrate terminal；Described 21st is brilliant
The substrate of body pipe, the 22nd transistor and the 23rd transistor is connected, used as the second substrate terminal；
11st transistor, the 12nd transistor, the 13rd transistor, the 21st transistor, the 22nd transistor, the source of the 23rd transistor
Extremely it is connected, as total source terminal；
Drain electrode, the 12nd transistor drain, the grid of the 12nd transistor, the grid of the 13rd transistor, of the 11st transistor
The grid of 21 transistors is connected, extreme as the first grid；
Drain electrode, the 22nd transistor drain, the grid of the 22nd transistor, the grid of the 23rd transistor, of the 21st transistor
The grid of 11 transistors is connected, extreme as second gate；
The drain electrode of the 13rd transistor is the first drain electrode end；
The drain electrode of the 23rd transistor is the second drain electrode end.
2. low sensitivity substrate input amplifier as claimed in claim 1, it is characterised in that comprising improving positive feedback structure, institute
State improvement positive feedback structure and include first positive feedback structure and a filter circuit；
The filter circuit includes first resistor, second resistance, the first electric capacity, the second electric capacity, the first lining source electric capacity and the second lining
Source electric capacity；
The terminating differential signal positive input terminal of the first resistor one, another termination the first substrate terminal of the first positive feedback structure；
First capacitance cathode connects first the first substrate terminal of positive feedback structure, negative pole ground connection；
The first lining source electric capacity one terminates total source terminal, another termination the first substrate terminal of the first positive feedback structure；
The terminating differential signal negative input end of the second resistance one, another termination the second substrate terminal of the first positive feedback structure；
Second capacitance cathode connects first the second substrate terminal of positive feedback structure, negative pole ground connection；
The second lining source electric capacity one terminates total source terminal, another termination the second substrate terminal of the first positive feedback structure.
3. low sensitivity substrate input amplifier as claimed in claim 2, it is characterised in that
The value of the first resistor and the second resistance is 500k Ω；
The value of first electric capacity and the second electric capacity is 200fF；
The value of the first lining source electric capacity and the second lining source electric capacity is 3pF.
4. low sensitivity substrate input amplifier as claimed in claim 2, it is characterised in that comprising second positive feedback knot
Structure；
First drain electrode end of first positive feedback structure and the first drain electrode end of the second positive feedback structure are connected；
Second drain electrode end of first positive feedback structure and the second drain electrode end of the second positive feedback structure are connected；
The first grid of first positive feedback structure is extremely extremely connected with the first grid of the second positive feedback structure；
The second gate of first positive feedback structure is extremely extremely connected with the second gate of the second positive feedback structure；
The differential signal positive input terminates the first substrate terminal of the second positive feedback structure；
The differential signal negative input terminates the second substrate terminal of the second positive feedback structure.
5. the low sensitivity substrate input amplifier as described in claims 1 to 3 any one, it is characterised in that comprising biased electrical
Road；
The biasing circuit includes the 6th transistor, the 14th transistor and the 24th transistor；
6th transistor is PMOS transistor；
14th transistor and the 24th transistor are nmos pass transistor；
The source electrode of the 6th transistor connects operating voltage, and grid connects bias voltage, and drain electrode is connected with total source terminal；
The source ground of the 14th transistor, grid connects below-center offset voltage, and it is extreme that drain electrode connects the first grid；
The source ground of the 24th transistor, grid connects below-center offset voltage, and it is extreme that drain electrode connects the second gate.
6. low sensitivity substrate input amplifier as claimed in claim 4, it is characterised in that
Comprising the first biasing circuit, the second biasing circuit；
First biasing circuit includes the 6th transistor, the 14th transistor and the 24th transistor；
6th transistor is PMOS transistor；
14th transistor and the 24th transistor are nmos pass transistor；
The source electrode of the 6th transistor connects operating voltage, and grid connects bias voltage, drain electrode and first positive feedback structure
Total source terminal is connected；
The source ground of the 14th transistor, grid connects below-center offset voltage, and drain electrode connects the first of first positive feedback structure
Gate terminal；
The source ground of the 24th transistor, grid connects below-center offset voltage, and drain electrode connects the second of first positive feedback structure
Gate terminal；
Second biasing circuit includes 6* transistors, 14* transistors and 24* transistors；
The 6* transistors are PMOS transistor；
The 14* transistors and 24* transistors are nmos pass transistor；
The source electrode of the 6* transistors connects operating voltage, and grid connects bias voltage, drain electrode and second positive feedback structure
Total source terminal be connected；
The source ground of the 14* transistors, grid connects below-center offset voltage, and drain electrode connects the first of second positive feedback structure
Gate terminal；
The source ground of the 24* transistors, grid connects below-center offset voltage, and drain electrode connects the second of second positive feedback structure
Gate terminal.
7. the low sensitivity substrate input amplifier as described in Claims 1 to 4,6 any one, it is characterised in that comprising symmetrical
Output-stage circuit；
The symmetrical output-stage circuit includes the 31st transistor, the 32nd transistor, the 41st transistor, the 42nd transistor；
41st transistor, the 42nd transistor are PMOS transistor；
31st transistor, the 32nd transistor are nmos pass transistor；
The drain electrode of the 31st transistor connects the drain electrode of the 41st transistor, and grid connects first drain electrode end, source ground；
The drain electrode of the 32nd transistor connects the drain electrode of the 42nd transistor, and grid connects second drain electrode end, source ground；
The grid of the 41st transistor is connected with drain electrode, and source electrode connects operating voltage；
The grid of the 42nd transistor is connected with the grid of the 41st transistor, and source electrode connects operating voltage；
The drain electrode of the 32nd transistor is used as output voltage terminal.
8. the low sensitivity substrate input amplifier as described in Claims 1 to 4,6 any one, it is characterised in that comprising active
Load circuit；
The active pull-up circuit includes the 15th transistor, the 25th transistor；
15th transistor, the 25th transistor are nmos pass transistor；
The grid of the 15th transistor is connected with drain electrode and connects first drain electrode end, source ground；
The grid of the 25th transistor is connected with drain electrode and connects second drain electrode end, source ground.
9. low sensitivity substrate input amplifier as claimed in claim 5, it is characterised in that the biasing circuit is further wrapped
Contain：
7th transistor, the 8th transistor, the 9th transistor, the 10th transistor, the 5th transistor, current source；
7th transistor, the 9th transistor, the 10th transistor are PMOS transistor；
8th transistor, the 5th transistor are nmos pass transistor；
The source electrode of the 6th transistor connects operating voltage, and drain electrode connects total source terminal；
7th transistor source connects total source terminal, and grid connects the drain electrode of the 9th transistor, and drain electrode connects the leakage of the 8th transistor
Pole；
The source ground of the 8th transistor, grid connects the grid of the 10th transistor；
The source electrode of the 9th transistor connects operating voltage, and grid is connected with the drain electrode of itself；
The source ground of the 10th transistor, grid is connected with the 5th transistor, the drain electrode of drain electrode the 9th transistor of connection；
The grid of the 5th transistor is connected with drain electrode, source ground；
The current source positive pole connects operating voltage, and negative pole connects the drain electrode of the 5th transistor；
The drain voltage of the 7th transistor, as the upper offset voltage；
The grid voltage of the 5th transistor, as the below-center offset voltage.
10. low sensitivity substrate input amplifier as claimed in claim 6, it is characterised in that
First biasing circuit is further comprising the 7th transistor, the 8th transistor, the 9th transistor, the 10th transistor, the 5th crystalline substance
Body pipe, current source；
7th transistor, the 9th transistor, the 10th transistor are PMOS transistor；
8th transistor, the 5th transistor are nmos pass transistor；
The source electrode of the 6th transistor connects operating voltage, and drain electrode connects total source terminal of first positive feedback structure；
7th transistor source connects total source terminal of first positive feedback structure, and grid connects the drain electrode of the 9th transistor, leakage
Pole connects the drain electrode of the 8th transistor；
The source ground of the 8th transistor, grid connects the grid of the 10th transistor；
The source electrode of the 9th transistor connects operating voltage, and grid is connected with the drain electrode of itself；
The source ground of the 10th transistor, grid is connected with the 5th transistor, the drain electrode of drain electrode the 9th transistor of connection；
The grid of the 5th transistor is connected with drain electrode, source ground；
The current source positive pole connects operating voltage, and negative pole connects the drain electrode of the 5th transistor；
The drain voltage of the 7th transistor, the upper offset voltage as first biasing circuit；
The grid voltage of the 5th transistor, the below-center offset voltage as first biasing circuit.
Second biasing circuit further includes 7* transistors M7*, 8* transistors M8*, the 9th transistor, the 10th crystal
Pipe, the 5th transistor, current source；
9th transistor, the 10th transistor, the 5th transistor, current source are first biasing circuit and the second biasing circuit
Shared device；
The 7* transistors are PMOS transistor；
The 8* transistors are nmos pass transistor；
The source electrode of the 6* transistors connects operating voltage, and drain electrode connects total source terminal of second positive feedback structure；
The 7* transistor sources connect total source terminal of second positive feedback structure, and grid connects the drain electrode of the 9th transistor, leakage
Pole connects the drain electrode of 8* transistors；
The source ground of the 8* transistors, grid connects the grid of the 10th transistor；
The drain voltage of the 7* transistors, the upper offset voltage as second biasing circuit；
The grid voltage of the 5th transistor, also serves as the below-center offset voltage of second biasing circuit.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107370467A (en) * | 2017-07-22 | 2017-11-21 | 长沙方星腾电子科技有限公司 | A kind of current limliting error amplifier circuit for DC DC converters |
| CN109327197A (en) * | 2018-11-28 | 2019-02-12 | 电子科技大学 | A kind of control circuit of depletion type GaN-HEMT power amplifier |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741328A (en) * | 2009-12-16 | 2010-06-16 | 清华大学 | Complementary input circularly folding operational transconductance amplifier |
| CN101951236A (en) * | 2010-09-20 | 2011-01-19 | 东南大学 | Digital variable gain amplifier |
| CN104270100A (en) * | 2014-08-28 | 2015-01-07 | 中国科学技术大学 | Low-power low-noise amplifier utilizing positive feedback technique and active transconductance enhancement technique |
| US20150214900A1 (en) * | 2014-01-28 | 2015-07-30 | National Sun Yat-Sen University | Dual feedback low noise amplifier |
| CN105720935A (en) * | 2016-01-21 | 2016-06-29 | 中国电子科技集团公司第二十四研究所 | Transconductance amplifier of substrate input structure |
| CN106026938A (en) * | 2016-05-23 | 2016-10-12 | 四川和芯微电子股份有限公司 | Fully differential comparator |
| CN106059511A (en) * | 2015-04-09 | 2016-10-26 | 美国亚德诺半导体公司 | Multipath feedforward band pass amplifier |
-
2016
- 2016-12-01 CN CN201611095402.XA patent/CN106788279B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741328A (en) * | 2009-12-16 | 2010-06-16 | 清华大学 | Complementary input circularly folding operational transconductance amplifier |
| CN101951236A (en) * | 2010-09-20 | 2011-01-19 | 东南大学 | Digital variable gain amplifier |
| US20150214900A1 (en) * | 2014-01-28 | 2015-07-30 | National Sun Yat-Sen University | Dual feedback low noise amplifier |
| CN104270100A (en) * | 2014-08-28 | 2015-01-07 | 中国科学技术大学 | Low-power low-noise amplifier utilizing positive feedback technique and active transconductance enhancement technique |
| CN106059511A (en) * | 2015-04-09 | 2016-10-26 | 美国亚德诺半导体公司 | Multipath feedforward band pass amplifier |
| CN105720935A (en) * | 2016-01-21 | 2016-06-29 | 中国电子科技集团公司第二十四研究所 | Transconductance amplifier of substrate input structure |
| CN106026938A (en) * | 2016-05-23 | 2016-10-12 | 四川和芯微电子股份有限公司 | Fully differential comparator |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107370467A (en) * | 2017-07-22 | 2017-11-21 | 长沙方星腾电子科技有限公司 | A kind of current limliting error amplifier circuit for DC DC converters |
| CN107370467B (en) * | 2017-07-22 | 2020-06-09 | 上海军陶电源设备有限公司 | Current-limiting error amplifier circuit for DC-DC converter |
| CN109327197A (en) * | 2018-11-28 | 2019-02-12 | 电子科技大学 | A kind of control circuit of depletion type GaN-HEMT power amplifier |
| CN109327197B (en) * | 2018-11-28 | 2021-08-17 | 电子科技大学 | Control circuit of depletion type GaN-HEMT power amplifier |
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