CN101741328A - Complementary input circularly folding operational transconductance amplifier - Google Patents
Complementary input circularly folding operational transconductance amplifier Download PDFInfo
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- CN101741328A CN101741328A CN200910242475A CN200910242475A CN101741328A CN 101741328 A CN101741328 A CN 101741328A CN 200910242475 A CN200910242475 A CN 200910242475A CN 200910242475 A CN200910242475 A CN 200910242475A CN 101741328 A CN101741328 A CN 101741328A
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Abstract
The invention relates to a complementary input circularly folding operational transconductance amplifier, belongs to the technical field of operational amplifiers, and is characterized in that: the unity gain bandwidth of the operational transconductance amplifier is increased through the complementary input of P-type transistors (M1a, M1b, M2a and M2b) and N-type transistors (M14a, M14b, M15a and M15b) and through the adoption of the circularly folding operational transconductance amplifier. A circuit has the advantages of high unity gain bandwidth and low power consumption and accords with the research and development direction of an integrated circuit.
Description
Technical field
The invention belongs to the VLSI (very large scale integrated circuit) designs in Microelectronics and Solid State Electronics field, relate to a kind of novel transconductance amplifier circuit, can be used for analog to digital conversion circuit, the design of analog signal processing circuits such as filter.
Background technology
The present invention relates to design such as the contour performance switched-capacitor circuit of high-speed AD converter high speed operational transconductance amplifier.Operational amplifier is one of most important module of a lot of analog circuits, is widely used in analog to digital conversion circuit, in the analog signal processing circuits such as filter.Usually the indexs such as precision, speed and power consumption that the high performance switch condenser network can reach have been determined.In switched-capacitor circuit, load is generally pure capacitive properties, and single-stage operation transconductance amplifier this moment (OTA) is better than multistage operational amplifier.Therefore, traditional collapsible OTA amplifier has obtained to use widely.But traditional collapsible OTA has shortcomings such as speed is slow, power consumption is big.On the one hand, the operating rate of integrated circuit improves day by day; On the other hand, present consumer electronics field is that the mobile portable equipment of electric power requires the power consumption of circuit low as far as possible with the battery, thereby prolongs the service time of mobile portable equipment.
At above-mentioned situation, the present invention proposes a kind of loop collapsing OTA with complementary input.
Summary of the invention
In order to overcome the existing deficiency that collapsible OTA speed is slow, power consumption is big, the present invention has designed the folding OTA of novel complementary cycle.The object of the invention is to improve the unity gain bandwidth GBW of OTA, with the operating rate of raising operational amplifier, and the power consumption of reduction OTA.Use the present invention, can improve speed, perhaps reduce power consumption such as the high performance switch electric capacity of high-performance analog to digital converter.
The invention is characterized in,
Contain two complementary input branch roads of N type and P type, and wherein each imports voltage bias transistor part that branch road connected, the tail current transistor of setovering part and cascode transistors to part, wherein:
The complementary input of P type branch road, contain: a PMOS pipe M1a, the 2nd PMOS pipe M1b, the 3rd PMOS pipe M2b and the 4th PMOS pipe M2a, wherein: the grid of the grid of PMOS pipe M1a, the 2nd PMOS pipe M1b all links to each other with a VINN differential signal in two fully differential signals of input, and the grid that the grid of the 3rd PMOS pipe M2b, the 4th PMOS manage M2a all links to each other with another VINP differential signal in two fully differential signals of described input;
Two the 5th PMOS transistor M31 and the 6th PMOS transistor M32 of polyphone constitute the voltage bias transistor part mutually, wherein: meet the first bias voltage Vbp0 after the grid of the grid of the 5th PMOS transistor M31 and the 6th PMOS transistor M32 links to each other, the drain electrode while of the 5th PMOS transistor M31 and the source electrode of a PMOS transistor M1a, the source electrode of the 2nd PMOS transistor M1b, the source electrode of the source electrode of the 3rd PMOS transistor M2b and the 4th PMOS transistor M2a links to each other, the source electrode of the 6th PMOS transistor M32 meets supply voltage VDD
Four NMOS pipes altogether of the one NMOS pipe M3a, the 2nd NMOS pipe M3b, the 3rd NMOS pipe M4b, the 4th NMOS pipe M4a have been formed the biasing tail current transistor part of the complementary input of described P type branch road, wherein: link to each other with the drain electrode of described the 3rd PMOS pipe M2b again after the grid of the grid of NMOS pipe M3a and the 2nd NMOS pipe M3b links to each other, link to each other with the drain electrode that described the 2nd PMOS manages M1b again after the grid that the grid of the 3rd NMOS pipe M4b and the 4th NMOS manage M4a links to each other; The 5th NMOS manages M5, the 6th NMOS manages M6, the 7th NMOS manages M11, this four NMOS pipe of the 8th NMOS pipe M12 has constituted the cascode transistors of the complementary input of described P type branch road jointly to part, wherein: the source electrode of the 5th NMOS pipe M5 is managed the drain electrode of M1a simultaneously with a described PMOS, the drain electrode of the one NMOS pipe M3a links to each other, the source electrode of the 6th NMOS pipe M6 is managed the drain electrode of M2a simultaneously with described the 4th PMOS, the drain electrode of the 4th NMOS pipe M4a connects, the source electrode of the 7th NMOS pipe M11 links to each other with the drain electrode of described the 2nd NMOS pipe M3b, the source electrode of the 8th NMOS pipe M12 links to each other with the drain electrode of described the 3rd NMOS pipe M4b, the drain electrode of the 7th NMOS pipe M11 links to each other with the drain electrode of affiliated the 3rd PMOS pipe M2b, the drain electrode of the 8th NMOS pipe M12 links to each other with the drain electrode of described the 2nd PMOS pipe M1b, meet the second bias voltage Vbn2 after the gate interconnection of the grid of the 7th NMOS pipe M11 and the 8th NMOS pipe M12, also meet the second bias voltage Vbn2 after the grid of the grid of the 5th nmos pass transistor M5 and the 6th nmos pass transistor M6 links to each other;
The complementary input circuit of N type, contain: the nmos pass transistor of four source electrode interconnection: the 9th NMOS pipe M14a, the tenth NMOS pipe M14b, the 11 NMOS pipe M15b, the 12 NMOS manage M15a, wherein: the grid of these two NMOS pipes of the 9th NMOS pipe M14a, the tenth NMOS pipe M14b all is connected to a differential signal VINN of described two fully differential input signals, and the grid of these two NMOS pipes of the 11 NMOS pipe M15b, the 12 NMOS pipe M15a all is connected to another differential signal VINP of described two fully differential input signals; The voltage bias transistor part is made of the 13 NMOS pipe M13, the source ground of the 13 nmos pass transistor M13, grid meets common mode control signal VCMFB, and drain electrode links to each other with the source electrode of described four NMOS pipe, biasing tail current transistor part is made of these four PMOS pipes of the 7th PMOS pipe M9a, the 8th PMOS pipe M9b, the 9th PMOS pipe M10b, the tenth PMOS pipe M10a, wherein: the described the 7th to the tenth the source electrode of totally four PMOS pipes M9a, M9b, M10b, M10a all link described supply voltage VDD; Cascode transistors is managed M7 to part by the 11 PMOS, the 12 PMOS manages M8, the 13 PMOS manages M16, the 14 PMOS pipe M17 constitutes, wherein: the grid of the 11 PMOS pipe M7, the grid of the 12 PMOS transistor M8, the grid of 13 PMOS transistor M13 and the grid of the 14 PMOS transistor M17 all meet the 3rd bias voltage Vbp2, the source electrode while of the 11 PMOS transistor M7 and the source electrode of the 7th PMOS transistor M9a, the drain electrode of the 9th nmos pass transistor M14a links to each other, the source electrode while of the 12 PMOS transistor M8 and the drain electrode of the tenth PMOS transistor M10a, the drain electrode of the tenth bi-NMOS transistor M15a links to each other, the drain electrode of the 13 PMOS pipe M16 links to each other with the drain electrode of the 8th PMOS pipe M9b, drain electrode links to each other the source electrode of the 14 PMOS pipe M17 with the 9th PMOS pipe M10b simultaneously, in addition, after the gate interconnection of the grid of the 7th PMOS transistor M9a and the 8th PMOS transistor M9b again with the drain electrode of the 13 PMOS transistor M16, the drain electrode of the 11 NMOS pipe M15b links to each other, after the gate interconnection of the grid of the 9th PMOS transistor M10b and the tenth PMOS transistor M10a again with the drain electrode of the 14 PMOS transistor M17, the drain electrode interconnection of the tenth nmos pass transistor M14b, the drain electrode of the drain electrode of described the 11 PMOS pipe M7 and the 5th NMOS pipe M5 links to each other and exports differential signal VOUTP, the 12 PMOS pipe M8 links to each other with the drain electrode of the 6th NMOS pipe M6, export another differential signal VOUTN, these two differential signals of described VOUTP and VOUTN constitute fully differential output jointly;
The circularly folding operational transconductance amplifier of described complementary input also comprises a common mode feedback circuit, and this common mode feedback circuit contains the input branch road and the common-mode feedback control electronic circuit of fully differential output signal, wherein:
The input branch road of fully differential output signal is a series arm that is made of resistance R 1 and resistance R 2 serial connections, the described output differential signal of the non-series termination VOUTN of resistance R 1, another output differential signal of the non-series termination of resistance R 2 VOUTP;
Common-mode feedback control electronic circuit, contain: the 25 PMOS pipe M18 and two transistor series connection branch roads parallel with one another, wherein:
Article one, transistor series connection branch road, form by the 16 PMOS pipe M19 and the 14 NMOS pipe M21 serial connection, wherein: the grid of the 16 PMOS pipe M19 connects the tie point of described resistance R 1 and resistance R 2, meets common mode control signal VCMFB after the grid of the 14 NMOS pipe M21 and draining links to each other
Second crystal series arm, be in series by the 18 PMOS pipe M20 and the 15 NMOS pipe M22, wherein, the grid of the 18 PMOS pipe M20 meets input common mode voltage VCM, the grid of the 15 NMOS pipe M22 links to each other with drain electrode, the source electrode of described the 14 NMOS pipe M21 and the 15 NMOS pipe M22 altogether, connect the drain electrode of described the 15 PMOS transistor M18 after the 16 PMOS pipe M19 and the 17 PMOS pipe M20 source electrode interconnection separately, then the source electrode of the 15 PMOS transistor M18 meets supply voltage VDD.
The invention has the beneficial effects as follows: carry out SPICE emulation at the CADENCE platform, simulation result shows that at the 5.6pF capacitive load, under the total bias current of 800 μ A, unity gain bandwidth is 194.5MHz, DC current gain 61.17dB, phase margin 81.49 degree.
Description of drawings
Fig. 1. the circuit diagram of the loop collapsing OTA of the complementary input of the present invention.
Fig. 2. the circuit diagram of the common mode feedback circuit of implementing according to example.
Embodiment
Technical solution of the present invention is consulted Fig. 1.Fig. 1 is the loop collapsing OTA of a complementary input, different with conventional OTA, it has adopted N type metal-oxide-semiconductor and the complementary input of P type metal-oxide-semiconductor branch road, and two branch roads have all adopted the loop collapsing OTA structure of being reported in the article " The Recycling Folded Cascode:A GeneralEnhancement of the Folded Cascode Amplifier " of the 9th volume 2535-2542 page or leaf September in 2009 at IEEE solid-state circuit magazine by Rida S.Assaad and Jose Silva-Martinez.
Transistor M1a, M1b, M2a, M2b are P type entering apparatus among Fig. 1, and M14a, M14b, M15a, M15b are N type entering apparatus.VINP, VINN are the fully differential input signal, and VINP is added to the grid of M2a, M2b and M15a, M15b, and VINN is added to the grid of M1a, M1b and M14a, M14b.Transistor M31, M32 provide bias current for P type input branch road M1a, M1b, M2a, M2b, and M13 provides bias current for N type input branch road M14a, M14b, M15a, M15b.Meanwhile, M13 provides a path, with the signal VCMFB control common mode component by producing in common mode feedback circuit.Transistor M3a, M3b and M4a, M4b are the biasing tail current transistor of P input branch, and M5, M6 and M11, M12 are that the cascode transistors of P input branch is right.Transistor M9a, M9b and M10a, M10b are the biasing tail current transistor of N input branch.M7, M8 and M16, M17 are that the cascode transistors of N input branch is right.VOUTP and VOUTN are fully differential output.Vbp0 is the bias voltage of transistor M31, M32, and Vpb2 is the bias voltage of transistor M7, M8, M16, M17.Vbn2 is the bias voltage of transistor M5, M6, M11, M12.VDD and GND have the supply voltage of 2.5V and 0V respectively.
Compare with the Rida S.Assaad loop collapsing OTA that P type entering apparatus is only arranged, the folding OTA of complementary cycle of the present invention has increased N type entering apparatus branch road, and cascode transistors M5, the M6 of N type entering apparatus branch road and P type entering apparatus branch road and M7, M8 shared identical electric current.The electric current of each branch road that has therefore utilized more fully effectively raises the unity gain bandwidth GBW of amplifier, improving the speed of amplifier.
Fig. 2 is a common mode feedback circuit.Resistance R 1 and R2 are the entering apparatus of common mode feedback circuit, and the one end meets output VOUTP and the VOUTN of OTA respectively, the grid of another termination transistor M19.Common-mode voltage in the grid generation OTA fully differential output voltage that act as at M19 of R1 and R2.Input common mode voltage VCM is added in the grid of transistor M20.Transistor M21 and M22 that diode connects are the loads of differential pair M19 and M20, and the voltage difference that differential pair M19 and M20 are produced through transistor M21 and M22, is created in the used common mode control signal VCMFB of OTA among Fig. 1.Transistor M18 provides bias current for transistor M19, M20, and Vbp1 is the bias voltage of M18.VDD and GND are respectively the supply voltage of 2.5V and 0V.
In order to verify performance, carry out SPICE emulation at the CADENCE platform.
Simulation result shows that at the 5.6pF capacitive load, under the total bias current of 800 μ A, unity gain bandwidth is 194.5MHz.The characteristic of OTA is summed up as table 1.
Table 1:OTA characteristic is summed up
| Title | Complementary cycle folds OTA |
| Bias current (μ A) | ????800 |
| DC current gain (dB) | ????61.17 |
| Unity gain bandwidth (MHz) | ????194.5 |
| Phase margin (deg) | ????81.49 |
| Capacitive load (pF) | ????5.6 |
Claims (2)
1. the complementary circularly folding operational transconductance amplifier of importing, it is characterized in that, contain two complementary input branch roads of N type and P type, and wherein each imports voltage bias transistor part that branch road connected, the tail current transistor of setovering part and cascode transistors to part, wherein:
The complementary input of P type branch road, contain: PMOS pipe (M1a), the 2nd PMOS pipe (M1b), the 3rd PMOS pipe (M2b) and the 4th PMOS pipe (M2a), wherein: the grid of the grid of PMOS pipe (M1a), the 2nd PMOS pipe (M1b) all links to each other with a VINN differential signal in two fully differential signals of input, and the grid that the grid of the 3rd PMOS pipe (M2b), the 4th PMOS manage (M2a) all links to each other with another VINP differential signal in two fully differential signals of described input;
Two the 5th PMOS transistor (M31) and the 6th PMOS transistor (M32) of polyphone constitute the voltage bias transistor part mutually, wherein: connect first bias voltage (Vbp0) after the grid of the grid of the 5th PMOS transistor (M31) and the 6th PMOS transistor (M32) links to each other, the drain electrode while of the 5th PMOS transistor (M31) and the source electrode of a PMOS transistor (M1a), the source electrode of the 2nd PMOS transistor (M1b), the source electrode of the source electrode of the 3rd PMOS transistor (M2b) and the 4th PMOS transistor (M2a) links to each other, the source electrode of the 6th PMOS transistor (M32) connects supply voltage (VDD)
The one NMOS pipe (M3a), the 2nd NMOS pipe (M3b), the 3rd NMOS pipe (M4b), the 4th NMOS pipe (M4a) four NMOS pipes have altogether been formed the biasing tail current transistor part of the complementary input of described P type branch road, wherein: link to each other with the drain electrode of described the 3rd PMOS pipe (M2b) again after the grid that the grid of NMOS pipe (M3a) and the 2nd NMOS manages (M3b) links to each other, link to each other with the drain electrode that described the 2nd PMOS manages (M1b) again after the grid that the grid that the 3rd NMOS manages (M4b) and the 4th NMOS manage (M4a) links to each other; The 5th NMOS manages (M5), the 6th NMOS manages (M6), the 7th NMOS manages (M11), the 8th NMOS pipe (M12) this four NMOS pipe has constituted the cascode transistors of the complementary input of described P type branch road jointly to part, wherein: the source electrode of the 5th NMOS pipe (M5) is managed the drain electrode of (M1a) simultaneously with a described PMOS, the drain electrode of the one NMOS pipe (M3a) links to each other, the source electrode of the 6th NMOS pipe (M6) is managed the drain electrode of (M2a) simultaneously with described the 4th PMOS, the drain electrode of the 4th NMOS pipe (M4a) connects, the source electrode of the 7th NMOS pipe (M11) links to each other with the drain electrode that described the 2nd NMOS manages (M3b), the source electrode of the 8th NMOS pipe (M12) links to each other with the drain electrode that described the 3rd NMOS manages (M4b), the drain electrode of the 7th NMOS pipe (M11) links to each other with the drain electrode that affiliated the 3rd PMOS manages (M2b), the drain electrode of the 8th NMOS pipe (M12) links to each other with the drain electrode that described the 2nd PMOS manages (M1b), connect second bias voltage (Vbn2) after the gate interconnection of the grid of the 7th NMOS pipe (M11) and the 8th NMOS pipe (M12), also connect second bias voltage (Vbn2) after the grid of the grid of the 5th nmos pass transistor (M5) and the 6th nmos pass transistor (M6) links to each other;
The complementary input circuit of N type, contain: the nmos pass transistor of four source electrode interconnection: the 9th NMOS manages (M14a), the tenth NMOS manages (M14b), the 11 NMOS manages (M15b), the 12 NMOS manages (M15a), wherein: the 9th NMOS manages (M14a), the grid of the tenth NMOS pipe (M14b) these two NMOS pipes all is connected to a differential signal (VINN) of described two fully differential input signals, and the 11 NMOS manages (M15b), the grid of the 12 NMOS pipe (M15a) these two NMOS pipes all is connected to another differential signal (VINP) of described two fully differential input signals; The voltage bias transistor part is made of the 13 NMOS pipe (M13), the source ground of the 13 nmos pass transistor (M13), grid connects common mode control signal (VCMFB), and drain electrode links to each other with the source electrode of described four NMOS pipe, biasing tail current transistor part is made of the 7th PMOS pipe (M9a), the 8th PMOS pipe (M9b), the 9th PMOS pipe (M10b), these four PMOS pipes of the tenth PMOS pipe (M10a), wherein: the described the 7th to the tenth the source electrode of totally four PMOS pipes (M9a, M9b, M10b, M10a) all link described supply voltage (VDD); Cascode transistors is managed (M7) to part by the 11 PMOS, the 12 PMOS manages (M8), the 13 PMOS manages (M16), the 14 PMOS pipe (M17) constitutes, wherein: the grid of the 11 PMOS pipe (M7), the grid of the 12 PMOS transistor (M8), the grid of the 13 PMOS transistor (M13) and the grid of the 14 PMOS transistor (M17) all connect the 3rd bias voltage (Vbp2), the source electrode while of the 11 PMOS transistor (M7) and the source electrode of the 7th PMOS transistor (M9a), the drain electrode of the 9th nmos pass transistor (M14a) links to each other, the source electrode while of the 12 PMOS transistor (M8) and the drain electrode of the tenth PMOS transistor (M10a), the drain electrode of the tenth bi-NMOS transistor (M15a) links to each other
The drain electrode of the 13 PMOS pipe (M16) links to each other with the drain electrode that the 8th PMOS manages (M9b), drain electrode links to each other the source electrode of the 14 PMOS pipe (M17) with the 9th PMOS pipe (M10b) simultaneously, in addition, after the gate interconnection of the grid of the 7th PMOS transistor (M9a) and the 8th PMOS transistor (M9b) again with the drain electrode of the 13 PMOS transistor (M16), the drain electrode of the 11 NMOS pipe (M15b) links to each other, after the gate interconnection of the grid of the 9th PMOS transistor (M10b) and the tenth PMOS transistor (M10a) again with the drain electrode of the 14 PMOS transistor (M17), the drain electrode interconnection of the tenth nmos pass transistor (M14b)
The drain electrode that the drain electrode of described the 11 PMOS pipe (M7) and the 5th NMOS manages (M5) links to each other and exports differential signal (VOUTP), the 12 PMOS pipe (M8) links to each other with the drain electrode of the 6th NMOS pipe (M6), export another differential signal (VOUTN), these two differential signals of described VOUTP and VOUTN constitute fully differential output jointly.
2. the circularly folding operational transconductance amplifier of complementary input according to claim 1 is characterized in that, the circularly folding operational transconductance amplifier of described complementary input also comprises a common mode feedback circuit, this common mode feedback circuit contains the input branch road and the common-mode feedback control electronic circuit of fully differential output signal, wherein:
The input branch road of fully differential output signal, it is a series arm that constitutes by resistance (R1) and resistance (R2) serial connection, the described output differential signal of the non-series termination of resistance (R1) (VOUTN), another output differential signal (VOUTP) of the non-series termination of resistance (R2)
Common-mode feedback control electronic circuit, contain: the 25 PMOS manages (M18) and two transistor series connection branch roads parallel with one another, wherein:
Article one, transistor series connection branch road, form by the 16 PMOS pipe (M19) and the 14 NMOS pipe (M21) serial connection, wherein: the grid of the 16 PMOS pipe (M19) connects the tie point of described resistance (R1) and resistance (R2), after linking to each other, the grid of the 14 NMOS pipe (M21) and draining connects common mode control signal (VCMFB)
Second crystal series arm is in series by the 18 PMOS pipe (M20) and the 15 NMOS pipe (M22), and wherein, the grid of the 18 PMOS pipe (M20) connects input common mode voltage (VCM), and the grid of the 15 NMOS pipe (M22) links to each other with drain electrode,
The source electrode of described the 14 NMOS pipe (M21) and the 15 NMOS pipe (M22) altogether, connect the drain electrode of described the 15 PMOS transistor (M18) after the source electrode interconnection separately of the 16 PMOS pipe (M19) and the 17 PMOS pipe (M20), then the source electrode of the 15 PMOS transistor (M18) connects supply voltage (VDD).
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| CN107579713A (en) * | 2017-09-29 | 2018-01-12 | 清华大学 | A kind of new operational transconductance amplifier circuit |
| CN107579713B (en) * | 2017-09-29 | 2020-12-04 | 清华大学 | Novel transconductance operational amplifier circuit |
| CN108494377A (en) * | 2018-04-11 | 2018-09-04 | 昆山锐芯微电子有限公司 | Operation amplifier circuit |
| CN108494377B (en) * | 2018-04-11 | 2022-02-01 | 锐芯微电子股份有限公司 | Operational amplifier circuit |
| CN109728786A (en) * | 2019-03-01 | 2019-05-07 | 赣南师范大学 | A kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier |
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Open date: 20100616 |