CN101969351A - Circuit for detecting strength of receipt signals - Google Patents

Abstract

The invention discloses a circuit for detecting strength of receipt signals, comprising a nonequilibrium source-level cross coupling pair, a local positive feedback load and an output terminal clamping circuit. Within the detection range, input signal strength and output DC level are in a linear relation and the nonequilibrium source-level cross coupling pair is employed to carry out the function of the traditional logarithmic amplifier on the circuit. The local positive feedback load and the output terminal clamping circuit are in circuit cascade connection with the nonequilibrium source-level cross coupling pair; as a result, the performance of the circuit for detecting the strength of the receipt signals is optimized. Compared with the traditional receipt signal strength detection circuit based on the logarithmic amplifier, the circuit of the invention features wider detection range, better linearity and better stability.

Description

A kind of received signal intensity detection circuit

Technical field

The present invention relates to a kind of received signal intensity detection circuit (Receive Signal Strength Indicator is called for short RSSI).

Background technology

In the transceiver structure, the effect of received signal intensity detection circuit is to detect the intensity of signal in the link, testing result is outputed to analog/digital converter (A/D), baseband processing circuitry, and then generation control signal, adjust the operating state of correlation module (as low noise amplifier, power amplifier, PGA etc.) in the link, guarantee that system can work normally.

The leading indicator of received signal intensity detection circuit comprises dynamic range, the influence to link, linearity, the stability of monitor signal.The monitor signal dynamic range should be big as much as possible, covers the whole excursion of signal in the link.Should be little to the link influence, do not influence the operate as normal of link.Have good linearity, avoid producing the detection error.Have good stability, avoid circuit working state to be subjected to the influence of external environment, as temperature.

General received signal intensity detection circuit can be classified according to signal detection mode, comprises that peak value detects, RMS detects and power detection.Peak value detects and is meant that peak value to received signal detects.RMS detects and is meant that the root-mean-square value to signal detects.Power detection is meant that the power (being the dBm value) to signal detects.

Based on the received signal intensity detection circuit of logarithmic amplifier is power detection at signal, mainly is according to dBm value computing formula:

$\mathrm{Power}\left(\mathrm{dBm}\right)=10{\log }_{10}\left(\frac{{V^2}_{\mathrm{rms}}/50}{1\mathrm{mw}}\right)$

By formula as seen, dBm value and signal amplitude are logarithmic relationship, so can utilize logarithmic amplifier to realize the received signal intensity detection circuit.

Traditional received signal intensity detection circuit based on logarithmic amplifier, such as list of references " A CMOS Logarithmic IF Amplifier with Unbalanced Source-Coupled Pairs " introduction, adopt the coupling of nonequilibrium source class to, cross-linked input stage and parallel connected output stage.The transistor of nonequilibrium source class coupling centering adopts two kinds of different sizes (β and K β), according to the difference of K value, obtains different input/output relation curves.The input/output relation of logarithmic amplifier presents logarithmic relationship in the certain limit of input signal, this scope is the working range of received signal intensity detection circuit.

The nonequilibrium source class of organizing different size (β) can be coupled more to parallel connection the detection range of expansion received signal intensity detection circuit during practical application.

Summary of the invention

Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides that a kind of wide dynamic range, the linearity are good, good stability novel received signal intensity detection circuit.

Technical scheme: for achieving the above object, the technical solution used in the present invention is:

A kind of received signal intensity detection circuit, adopt non-equilibrium source class cross-couplings to, local positive feedback load and the three part cascades of output clamp circuit, in detection range, make between input signal strength (dBm) and the output DC flat (V) and realize linear relationship.This received signal intensity detection circuit comprises that mainly non-equilibrium source class cross-couplings is to circuit, local positive feedback load circuit and output clamp circuit three parts:

Described non-equilibrium source class cross-couplings comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor to circuit;

Described local positive feedback load circuit comprises the 8th nmos pass transistor, the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 18 nmos pass transistor, the 19 nmos pass transistor, the 20 PMOS transistor, the 21 PMOS transistor, the 20 bi-NMOS transistor, the 23 nmos pass transistor;

Described output clamp circuit comprises that load resistance, the 24 PMOS transistor, operational amplifier and realization provide circuit Replica to non-equilibrium source class cross-couplings to the output offset current potential that duplicates of circuit and local positive feedback load circuit;

Non-equilibrium source class cross-couplings to circuit in, a PMOS transistor and the transistorized grid of the 2nd PMOS connect the positive level of radio-frequency input signals, the 3rd PMOS transistor and the transistorized grid of the 4th PMOS connect the negative level of radio-frequency input signals; The one PMOS transistor and the transistorized source class of the 2nd PMOS connect the 5th PMOS transistor drain, and the 3rd PMOS transistor and the transistorized source class of the 4th PMOS connect the 6th PMOS transistor drain; The 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor are formed current-mirror structure, constitute the biasing circuit that bias current is provided;

In the local positive feedback load circuit, the grid of the 8th nmos pass transistor and the 9th nmos pass transistor connects the drain electrode of the 9th nmos pass transistor, the drain electrode of the 8th nmos pass transistor connects the drain electrode of the 21 nmos pass transistor, the drain electrode of the 9th nmos pass transistor and the tenth nmos pass transistor connects a PMOS transistor drain, the grid of the tenth nmos pass transistor connects the drain electrode of the tenth bi-NMOS transistor, the grid of the 11 nmos pass transistor connects the drain electrode of the tenth nmos pass transistor, the grid of the tenth bi-NMOS transistor and the 13 nmos pass transistor all connects the drain electrode of the tenth bi-NMOS transistor, the drain electrode of the 13 nmos pass transistor connects the drain electrode of the 21 nmos pass transistor, and the drain electrode of the tenth bi-NMOS transistor connects the 3rd PMOS transistor drain;

The grid of the 14 nmos pass transistor and the 15 nmos pass transistor connects the 15 nmos transistor drain, the drain electrode of the 14 nmos pass transistor connects the drain electrode of the 20 nmos pass transistor, the drain electrode of the 15 nmos pass transistor and the 16 nmos pass transistor connects the 2nd PMOS transistor drain, the grid of the 16 nmos pass transistor connects the drain electrode of the 18 nmos pass transistor, the grid of the 17 nmos pass transistor connects the drain electrode of the 15 nmos pass transistor, the grid of the 18 nmos pass transistor and the 19 nmos pass transistor all connects the 18 nmos transistor drain, the drain electrode of the 19 nmos pass transistor connects the drain electrode of the 20 nmos pass transistor, and the drain electrode of the 18 nmos pass transistor connects the 4th PMOS transistor drain;

The source ground of the 8th nmos pass transistor, the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor the 17 nmos pass transistor and the 18 nmos pass transistor;

The 20 PMOS transistor and the transistorized grid of the 21 PMOS are all received the 20 PMOS transistor drain, the 20 PMOS transistor and the transistorized source electrode of the 21 PMOS connect power supply, the 20 PMOS transistor drain connects the drain electrode of the 14 nmos pass transistor and the 19 nmos pass transistor, the 21 PMOS transistor drain is received the 8th nmos pass transistor, the drain electrode of the 13 nmos pass transistor and the 20 bi-NMOS transistor, the drain electrode that the grid of the 20 bi-NMOS transistor and the 23 nmos pass transistor is all received the 20 bi-NMOS transistor, the source electrode of the 20 bi-NMOS transistor and the 23 nmos pass transistor is ground connection all, and the drain electrode of the 23 nmos pass transistor connects load resistance and the 24 PMOS transistor drain;

In the output clamp circuit, load resistance one termination power, another termination the 23 nmos pass transistor and the 24 PMOS transistor drain, the transistorized source electrode of the 24 PMOS connects power supply, and the transistorized grid of the 24 PMOS connects the output of operational amplifier; The positive pole of operational amplifier connects the output offset current potential circuit Replica is provided, and the negative pole of operational amplifier connects reference voltage.

Described operational amplifier comprises the 25 PMOS transistor, the 26 PMOS transistor, the 27 nmos pass transistor, the 28 nmos pass transistor, the 29 nmos pass transistor; The 25 PMOS transistor and the transistorized source class of the 26 PMOS connect power supply, the 25 PMOS transistor and the transistorized grid of the 26 PMOS connect the 25 PMOS transistor drain, the 25 PMOS transistor drain connects the 27 PMOS transistor drain, the drain electrode of the 26 PMOS transistor drain and the 28 nmos pass transistor connects the output of operational amplifier, the source electrode of the 27 nmos pass transistor and the 28 nmos pass transistor connects the drain electrode of the 29 nmos pass transistor, the grid of the 29 nmos pass transistor connects biasing BIAS, the source ground of the 29 nmos pass transistor.

Beneficial effect: received signal intensity detection circuit provided by the invention, the main body circuit is made of, local positive feedback load and the three part cascades of output clamp circuit non-equilibrium source class cross-couplings.Effectively expansion detection signal scope provides the good linearity and stability, improves the sensitivity and the precision of input.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Fig. 2 a and Fig. 2 b are circuit theory schematic diagram of the present invention;

Fig. 3 is the circuit theory schematic diagram of operational amplifier;

Fig. 4 is the received signal intensity detection circuit principle schematic of traditional opportunity logarithmic amplifier;

Fig. 5 is the design sketch that received signal intensity detection circuit provided by the invention detects input signal strength.

Embodiment

Below in conjunction with accompanying drawing the present invention is done further explanation.

Be illustrated in figure 1 as the structural representation of received signal intensity detection circuit provided by the invention, the Vout among Fig. 1, cm is produced by the Replica modular circuit; The Replica modular circuit is identical with the structure shown in Fig. 2 a and Fig. 2 b, and just input does not add signal to be detected (input offset voltage), produces clamping level at output like this.

Fig. 2 a and Fig. 2 b are the circuit theory schematic diagram of described testing circuit, and in Fig. 2 a and Fig. 2 b, the L1 among the L1 among Fig. 2 a and Fig. 2 b links together, and the L2 among the L2 among Fig. 2 a and Fig. 2 b links together.This received signal intensity detection circuit comprises that non-equilibrium source class cross-couplings is to circuit, local positive feedback load circuit and output clamp circuit:

Described non-equilibrium source class cross-couplings comprises a PMOS transistor M1, the 2nd PMOS transistor M2, the 3rd PMOS transistor M3, the 4th PMOS transistor M4, the 5th PMOS transistor M5, the 6th PMOS transistor M6, the 7th PMOS transistor M7 to circuit;

Described local positive feedback load circuit comprises the 8th nmos pass transistor M8, the 9th nmos pass transistor M9, the tenth nmos pass transistor M10, the 11 nmos pass transistor M11, the tenth bi-NMOS transistor M12, the 13 nmos pass transistor M13, the 14 nmos pass transistor M14, the 15 nmos pass transistor M15, the 16 nmos pass transistor M16, the 17 nmos pass transistor M17, the 18 nmos pass transistor M18, the 19 nmos pass transistor M19, the 20 PMOS transistor M20, the 21 PMOS transistor M21, the 20 bi-NMOS transistor M22, the 23 nmos pass transistor M23;

Described output clamp circuit comprises load resistance R1, the 24 PMOS transistor M24, operational amplifier OP and realizes providing circuit Replica to non-equilibrium source class cross-couplings to the output offset current potential that duplicates of circuit and local positive feedback load circuit;

Non-equilibrium source class cross-couplings to circuit in, the grid of a PMOS transistor M1 and the 2nd PMOS transistor M2 connects the positive level of radio-frequency input signals, the grid of the 3rd PMOS transistor M3 and the 4th PMOS transistor M4 connects the negative level of radio-frequency input signals; The source class of the one PMOS transistor M1 and the 2nd PMOS transistor M2 connects the drain electrode of the 5th PMOS transistor M5, and the source class of the 3rd PMOS transistor M3 and the 4th PMOS transistor M4 connects the drain electrode of the 6th PMOS transistor M6; The 5th PMOS transistor M5, the 6th PMOS transistor M6, the 7th PMOS transistor M7 form current-mirror structure, constitute the biasing circuit that bias current is provided;

In the local positive feedback load circuit, the grid of the 8th nmos pass transistor M8 and the 9th nmos pass transistor M9 connects the drain electrode of the 9th nmos pass transistor M9, the drain electrode of the 8th nmos pass transistor M8 meets the drain electrode L1 place of the 21 nmos pass transistor M21, the drain electrode of the 9th nmos pass transistor M9 and the tenth nmos pass transistor M10 connects the drain electrode of a PMOS transistor M1, the grid of the tenth nmos pass transistor M10 connects the drain electrode of the tenth bi-NMOS transistor M12, the grid of the 11 nmos pass transistor M11 connects the drain electrode of the tenth nmos pass transistor M10, the grid of the tenth bi-NMOS transistor M12 and the 13 nmos pass transistor M13 all connects the tenth bi-NMOS transistor M12 drain electrode, the drain electrode of the 13 nmos pass transistor M13 meets the drain electrode L1 place of the 21 nmos pass transistor M21, and the drain electrode of the tenth bi-NMOS transistor M12 connects the drain electrode of the 3rd PMOS transistor M3;

The grid of the 14 nmos pass transistor M14 and the 15 nmos pass transistor M15 connects the 15 nmos pass transistor M15 drain electrode, the drain electrode of the 14 nmos pass transistor M14 meets the drain electrode L2 place of the 20 nmos pass transistor M20, the drain electrode of the 15 nmos pass transistor M15 and the 16 nmos pass transistor M16 connects the drain electrode of the 2nd PMOS transistor M2, the grid of the 16 nmos pass transistor M16 connects the drain electrode of the 18 nmos pass transistor M18, the grid of the 17 nmos pass transistor M17 connects the drain electrode of the 15 nmos pass transistor M15, the grid of the 18 nmos pass transistor M18 and the 19 nmos pass transistor M19 all connects the 18 nmos pass transistor M18 drain electrode, the drain electrode of the 19 nmos pass transistor M19 meets the drain electrode L2 place of the 20 nmos pass transistor M20, and the drain electrode of the 18 nmos pass transistor M12 connects the drain electrode of the 4th PMOS transistor M4;

The source ground of the 8th nmos pass transistor M8, the 9th nmos pass transistor M9, the tenth nmos pass transistor M10, the 11 nmos pass transistor M11, the tenth bi-NMOS transistor M12, the 13 nmos pass transistor M13, the 14 nmos pass transistor M14, the 15 nmos pass transistor M15, the 16 nmos pass transistor M16 the 17 nmos pass transistor M17 and the 18 nmos pass transistor M18;

The drain electrode that the grid of the 20 PMOS transistor M20 and the 21 PMOS transistor M21 is all received the 20 PMOS transistor M20, the source electrode of the 20 PMOS transistor M20 and the 21 PMOS transistor M21 connects power supply, the drain electrode of the 20 PMOS transistor M20 connects the drain electrode of the 14 nmos pass transistor M14 and the 19 nmos pass transistor M19, the 8th nmos pass transistor M8 is received in the drain electrode of the 21 PMOS transistor M21, the drain electrode of the 13 nmos pass transistor M13 and the 20 bi-NMOS transistor M22, the drain electrode that the grid of the 20 bi-NMOS transistor M22 and the 23 nmos pass transistor M23 is all received the 20 bi-NMOS transistor M22, the source electrode of the 20 bi-NMOS transistor M22 and the 23 nmos pass transistor M23 is ground connection all, and the drain electrode of the 23 nmos pass transistor M23 connects the drain electrode of load resistance R1 and the 24 PMOS transistor M24;

In the output clamp circuit, load resistance R1 one termination power, the drain electrode of another termination the 23 nmos pass transistor M23 and the 24 PMOS transistor M24, the source electrode of the 24 PMOS transistor M24 connects power supply, and the grid of the 24 PMOS transistor M24 connects the output of operational amplifier OP; The positive pole of operational amplifier OP connects the output offset current potential circuit Replica is provided, and the negative pole of operational amplifier OP connects reference voltage Vref;

The circuit theory diagrams of described operational amplifier OP comprise the 25 PMOS transistor M25, the 26 PMOS transistor M26, the 27 nmos pass transistor M27, the 28 nmos pass transistor M27, the 29 nmos pass transistor M29 as shown in Figure 3; The source class of the 25 PMOS transistor M25 and the 26 PMOS transistor M26 connects power supply, the grid of the 25 PMOS transistor M25 and the 26 PMOS transistor M26 connects the drain electrode of the 25 PMOS transistor M25, the drain electrode of the 25 PMOS transistor M25 connects the drain electrode of the 27 PMOS transistor M27, and the drain electrode of the 26 PMOS transistor M26 and the drain electrode of the 28 nmos pass transistor M28 meet the output OUT of operational amplifier OP ₁, the source electrode of the 27 nmos pass transistor M27 and the 28 nmos pass transistor M28 connects the drain electrode of the 29 nmos pass transistor M29, and the grid of the 29 nmos pass transistor M29 connects biasing BIAS, the source ground of the 29 nmos pass transistor M29.

Traditional received signal intensity detection circuit principle based on logarithmic amplifier is very directly perceived, as shown in Figure 4, adopts the coupling of nonequilibrium source class to, cross-linked input stage and parallel connected output stage.The transistor of nonequilibrium source class coupling centering adopts two kinds of different sizes (β and K β), according to the difference of K value, obtains different input/output relation curves.The input/output relation of logarithmic amplifier presents logarithmic relationship in the certain limit of input signal, this scope is the working range of received signal intensity detection circuit.There is the deficiency of less stable, less dynamic range, the relatively poor linearity in traditional received signal intensity detection circuit based on logarithmic amplifier.Therefore, this patent has improved traditional design, increases the adjunct circuit module, tries hard to overcome above-mentioned defective.

The local positive feedback load circuit provides local regenerative feedback loop among the present invention, under the prerequisite that does not increase the circuit bias electric current, improves the mutual conductance of circuit.Bigger circuit mutual conductance can increase the accessible range of signal of circuit effectively, the ability of enhancement process small intensity signal.Generally speaking, strengthen mutual conductance, will cause the increase of power consumption like this by the bias current that increases circuit.Under the deep submicron process condition, circuit design is more and more stricter to the requirement of power consumption.Therefore, need avoid as much as possible increasing mutual conductance by sacrificing power consumption.Adopt the local positive feedback load, solved the compromise between mutual conductance and power consumption effectively, increased the equivalent transconductance of circuit.In addition, adopt local positive feedback structure of the present invention, can avoid occurring vibration, guarantee the stability of loop.

The purpose of output clamp circuit mainly realizes two aspect functions among the present invention, and at first by increasing a diverter branch, the 24 PMOS transistor M24 and load resistance R1 parallel connection realize the better linearity.Secondly, feedback control loop can be realized the clamper function to the output current potential, avoids the influence of external environment, improves stability.

The reference voltage of feedback control loop is provided by module Replica, and the operating state of this module simulation core circuit when no signal is imported produces the output common mode level.

During use, equally can be with the nonequilibrium source class cross-couplings of organizing different size (β) to parallel connection more, and adopt local positive feedback load, output clamp circuit, the detection range of expansion received signal intensity detection circuit.

Fig. 5 is the novel simulation result of received signal intensity detection circuit under the 0.18umCMOS process conditions based on logarithmic amplifier that this patent proposes, can draw in the scope of-20dBm-0dBm according to curve among the figure, circuit has the favorable linearity transmission characteristic.

The above only is a preferred implementation of the present invention; be noted that for those skilled in the art; under the prerequisite that does not break away from the principle of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (2)

1. received signal intensity detection circuit is characterized in that: described received signal intensity detection circuit comprises that non-equilibrium source class cross-couplings is to circuit, local positive feedback load circuit and output clamp circuit:

Described non-equilibrium source class cross-couplings comprises a PMOS transistor (M1), the 2nd PMOS transistor (M2), the 3rd PMOS transistor (M3), the 4th PMOS transistor (M4), the 5th PMOS transistor (M5), the 6th PMOS transistor (M6), the 7th PMOS transistor (M7) to circuit;

Described local positive feedback load circuit comprises the 8th nmos pass transistor (M8), the 9th nmos pass transistor (M9), the tenth nmos pass transistor (M10), the 11 nmos pass transistor (M11), the tenth bi-NMOS transistor (M12), the 13 nmos pass transistor (M13), the 14 nmos pass transistor (M14), the 15 nmos pass transistor (M15), the 16 nmos pass transistor (M16), the 17 nmos pass transistor (M17), the 18 nmos pass transistor (M18), the 19 nmos pass transistor (M19), the 20 PMOS transistor (M20), the 21 PMOS transistor (M21), the 20 bi-NMOS transistor (M22), the 23 nmos pass transistor (M23);

Described output clamp circuit comprises load resistance (R1), the 24 PMOS transistor (M24), operational amplifier (OP) and realizes providing circuit Replica to non-equilibrium source class cross-couplings to the output offset current potential that duplicates of circuit and local positive feedback load circuit;

Non-equilibrium source class cross-couplings to circuit in, the grid of the one PMOS transistor (M1) and the 2nd PMOS transistor (M2) connects the positive level of radio-frequency input signals, and the grid of the 3rd PMOS transistor (M3) and the 4th PMOS transistor (M4) connects the negative level of radio-frequency input signals; The source class of the one PMOS transistor (M1) and the 2nd PMOS transistor (M2) connects the drain electrode of the 5th PMOS transistor (M5), and the source class of the 3rd PMOS transistor (M3) and the 4th PMOS transistor (M4) connects the drain electrode of the 6th PMOS transistor (M6); The 5th PMOS transistor (M5), the 6th PMOS transistor (M6), the 7th PMOS transistor (M7) are formed current-mirror structure, constitute the biasing circuit that bias current is provided;

In the local positive feedback load circuit, the grid of the 8th nmos pass transistor (M8) and the 9th nmos pass transistor (M9) connects the drain electrode of the 9th nmos pass transistor (M9), the drain electrode of the 8th nmos pass transistor (M8) connects the drain electrode of the 21 nmos pass transistor (M21), the drain electrode of the 9th nmos pass transistor (M9) and the tenth nmos pass transistor (M10) connects the drain electrode of a PMOS transistor (M1), the grid of the tenth nmos pass transistor (M10) connects the drain electrode of the tenth bi-NMOS transistor (M12), the grid of the 11 nmos pass transistor (M11) connects the drain electrode of the tenth nmos pass transistor (M10), the grid of the tenth bi-NMOS transistor (M12) and the 13 nmos pass transistor (M13) all connects the tenth bi-NMOS transistor (M12) drain electrode, the drain electrode of the 13 nmos pass transistor (M13) connects the drain electrode of the 21 nmos pass transistor (M21), and the drain electrode of the tenth bi-NMOS transistor (M12) connects the drain electrode of the 3rd PMOS transistor (M3);

The grid of the 14 nmos pass transistor (M14) and the 15 nmos pass transistor (M15) connects the 15 nmos pass transistor (M15) drain electrode, the drain electrode of the 14 nmos pass transistor (M14) connects the drain electrode of the 20 nmos pass transistor (M20), the drain electrode of the 15 nmos pass transistor (M15) and the 16 nmos pass transistor (M16) connects the drain electrode of the 2nd PMOS transistor (M2), the grid of the 16 nmos pass transistor (M16) connects the drain electrode of the 18 nmos pass transistor (M18), the grid of the 17 nmos pass transistor (M17) connects the drain electrode of the 15 nmos pass transistor (M15), the grid of the 18 nmos pass transistor (M18) and the 19 nmos pass transistor (M19) all connects the 18 nmos pass transistor (M18) drain electrode, the drain electrode of the 19 nmos pass transistor (M19) connects the drain electrode of the 20 nmos pass transistor (M20), and the drain electrode of the 18 nmos pass transistor (M12) connects the drain electrode of the 4th PMOS transistor (M4);

The source ground of the 8th nmos pass transistor (M8), the 9th nmos pass transistor (M9), the tenth nmos pass transistor (M10), the 11 nmos pass transistor (M11), the tenth bi-NMOS transistor (M12), the 13 nmos pass transistor (M13), the 14 nmos pass transistor (M14), the 15 nmos pass transistor (M15), the 16 nmos pass transistor (M16) the 17 nmos pass transistor (M17) and the 18 nmos pass transistor (M18);

The drain electrode that the grid of the 20 PMOS transistor (M20) and the 21 PMOS transistor (M21) is all received the 20 PMOS transistor (M20), the source electrode of the 20 PMOS transistor (M20) and the 21 PMOS transistor (M21) connects power supply, the drain electrode of the 20 PMOS transistor (M20) connects the drain electrode of the 14 nmos pass transistor (M14) and the 19 nmos pass transistor (M19), the 8th nmos pass transistor (M8) is received in the drain electrode of the 21 PMOS transistor (M21), the drain electrode of the 13 nmos pass transistor (M13) and the 20 bi-NMOS transistor (M22), the drain electrode that the grid of the 20 bi-NMOS transistor (M22) and the 23 nmos pass transistor (M23) is all received the 20 bi-NMOS transistor (M22), the source electrode of the 20 bi-NMOS transistor (M22) and the 23 nmos pass transistor (M23) is ground connection all, and the drain electrode of the 23 nmos pass transistor (M23) connects the drain electrode of load resistance (R1) and the 24 PMOS transistor (M24);

In the output clamp circuit, load resistance (R1) termination power, the drain electrode of another termination the 23 nmos pass transistor (M23) and the 24 PMOS transistor (M24), the source electrode of the 24 PMOS transistor (M24) connects power supply, and the grid of the 24 PMOS transistor (M24) connects the output of operational amplifier (OP); The positive pole of operational amplifier (OP) connects the output that the output offset current potential provides circuit Replica, and the negative pole of operational amplifier (OP) connects reference voltage.

2. received signal intensity detection circuit according to claim 1 is characterized in that: described operational amplifier (OP) comprises the 25 PMOS transistor (M25), the 26 PMOS transistor (M26), the 27 nmos pass transistor (M27), the 28 nmos pass transistor (M27), the 29 nmos pass transistor (M29); The source class of the 25 PMOS transistor (M25) and the 26 PMOS transistor (M26) connects power supply, the grid of the 25 PMOS transistor (M25) and the 26 PMOS transistor (M26) connects the drain electrode of the 25 PMOS transistor (M25), the drain electrode of the 25 PMOS transistor (M25) connects the drain electrode of the 27 PMOS transistor (M27), the drain electrode of the 26 PMOS transistor (M26) and the drain electrode of the 28 nmos pass transistor (M28) connect the output of operational amplifier (OP), the source electrode of the 27 nmos pass transistor (M27) and the 28 nmos pass transistor (M28) connects the drain electrode of the 29 nmos pass transistor (M29), the grid of the 29 nmos pass transistor (M29) connects biasing BIAS, the source ground of the 29 nmos pass transistor (M29).

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