CN109728786A - A kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier - Google Patents
A kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier Download PDFInfo
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- CN109728786A CN109728786A CN201910154186.9A CN201910154186A CN109728786A CN 109728786 A CN109728786 A CN 109728786A CN 201910154186 A CN201910154186 A CN 201910154186A CN 109728786 A CN109728786 A CN 109728786A
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Abstract
The invention discloses a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifiers, it is related to operation transconductance amplifier technical field, solve the problems, such as existing amplifier there are gains that low, output pole frequency is low and circuit stability is poor, its key points of the technical solution are that: the biasing circuit of bias voltage is provided including two-stage amplifying circuit, damping factor control modular circuit and for circuit structure；The first order of two-stage amplifying circuit is PMOS tube Differential Input amplifying circuit, and the second level is the complementary push-pull driving circuit of common source gain stage；Damping factor control modular circuit is connect with the output end of PMOS tube Differential Input amplifying circuit；The first capacitor C1 for being used to form miller compensation access is equipped between the output end and input terminal of the complementary push-pull driving circuit of common source gain stage, it being capable of stabilizing circuit, in the case where entire circuit is in low-power consumption, also have the effect of improving gain, common-mode rejection ratio and the power supply rejection ratio of circuit.
Description
Technical field
The present invention relates to operation transconductance amplifier technical fields, more specifically, it relates to a kind of intersection construction high-gain
Two-stage calculation trsanscondutance amplifier.
Background technique
Operation transconductance amplifier is compared with a part indispensable in multisystem, as a kind of fortune for eliminating Buffer output
Amplifier is calculated, operation transconductance amplifier output impedance with higher is a kind of voltage/current mode hybrid circuit, performance
The performance for determining entire IC system becomes the research hotspot of microelectronic field.
Currently, existing two-stage calculation amplifier structure is generally simple two-stage operational amplifier configuration, telescopic common source
Common gate structure and Foldable cascade structure.Wherein, the gain of simple operation amplifier architecture is often relatively low, it is difficult to reach
Real requirement；And telescopic and accordion structure can be such that transistor size increases, and improve the complexity of circuit, and both are tied
Structure is all using the output impedance of increasing circuit as starting point, to improve gain, but excessive output resistance can also cause to export
The frequency of pole reduces, and reduces the stability of circuit.
Two-stage calculation structure in the prior art, as shown in Figure 1, including forming difference by PMOS tube M1 and PMOS tube M2 to put
The input pipe of big device circuit constitutes one group of current mirror by NMOS tube M3 and NMOS tube M4, is made of NMOS tube M5 and NMOS tube M6
One group of current mirror and one group of current mirror is constituted by PMOS tube M7 and PMOS tube M8；NMOS tube M3 is connected with the drain electrode of PMOS tube M1
And the active load as PMOS tube M1, NMOS tube M5 are connected with the drain electrode of PMOS tube M2 and as the active negative of PMOS tube M2
It carries；The source electrode of the drain electrode connection PMOS tube M1 and PMOS tube M2 of PMOS tube M9 is as current source.Resistance R1, R2, R3 and NMOS
Pipe M12 constitutes biasing circuit, provides suitable grid voltage for PMOS tube M9.
The drain electrode of PMOS tube M9 exports first order amplified signal, and PMOS tube M10 and NMOS tube M11 constitute second level amplification electricity
Road, the drain electrode of PMOS tube M10 connect the drain electrode of NMOS tube M11, export second level amplified signal between drain junction, as scheme
Output voltage Vout in 1.Capacitor Cc and resistance Rc constitutes miller compensation structure, and capacitor CL is the load electricity of amplifier circuit
Hold.
Positive phase input signal Vi1 is inputted from the grid of PMOS tube M1, and the grid of rp input signal Vi2 from PMOS tube M2 are defeated
Enter, after being amplified by first order amplifier circuit, is exported from the drain electrode of PMOS tube M10, i.e. the gain of first order amplifying circuit is
One negative value illustrates that output signal is the amplification to input signal and reverse phase；The output of first order amplifying circuit is as second
The input of grade amplifying circuit is inputted from PMOS tube M10, and the gain of second level amplifier circuit is also negative value.Output signal and ground
Between connect load capacitance CL.
Therefore, how to design a kind of circuit stability, low-power consumption, high-gain two-stage calculation trsanscondutance amplifier be we at present
Problem in the urgent need to address.
Summary of the invention
The object of the present invention is to provide a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifiers, have in circuit stability
In the case where low-power consumption, the gain of circuit, the effect of common-mode rejection ratio and power supply rejection ratio are improved.
Above-mentioned technical purpose of the invention has the technical scheme that a kind of intersection construction high-gain two
Grade operation transconductance amplifier, including two-stage amplifying circuit, damping factor control modular circuit and biased electrical is provided for circuit structure
The biasing circuit of pressure；
The first order amplifying circuit of the two-stage amplifying circuit is PMOS tube Differential Input amplifying circuit, second level amplification electricity
Road is the complementary push-pull driving circuit of common source gain stage；The output end and the common source of the PMOS tube Differential Input amplifying circuit
The input terminal of the complementary push-pull driving circuit of gain stage connects；
The damping factor control modular circuit is connect with the output end of the PMOS tube Differential Input amplifying circuit；
It is equipped between the output end and input terminal of the complementary push-pull driving circuit of the common source gain stage and is used to form Miller
Compensate the first capacitor C1 of access.
By using above-mentioned technical proposal, first order amplifying circuit uses PMOS tube Differential Input amplifying circuit, so that electric
Road has lower input noise and input common mode electrical level；Second level amplifying circuit is driven using the complementary push-pull of common source gain stage
Circuit improves the gain of circuit, and reduces quiescent current；Damping factor control modular circuit and first capacitor C1 are collectively formed
Frequency compensation structure, the miller compensation access that first capacitor C1 is formed provide dominant pole for circuit, convenient for improving circuit stability.
The present invention is further arranged to: the PMOS tube Differential Input amplifying circuit includes constitute the input of four pipes first
MOS transistor M1a, the second MOS transistor M1b, third MOS transistor M2a and the 4th MOS transistor M2b；First MOS
The grid of transistor M1a and the second MOS transistor M1b connect input voltage Vi1 in the same direction；The third MOS transistor M2a and
The grid of four MOS transistor M2b connects reversed input voltage Vi2.
By using above-mentioned technical proposal, using the grid group of the first MOS transistor M1a and the second MOS transistor M1b as
The non-inverting input terminal of first order amplifying circuit, and the grid group of third MOS transistor M2a and the 4th MOS transistor M2b are made
For the inverting input terminal of first order amplifying circuit, convenient for improving the input mutual conductance of first order amplifying circuit, and then entire electricity is improved
The voltage gain on road.
The present invention is further arranged to: the first MOS transistor M1a's and the second MOS transistor M1b passes through electricity
The electric current ratio of stream is 1:3.
By using above-mentioned technical proposal, convenient for improving the input impedance of first order amplifying circuit.
The present invention is further arranged to: the PMOS tube Differential Input amplifying circuit further includes by the 7th NMOS tube M5a,
Eight NMOS tube M5b, the 9th NMOS tube M6a and the tenth NMOS tube M6b composition current mirror and the 11st PMOS as current source
Pipe M7；The source electrode of the 11st PMOS tube M7 connects supply voltage VDD, the drain electrode connection described first of the 11st PMOS tube M7
The source electrode of MOS transistor M1a, the second MOS transistor M1b, third MOS transistor M2a and the 4th MOS transistor M2b.
By using above-mentioned technical proposal, active electric current mirror is matched with input mos transistor, convenient for being circuit knot
Structure provides multithread bias current.
The present invention is further arranged to: the PMOS tube Differential Input amplifying circuit further includes the 5th NMOS tube M3 and the 6th
NMOS tube M4, the drain electrode of the 5th NMOS tube M3 and the 6th NMOS tube M4 be cross connected to respectively the first MOS transistor M1a and
The drain electrode of third MOS transistor M2a；The source electrode of the 5th NMOS tube M3 and the 6th NMOS tube M4 respectively with the 7th NMOS tube
The drain electrode of M5a and the 9th NMOS tube M6a connect.
By using above-mentioned technical proposal, current mirror and input mos transistor are connected by excessively cross-linked mode,
Convenient for improving the matching of current mirror.
The present invention is further arranged to: the PMOS tube Differential Input amplifying circuit further includes the 12nd PMOS tube M8,
13 PMOS tube M9, the 14th NMOS tube M10 and the 15th NMOS tube M11；The 12nd PMOS tube M8, the 13rd PMOS tube
M9 and the 14th NMOS tube M10, the 15th NMOS tube M11 grid two-by-two be connected after form two groups of current mirrors；Described tenth
The source electrode of two PMOS tube M8 and the 13rd PMOS tube M9 connects supply voltage VDD；The 14th NMOS tube M10 and the 15th
The source electrode of NMOS tube M11 is grounded.
By using above-mentioned technical proposal, using two groups of current mirrors, convenient for improving the precision of current mirror.
The present invention is further arranged to: the complementary push-pull driving circuit of the common source gain stage includes the 16th PMOS tube
M12 and the 17th NMOS tube M13；The source electrode of the 16th PMOS tube M12 connects supply voltage VDD, the 16th PMOS tube M12
Drain electrode connect with the drain electrode of the 17th NMOS tube M13；The grid of the 16th PMOS tube M12 and the PMOS tube are poor
Divide the output end connection of input amplifying circuit, the source electrode ground connection of the 17th NMOS tube M13.
By using above-mentioned technical proposal, the output of the grid connection first order amplifying circuit of the 16th MOS transistor M12
Hold the input terminal as second level amplifying circuit, the output end of the drain electrode connection second level amplifying circuit of the 17th NMOS tube M13
And current source load, the 16th MOS transistor M12 and the 17th NMOS tube M13 composition second are provided for second level amplifying circuit
Grade amplifying circuit, constitutes the complementary push-pull driving circuit of common source gain stage.
The present invention is further arranged to: the biasing circuit includes the 18th NMOS tube M14 and first resistor R1, the second electricity
Hinder R2 and 3rd resistor R3；The drain electrode of the 18th NMOS tube M14 is connected with the first resistor R1,18 NMOS tube
The drain electrode of M14 is connect as the output end of biasing circuit with the grid of the 11st PMOS tube M7.
By using above-mentioned technical proposal, using the clamping action of the gate source voltage VGS of 18 NMOS tube M14, and use
Second resistance R2 and the concatenated multiplier effect of 3rd resistor R3, provide the bias voltage of relationship proportional to VGS.
The present invention is further arranged to: the damping factor control modular circuit includes the 19th PMOS tube M15, the 20th
NMOS tube M16, the 4th resistance RDFC and the second capacitor CDFC；After the 4th resistance RDFC and the second capacitor CDFC series connection, the
Another terminals of four resistance RDFC are connect with the grid of the 19th PMOS tube M15, another terminals of the second capacitor CDFC with
The drain electrode of 20th NMOS tube M16 connects.
By using above-mentioned technical proposal, convenient for enhancing the stability of circuit while providing gain.
In conclusion the invention has the following advantages: first order amplifying circuit is amplified using PMOS tube Differential Input
Circuit, so that circuit has lower input noise and input common mode electrical level；Second level amplifying circuit is using common source gain stage
Complementary push-pull driving circuit improves the gain of circuit, and reduces quiescent current；Damping factor control modular circuit and the first electricity
Hold C1 and collectively form frequency compensation structure, the miller compensation access that first capacitor C1 is formed provides dominant pole for circuit, convenient for mentioning
High circuit stability；By it is traditional to pipe input become four pipes input after, recycle matched active electric current mirror conduct
Differential pair input transistors are loaded and be cross connected to, input mutual conductance is improved.
Detailed description of the invention
Fig. 1 is the circuit diagram of the symmetrical trsanscondutance amplifier of PMOS Differential Input in the prior art；
Fig. 2 is the circuit diagram of the intersection construction high-gain two-stage calculation trsanscondutance amplifier in the embodiment of the present invention；
Fig. 3 is the comparison figure that the amplitude-versus-frequency curve that ac small signal simulating, verifying obtains is carried out to Fig. 1 and Fig. 2；
Fig. 4 is the comparison figure that the phase-frequency characteristic curve that ac small signal simulating, verifying obtains is carried out to Fig. 1 and Fig. 2；
Fig. 5 is to carry out the common-mode rejection ratio simulation curve figure that ac small signal simulating, verifying obtains to Fig. 1；
Fig. 6 is to carry out the common-mode rejection ratio simulation curve figure that ac small signal simulating, verifying obtains to Fig. 2；
Fig. 7 is to carry out the power supply rejection ratio simulation curve figure that ac small signal simulating, verifying obtains to Fig. 1；
Fig. 8 is to carry out the power supply rejection ratio simulation curve figure that ac small signal simulating, verifying obtains to Fig. 2；
Fig. 9 is the comparison figure that the output voltage Transient curve that Transient is verified is carried out to Fig. 1 and Fig. 2；
Figure 10 is the comparison that the equivalent inpnt reference noise simulation curve that noise Simulation is verified is carried out to Fig. 1 and Fig. 2
Figure.
Specific embodiment
Below in conjunction with attached drawing 1-10, invention is further described in detail.
It should also be noted that in the present invention, term " first ", " second " etc. are only used for distinguishing description, and should not be understood as referring to
Show or imply relative importance.
Embodiment: a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier, as shown in Fig. 2, including two-stage amplification electricity
Road, damping factor control modular circuit and the biasing circuit of bias voltage is provided for circuit structure.The first of two-stage amplifying circuit
Grade amplifying circuit is PMOS tube Differential Input amplifying circuit, and second level amplifying circuit is that the complementary push-pull of common source gain stage drives electricity
Road.The output end of PMOS tube Differential Input amplifying circuit together the complementary push-pull driving circuit of source gain grade input terminal connection.
Damping factor control modular circuit is connect with the output end of PMOS tube Differential Input amplifying circuit.The complementary push-pull of common source gain stage
The first capacitor C1 for being used to form miller compensation access is equipped between the output end and input terminal of driving circuit.First order amplification electricity
Road uses PMOS tube Differential Input amplifying circuit, so that circuit has lower input noise and input common mode electrical level.The second level
Amplifying circuit uses the complementary push-pull driving circuit of common source gain stage, improves the gain of circuit, and reduce quiescent current.Damping
Factor control module circuit and first capacitor C1 collectively form frequency compensation structure, the miller compensation access that first capacitor C1 is formed
Dominant pole is provided for circuit, convenient for improving circuit stability.
PMOS tube Differential Input amplifying circuit includes the first MOS transistor M1a for constituting the input of four pipes, the 2nd MOS crystal
Pipe M1b, third MOS transistor M2a and the 4th MOS transistor M2b.First MOS transistor M1a's and the second MOS transistor M1b
Grid connects input voltage Vi1 in the same direction.The reversed input of the grid of third MOS transistor M2a and the 4th MOS transistor M2b connection
Voltage Vi2.Using the grid group of the first MOS transistor M1a and the second MOS transistor M1b as the same phase of first order amplifying circuit
Input terminal, and using the grid group of third MOS transistor M2a and the 4th MOS transistor M2b as the anti-of first order amplifying circuit
Phase input terminal convenient for improving the input mutual conductance of first order amplifying circuit, and then improves the voltage gain of entire circuit.
The electric current ratio by electric current of first MOS transistor M1a and the second MOS transistor M1b is 1:3, convenient for improving the
The input impedance of level-one amplifying circuit.
PMOS tube Differential Input amplifying circuit further includes by the 7th NMOS tube M5a, the 8th NMOS tube M5b, the 9th NMOS tube
M6a and the tenth NMOS tube M6b composition current mirror and the 11st PMOS tube M7 as current source.7th NMOS tube M5a and
It is 1:3 that eight NMOS tube M5b and the 9th NMOS tube M6a and the tenth NMOS tube M6b, which constitute the electric current ratio flowed through when current mirror load,.
The first MOS transistor M1a of drain electrode connection of source electrode connection the supply voltage VDD, the 11st PMOS tube M7 of 11st PMOS tube M7,
The source electrode of second MOS transistor M1b, third MOS transistor M2a and the 4th MOS transistor M2b.By active electric current mirror and input
MOS transistor is matched, convenient for providing multithread bias current for circuit structure.
PMOS tube Differential Input amplifying circuit further includes the 5th NMOS tube M3 and the 6th NMOS tube M4, the 5th NMOS tube M3 and
The drain electrode of 6th NMOS tube M4 is cross connected to the drain electrode of the first MOS transistor M1a and third MOS transistor M2a respectively.5th
The source electrode of NMOS tube M3 and the 6th NMOS tube M4 are connect with the drain electrode of the 7th NMOS tube M5a and the 9th NMOS tube M6a respectively.It will be electric
Stream mirror and input mos transistor are connected by excessively cross-linked mode, convenient for improving the matching of current mirror.
PMOS tube Differential Input amplifying circuit further includes the 12nd PMOS tube M8, the 13rd PMOS tube M9, the 14th NMOS
Pipe M10 and the 15th NMOS tube M11.12nd PMOS tube M8, the 13rd PMOS tube M9 and the 14th NMOS tube M10, the tenth
The grid of five NMOS tube M11 forms two groups of current mirrors after being connected two-by-two.The source of 12nd PMOS tube M8 and the 13rd PMOS tube M9
Pole connects supply voltage VDD.The source electrode of 14th NMOS tube M10 and the 15th NMOS tube M11 is grounded.Using two groups of current mirrors,
Convenient for improving the precision of current mirror.
In other possible embodiments, the first MOS transistor M1a, the second MOS transistor M1b, third MOS transistor M2a
NMOS tube can also be used with the 4th MOS transistor M2b, corresponding load and tail current source also make corresponding change.
The complementary push-pull driving circuit of common source gain stage includes the 16th PMOS tube M12 and the 17th NMOS tube M13.Tenth
The source electrode of six PMOS tube M12 connects supply voltage VDD, the drain electrode and the drain electrode of the 17th NMOS tube M13 of the 16th PMOS tube M12
Connection.The grid of 16th PMOS tube M12 is connect with the output end of PMOS tube Differential Input amplifying circuit, the 17th NMOS tube
The source electrode of M13 is grounded.The output end of the grid connection first order amplifying circuit of 16th MOS transistor M12 is put as the second level
The input terminal of big circuit, the output end of the drain electrode connection second level amplifying circuit of the 17th NMOS tube M13 simultaneously amplify for the second level
Circuit provides current source load, and the 16th MOS transistor M12 and the 17th NMOS tube M13 form second level amplifying circuit, constitute
The complementary push-pull driving circuit of common source gain stage.
In other possible embodiments, the signal amplifying part of the complementary push-pull driving circuit of common source gain stage point also can be by
NMOS tube composition, corresponding current source load are changed to PMOS tube.
Biasing circuit includes the 18th NMOS tube M14 and first resistor R1, second resistance R2 and 3rd resistor R3.18th
The drain electrode of NMOS tube M14 is connected with first resistor R1, and the drain electrode of 18 NMOS tube M14 is as the output end of biasing circuit and the tenth
The grid of one PMOS tube M7 connects.Using the clamping action of the gate source voltage VGS of 18 NMOS tube M14, and use second resistance
R2 and the concatenated multiplier effect of 3rd resistor R3, provide the bias voltage of relationship proportional to VGS.
Damping factor control modular circuit includes the 19th PMOS tube M15, the 20th NMOS tube M16, the 4th resistance RDFC
With the second capacitor CDFC；After 4th resistance RDFC and the second capacitor CDFC series connection, another terminals of the 4th resistance RDFC and the
The grid of 19 PMOS tube M15 connects, and another terminals of the second capacitor CDFC are connect with the drain electrode of the 20th NMOS tube M16,
Convenient for enhancing the stability of circuit while providing gain.
Based on 0.13 μm of technique, to the symmetrical transconductance amplifier circuit and Fig. 2 of tradition PMOS Differential Input shown in Fig. 1
Shown in intersection construction high-gain two-stage calculation transconductance amplifier circuit carry out simulating, verifying:
Simulating, verifying 1: direct current simulation analysis is carried out to circuit shown in circuit shown in Fig. 1 and Fig. 2, it is ensured that all members in circuit
Device can work normally；
Simulating, verifying 2: ac small signal simulation analysis is carried out to circuit shown in circuit shown in Fig. 1 and Fig. 2, obtains Fig. 1 institute
The comparison figure of the amplitude-versus-frequency curve and phase-frequency characteristic curve that show circuit shown in circuit and Fig. 2 distinguishes as shown in Figure 3, Figure 4, horizontal seat
Mark is all frequency；Comparing it is found that the low-frequency voltage gain of tradition amplifier shown in FIG. 1 is 63.7dB, phase margin is 76.6 °,
Unity gain bandwidth is 7.894MHz, and the low-frequency voltage gain of present pre-ferred embodiments shown in Fig. 2 is 102.7dB, phase
Position nargin (PM) is 55 °, unity gain bandwidth 2.845MHz, therefore the embodiment of the present invention can obtain high-gain, low-frequency voltage
Gain has been increased to 102.7dB from 63.7dB, and 55 ° of PM can also meet the requirement of circuit stability, Neng Gougeng well
Amplify input signal well.
Simulating, verifying 3: simulating, verifying point is carried out to the common-mode rejection ratio (CMRR) of circuit shown in circuit shown in Fig. 1 and Fig. 2
Analysis, simulate the differential gain diff_gain and common-mode gain cm_gain of two circuits respectively, can be obtained circuit shown in Fig. 1 and
The common-mode rejection ratio simulation curve difference of circuit shown in Fig. 2 is as shown in Figure 5, Figure 6；Analysis is it is found that tradition amplifier shown in FIG. 1
It is 93.34dB when CMRR low frequency stabilization, and is when the CMRR low frequency of present pre-ferred embodiments shown in Fig. 2 stabilization
133.34dB, therefore the embodiment of the present invention can be improved the common-mode rejection ratio of circuit, CMRR is increased to from 93.34dB
133.34dB can preferably inhibit and eliminate the common mode interference in circuit.
Simulating, verifying 4: simulating, verifying point is carried out to the power supply rejection ratio (PSRR) of circuit shown in circuit shown in Fig. 1 and Fig. 2
Fig. 1 can be obtained to the gain vdd_gain of output in analysis, the differential gain diff_gain and power supply for simulating two circuits respectively
The power supply rejection ratio simulation curve difference of circuit shown in shown circuit and Fig. 2 is as shown in Figure 7, Figure 8；Analysis is it is found that shown in FIG. 1
It is 64.7dB when the PSRR low frequency stabilization of traditional amplifier, and when the PSRR low frequency of present pre-ferred embodiments shown in Fig. 2 stabilization
For 86.1dB, therefore the embodiment of the present invention can be improved the power supply rejection ratio of circuit, and PSRR has increased to 86.1dB, energy from 64.7dB
It is enough preferably to inhibit power supply noise.
Simulating, verifying 5: the carry out Transient analysis to circuit shown in circuit shown in Fig. 1 and Fig. 2, by shown homophase input
One rectangular wave power supply of Vi1 connection is held, the output end of shown inverting input terminal Vi2 connection circuit obtains circuit and figure shown in Fig. 1
The comparison figure of the output voltage Transient curve of circuit shown in 2 is as shown in figure 9, it is Slew Rate that it, which changes slope,；Compare it is found that scheming
The Slew Rate of tradition amplifier shown in 1 is 5V/ μ s, is slightly less than the Slew Rate 7V/ μ s of present pre-ferred embodiments shown in Fig. 2, just real
For the situation of border, because shown two circuits all work under conditions of low quiescent current, power consumption is lower, therefore Slew Rate is all inclined
It is small.
Simulating, verifying 6: to circuit shown in circuit shown in Fig. 1 and Fig. 2 progress equivalent inpnt reference noise simulation analysis,
The comparison figure for obtaining the equivalent inpnt reference noise simulation curve of circuit shown in circuit and Fig. 2 shown in Fig. 1 is as shown in Figure 10；Compare
It is found that in same frequency f=100kHz, the equivalent inpnt reference noise of tradition amplifier shown in FIG. 1 isThe equivalent inpnt reference noise of present pre-ferred embodiments shown in Fig. 2 isComparatively, low frequency range noise is bigger, gradually decreases and goes to zero with the raising noise of frequency.
Working principle: first order amplifying circuit uses PMOS tube Differential Input amplifying circuit, so that circuit is with lower
Input noise and input common mode electrical level.Second level amplifying circuit uses the complementary push-pull driving circuit of common source gain stage, improves electricity
The gain on road, and reduce quiescent current.Damping factor control modular circuit and first capacitor C1 collectively form frequency compensation knot
Structure, the miller compensation access that first capacitor C1 is formed provide dominant pole for circuit, convenient for improving circuit stability.By traditional pair
After pipe input becomes the input of four pipes, recycle matched active electric current mirror defeated as loading and being cross connected to differential pair
Enter transistor, improves input mutual conductance.
This specific embodiment is only explanation of the invention, is not limitation of the present invention, those skilled in the art
Member can according to need the modification that not creative contribution is made to the present embodiment after reading this specification, but as long as at this
All by the protection of Patent Law in the scope of the claims of invention.
Claims (9)
1. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier, it is characterized in that: including two-stage amplifying circuit, damping factor
Control module circuit and the biasing circuit of bias voltage is provided for circuit structure；
The first order amplifying circuit of the two-stage amplifying circuit is PMOS tube Differential Input amplifying circuit, and second level amplifying circuit is
The complementary push-pull driving circuit of common source gain stage；The output end of the PMOS tube Differential Input amplifying circuit and the common source gain
The input terminal connection of the complementary push-pull driving circuit of grade；
The damping factor control modular circuit is connect with the output end of the PMOS tube Differential Input amplifying circuit；
It is equipped between the output end and input terminal of the complementary push-pull driving circuit of the common source gain stage and is used to form miller compensation
The first capacitor C1 of access.
2. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 1, it is characterized in that: described
PMOS tube Differential Input amplifying circuit includes the first MOS transistor M1a for constituting the input of four pipes, the second MOS transistor M1b, the
Three MOS transistor M2a and the 4th MOS transistor M2b；The grid of the first MOS transistor M1a and the second MOS transistor M1b
Connect input voltage Vi1 in the same direction；The reversed input of grid connection of the third MOS transistor M2a and the 4th MOS transistor M2b
Voltage Vi2.
3. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 2, it is characterized in that: described
The electric current ratio by electric current of one MOS transistor M1a and the second MOS transistor M1b is 1:3.
4. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 2, it is characterized in that: described
PMOS tube Differential Input amplifying circuit further includes by the 7th NMOS tube M5a, the 8th NMOS tube M5b, the 9th NMOS tube M6a and the tenth
NMOS tube M6b forms current mirror and the 11st PMOS tube M7 as current source；The source electrode of the 11st PMOS tube M7 connects
Meet supply voltage VDD, the drain electrode of the 11st PMOS tube M7 connect the first MOS transistor M1a, the second MOS transistor M1b,
The source electrode of third MOS transistor M2a and the 4th MOS transistor M2b.
5. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 4, it is characterized in that: described
PMOS tube Differential Input amplifying circuit further includes the 5th NMOS tube M3 and the 6th NMOS tube M4, the 5th NMOS tube M3 and the 6th NMOS
The drain electrode of pipe M4 is cross connected to the drain electrode of the first MOS transistor M1a and third MOS transistor M2a respectively；Described 5th
The source electrode of NMOS tube M3 and the 6th NMOS tube M4 are connect with the drain electrode of the 7th NMOS tube M5a and the 9th NMOS tube M6a respectively.
6. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 5, it is characterized in that: described
PMOS tube Differential Input amplifying circuit further includes the 12nd PMOS tube M8, the 13rd PMOS tube M9, the 14th NMOS tube M10 and
15 NMOS tube M11；The 12nd PMOS tube M8, the 13rd PMOS tube M9 and the 14th NMOS tube M10, the 15th NMOS
The grid of pipe M11 forms two groups of current mirrors after being connected two-by-two；The source electrode of 12nd the PMOS tube M8 and the 13rd PMOS tube M9
Connect supply voltage VDD；The source electrode of the 14th NMOS tube M10 and the 15th NMOS tube M11 is grounded.
7. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier according to claim 1, it is characterized in that: described total
The complementary push-pull driving circuit of source gain grade includes the 16th PMOS tube M12 and the 17th NMOS tube M13；16th PMOS
The source electrode of pipe M12 connects supply voltage VDD, and the drain electrode of the 16th PMOS tube M12 connects with the drain electrode of the 17th NMOS tube M13
It connects；The grid of the 16th PMOS tube M12 is connect with the output end of the PMOS tube Differential Input amplifying circuit, and the described tenth
The source electrode of seven NMOS tube M13 is grounded.
8. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier described in -7 any one according to claim 1, special
Sign is: the biasing circuit includes the 18th NMOS tube M14 and first resistor R1, second resistance R2 and 3rd resistor R3；It is described
The drain electrode of 18th NMOS tube M14 is connected with the first resistor R1, and the drain electrode of the 18 NMOS tube M14 is as biasing circuit
Output end connect with the grid of the 11st PMOS tube M7.
9. a kind of intersection construction high-gain two-stage calculation trsanscondutance amplifier described in -7 any one according to claim 1, special
Sign is: the damping factor control modular circuit includes the 19th PMOS tube M15, the 20th NMOS tube M16, the 4th resistance RDFC
With the second capacitor CDFC；After the 4th resistance RDFC and the second capacitor CDFC series connection, another terminals of the 4th resistance RDFC
It is connect with the grid of the 19th PMOS tube M15, the drain electrode of another terminals and the 20th NMOS tube M16 of the second capacitor CDFC connects
It connects.
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| CN113014246A (en) * | 2021-02-20 | 2021-06-22 | 广东省科学院半导体研究所 | Voltage level shifter and electronic device |
| CN113285673A (en) * | 2021-02-03 | 2021-08-20 | 深圳市中科蓝讯科技股份有限公司 | Radio frequency amplifying circuit, radio frequency front end receiving circuit and wireless communication equipment |
| CN113489462A (en) * | 2021-07-29 | 2021-10-08 | 北京京东方传感技术有限公司 | Voltage amplification circuit, sensor and electronic equipment |
| CN116317996A (en) * | 2023-05-23 | 2023-06-23 | 盈力半导体(上海)有限公司 | Error amplifier and power supply conversion device |
| CN116629186A (en) * | 2023-05-23 | 2023-08-22 | 广东匠芯创科技有限公司 | Layout design method and layout structure of two-stage fully differential operational amplifier |
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