CN116629186B - Layout design method and layout structure of two-stage fully differential operational amplifier - Google Patents
Layout design method and layout structure of two-stage fully differential operational amplifier Download PDFInfo
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- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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Abstract
The invention discloses a layout design method and a layout structure of a two-stage fully differential operational amplifier. The layout structure comprises: the first edition region, the second edition region, the third edition region and the fourth edition region are sequentially arranged in parallel from left to right; the first layout area comprises: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom; the second layout area includes: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom; the third layout region includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom; the fourth layout area includes: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom. The layout structure has clear signal flow direction, small circuit performance loss caused by parasitic parameters and high post-simulation passing rate.
Description
Technical Field
The invention relates to the technical field of CMOS analog integrated circuit layout design, in particular to a layout design method and a layout structure of a two-stage fully differential operational amplifier.
Background
CMOS analog integrated circuit layout design is a process of performing accurate physical description of a finished created circuit netlist, which must meet the common constraints of design flow, manufacturing process and circuit performance index at the same time. CMOS analog integrated circuits are more sensitive to parasitic parameters than digital integrated circuits, and therefore, in the case where the front simulation meets the design requirements, the back simulation is not necessarily able to meet the design requirements. In the deep submicron stage, the effect of parasitics on the circuit is more pronounced. In the chip design process, the application scene of the amplifier is very many, and the operational amplifier layout directly influences the overall performance of the circuit. Two-stage fully differential operational amplifiers are often used in circuit layouts that have high demands on circuit performance.
In the related art, due to unreasonable planning in the layout structure of the two-stage fully differential operational amplifier layout, the signal flow direction is unclear, parasitic parameters generated by the layout can greatly reduce the performance of the circuit, and the post-simulation passing rate of the layout is low.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein.
The embodiment of the invention provides a layout design method and a layout structure of a two-stage fully differential operational amplifier, which can be used for carrying out layout according to circuit functions to obtain the layout structure of the two-stage fully differential operational amplifier, wherein the signal flow of the layout structure is clear, the circuit performance loss caused by parasitic parameters is small, and the post-simulation passing rate is high.
In a first aspect, an embodiment of the present invention provides a layout structure of a two-stage fully differential operational amplifier, including:
the first edition region, the second edition region, the third edition region and the fourth edition region are sequentially arranged in parallel from left to right;
the first layout area comprises: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom;
the second layout area comprises: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom;
the third layout area includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom;
the fourth layout area comprises: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom;
the current mirror layout area is respectively connected with the bias circuit board area, the differential pair-transistor board area, the common mode feedback transistor board area and the first-stage load transistor layout area;
the common mode feedback pipe plate region is respectively connected with the first common mode capacitance array plate region, the second common mode capacitance array plate region, the first resistance array plate region and the second resistance array plate region;
the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region.
In some embodiments, the differential pair piping plot, the common mode feedback piping plot, and the first stage load piping plot all exhibit a common centroid match.
In some embodiments, the bias circuit board regions are symmetrically matched.
In some embodiments, the first common-mode capacitor array layout area and the second common-mode capacitor array layout area have the same shape and size and are distributed symmetrically left and right about a symmetry axis; the first resistor array plate region and the second resistor array plate region have the same shape and size and are distributed symmetrically about a symmetry axis; the first compensation capacitor array plate area and the second compensation capacitor array plate area have the same shape and size and are distributed symmetrically about a symmetry axis.
In some embodiments, further comprising: the differential signal input port and the differential signal output port are symmetrically arranged, the differential signal input port is arranged at the center position of the uppermost edge of the overall layout, and the differential signal output port is arranged at the center position of the lowermost edge of the overall layout.
In a second aspect, an embodiment of the present invention provides a layout design method for a two-stage fully differential operational amplifier, including:
setting a first edition of region, a second edition of region, a third edition of region and a fourth edition of region which are sequentially arranged in parallel from left to right;
setting the first layout area comprises the following steps: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom;
setting the second layout area comprises the following steps: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom;
setting the third layout area comprises the following steps: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom;
setting the fourth layout area comprises the following steps: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom;
the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region;
the common mode feedback tube plate region and the first common mode capacitor array plate region are respectively carried out; the second common mode capacitor array version region; the first resistor array plate area is connected with the second resistor array plate area;
and the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region.
In some embodiments, the differential pair stencil area, the common mode feedback stencil area and the first stage load stencil area are subjected to common centroid matching layout respectively, so that the differential pair stencil area, the common mode feedback stencil area and the first stage load stencil area are all subjected to common centroid matching.
In some embodiments, the bias circuit board regions are symmetrically matched in structure, and the bias circuit board regions are obtained to be symmetrically matched.
In some embodiments, the first common-mode capacitor array layout area and the second common-mode capacitor array layout area are arranged to have the same shape and size and are distributed symmetrically left and right about a symmetry axis; setting the first resistance array plate region and the second resistance array plate region to have the same shape and size and to be distributed symmetrically about a symmetry axis; the first compensation capacitor array plate area and the second compensation capacitor array plate area are arranged to be the same in shape and size and distributed symmetrically about a symmetry axis.
In some embodiments, further comprising: the method comprises the steps of symmetrically arranging a differential signal input port and a differential signal output port, arranging the differential signal input port at the center position of the uppermost edge of the overall layout, and arranging the differential signal output port at the center position of the lowermost edge of the overall layout.
The embodiment of the invention comprises the following steps: when designing a layout of a two-stage fully differential operational amplifier, firstly, a first edition of region, a second edition of region, a third edition of region and a fourth edition of region which are sequentially arranged in parallel from left to right are arranged; then, setting the first layout area includes: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom; next, setting the second layout region includes: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom; then, setting the third layout area includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom; then, setting the fourth layout region includes: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom; finally, the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region; respectively connecting the common mode feedback tube plate region with the first common mode capacitor array plate region; a second common mode capacitor array plate region; the first resistor array layout area is connected with the second resistor array layout area; the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region; the layout structure of the two-stage fully differential operational amplifier which is laid out according to the functions and has clear signal flow direction is obtained, and the layout structure can reduce the circuit performance loss caused by parasitic parameters, thereby improving the post-simulation passing rate. The scheme of the embodiment of the invention can be used for carrying out layout according to the circuit function to obtain the layout structure of the two-stage fully differential operational amplifier, the signal flow of the layout structure is clear, the circuit performance loss caused by parasitic parameters is small, and the post-simulation passing rate is high.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
FIG. 1 is a schematic diagram of a specific circuit configuration of a two-stage fully differential operational amplifier divided according to a circuit principle according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a layout structure of a two-stage fully differential operational amplifier according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a layout structure of a two-stage fully differential operational amplifier according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a cascaded two-stage fully differential operational amplifier according to one embodiment of the present invention;
fig. 5 is a flow chart of a layout design method of a two-stage fully differential operational amplifier according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It should be noted that although a logical order is illustrated in the flowchart in the description of the present invention, in some cases, the steps illustrated or described may be performed in an order different from that in the flowchart. In the description of the present invention, a plurality means one or more, and a plurality means two or more. The description of "first" and "second" is used for the purpose of distinguishing between technical features only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to be limiting of the invention.
First, several terms involved in the present invention are explained:
two-stage fully differential operational amplifier: two differential input ends and two differential output ends, which is characterized in that a common mode feedback circuit is needed to stabilize and determine the output point; the circuit scale and the power consumption are twice that of a single-ended amplifier, the output signal swing is 2 times that of a single-ended structure, and the noise of a power supply and the ground is restrained at an output end.
PMOS (Positive channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor field effect transistor) comprising drain D, source S and gate G; when the drain electrode D is connected with the negative electrode, the source electrode S is connected with the positive electrode, and the grid electrode G is negative voltage, the conducting channel is established, and the P-channel MOS tube starts to work.
An NMOS (Negative channel Metal Oxide Semiconductor, N-channel metal oxide semiconductor) comprising a drain D, a source S, and a gate G; when the drain electrode D is connected with the positive electrode, the source electrode S is connected with the negative electrode, and the grid electrode G is positive voltage, a conducting channel is established, and the N-channel MOS tube starts to work.
Dummy tube: may also be referred to as virtual elements. By adding patterns which are not related to LVS (circuit matching), such as Dummy tubes, the deviation in the middle process can be reduced and the matching degree can be improved.
STI effect: STI is an abbreviation for Shallow Trench Isolation (shallow trench isolation), and the STI effect is called shallow trench isolation effect. For the deep submicron CMOS process technology using STI as isolation, the STI trench is filled with isolation medium oxide, and the STI can generate compressive stress to squeeze an active region adjacent to MOS due to different thermal expansion coefficients of a silicon substrate and the isolation medium oxide, so that the electrical parameters of the device are changed, and the effect is the STI effect.
CMOS analog integrated circuit layout design is a process of performing accurate physical description of a finished created circuit netlist, which must meet the common constraints of design flow, manufacturing process and circuit performance index at the same time. CMOS analog integrated circuits are more sensitive to parasitic parameters than digital integrated circuits, and therefore, in the case where the front simulation meets the design requirements, the back simulation is not necessarily able to meet the design requirements. In the deep submicron stage, the effect of parasitics on the circuit is more pronounced. In the chip design process, the application scene of the amplifier is very many, and the operational amplifier layout directly influences the overall performance of the circuit. Two-stage fully differential operational amplifiers are often used in circuit layouts that have high demands on circuit performance. In the related art, unreasonable planning exists in the layout structure of the two-stage fully differential operational amplifier layout, specifically, the layout structure fed back by the common mode is not well planned, so that the signal flow direction is unclear, parasitic parameters generated by the layout can greatly reduce the performance of a circuit, and the post-simulation passing rate of the layout is low.
Based on the above, the invention provides a layout design method and a layout structure of a two-stage full-differential operational amplifier, when designing the layout of the two-stage full-differential operational amplifier, a first version region, a second version region, a third version region and a fourth version region are sequentially arranged in parallel from left to right; then, setting the first layout area includes: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom; next, setting the second layout region includes: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom; then, setting the third layout area includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom; then, setting the fourth layout region includes: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom; finally, the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region; respectively connecting the common mode feedback tube plate region with the first common mode capacitor array plate region; a second common mode capacitor array plate region; the first resistor array layout area is connected with the second resistor array layout area; the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region; the layout structure of the two-stage fully differential operational amplifier which is laid out according to the functions and has clear signal flow direction is obtained, and the layout structure can reduce the circuit performance loss caused by parasitic parameters, thereby improving the post-simulation passing rate. Therefore, the scheme of the embodiment of the invention can be used for carrying out layout according to the circuit function to obtain the layout structure of the two-stage fully differential operational amplifier, the signal flow of the layout structure is clear, the circuit performance loss caused by parasitic parameters is smaller, and the post-simulation passing rate is higher.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
As shown in fig. 1, the two-stage fully differential operational amplifier circuit can be divided into: a bias circuit, a common mode feedback circuit, a first stage amplifier and a second stage amplifier. Further, the two-stage fully differential operational amplifier circuit may be divided into: the circuit comprises a current mirror unit 201, a differential pair tube unit 202, a common mode feedback tube unit 203, a first stage load tube unit 204, a common mode capacitance resistance unit 205, a first compensation capacitance array unit 206, a second compensation capacitance array unit 207 and a bias circuit unit 208.
Wherein the current mirror unit 201 includes: a first switching tube PM1, a second switching tube PM2, a third switching tube PM3, a fourth switching tube PM4 and a fifth switching tube PM5.
A differential pair tube unit 202 comprising: a first differential pair pipe PM6 and a second differential pair pipe unit PM7.
A common mode feedback tube unit 203, comprising: a first common mode feedback pipe PM8, a second common mode feedback pipe PM9, and a third common mode feedback pipe PM10.
A first stage load pipe unit 204 comprising: a first load pipe NM1 and a second load pipe NM2.
A common mode capacitance-resistance unit 205, comprising: the first resistor R1, the first capacitor C1, the second resistor R2 and the second capacitor C2.
The first compensation capacitor array unit 206 includes: a first compensation capacitor C3.
The second compensation capacitor array unit 207 includes: and a second compensation capacitor C4.
The bias circuit unit 208 includes: a sixth switching tube NM3, a seventh switching tube NM4 and an Isink current source.
The current mirror unit 201 is electrically connected with the differential pair tube unit 202, the common mode feedback tube unit 203, the bias circuit unit 208, the first compensation capacitor array unit 206 and the second compensation capacitor array unit 207 respectively; the first stage load tube unit 204 is electrically connected with the differential pair tube unit 202, the common mode feedback tube unit 203, the first compensation capacitor array unit 206 and the second compensation capacitor array unit 207 respectively; the common mode feedback tube unit 203 is electrically connected to the common mode capacitance resistance unit 205.
It should be noted that, the specific connection relationship between each component in the two-stage fully differential operational amplifier circuit is shown in fig. 1, and the present invention is not described herein again.
The layout structure of the designed two-stage fully differential operational amplifier is further described based on the specific circuit structure of the two-stage fully differential operational amplifier shown in fig. 1.
As shown in fig. 2, fig. 2 is a schematic diagram of a layout structure of a two-stage fully differential operational amplifier according to an embodiment of the present invention. A layout structure 100 of a two-stage fully differential operational amplifier, comprising: a first edition of region A, a second edition of region B, a third edition of region C and a fourth edition of region D which are arranged in parallel in sequence from left to right.
Wherein the first version of region A comprises: a first common mode capacitance array plate region 105, a first resistance array plate region 107, and a first compensation capacitance array plate region 109 are arranged in this order from top to bottom.
The second version region B includes: a current mirror layout area 101 and a bias circuit board layout area 111 are arranged in order from top to bottom.
The third version region C includes: differential pair piping section 102, common mode feedback piping section 103 and first stage load piping section 104 are arranged in this order from top to bottom.
The fourth edition region D includes: a second common mode capacitance array plate region 106, a second resistance array plate region 108, and a second compensation capacitance array plate region 110, which are arranged in this order from top to bottom.
The current mirror plate region 101 is respectively connected with the bias circuit plate region, the differential pair plate region 102, the common mode feedback tube plate region 103 and the first-stage load tube plate region 104; the common mode feedback tube plate region 103 is respectively connected with the first common mode capacitor array plate region, the second common mode capacitor array plate region 106, the first resistor array plate region 107 and the second resistor array plate region; the first stage load layout area 104 is connected to the first compensation capacitor array layout area and the second compensation capacitor array layout area, respectively.
It will be understood that, when the schematic circuit diagram shown in fig. 1 is designed as the layout structure shown in fig. 2, the current mirror unit 201 corresponds to the current mirror plate region 101, the differential pair transistor unit 202 corresponds to the differential pair plate region 102, the common mode feedback transistor unit 203 corresponds to the common mode feedback transistor layout region 103, the first stage load transistor unit 204 corresponds to the first stage load transistor plate region 104, the first resistor R1, the first capacitor C1, the second resistor R2 and the second capacitor C2 in the common mode capacitor resistor unit 205 respectively correspond to the first resistor array plate region 107, the second resistor array plate region 108, the first compensation capacitor array plate region 109 and the second compensation capacitor array plate region 110, the first compensation capacitor array unit 206 corresponds to the first common mode capacitor array plate region 105, the second compensation capacitor array unit 207 corresponds to the second common mode capacitor array plate region 106, and the bias circuit unit 208 corresponds to the bias circuit plate region 111.
It will be appreciated that a two-stage fully differential operational amplifier layout may be implemented by providing, laying out, a current mirror layout 101, a differential pair layout 102, a common mode feedback layout 103, a first stage load layout 104, a first common mode capacitance array layout 105, a second common mode capacitance array layout 106, a first resistive array layout 107, a second resistive array layout 108, a first compensating capacitance array layout 109, a second compensating capacitance array layout 110, and a bias circuit layout 111. The current mirror layout area 101, the differential pair transistor layout area 102 and the first-stage load transistor layout area 104 form an amplifier first-stage layout, the current mirror layout area 101, the first resistor array layout area 107, the second resistor array layout area 108, the first compensation capacitor array layout area 109 and the second compensation capacitor array layout area 110 form an amplifier second-stage layout, and the common-mode feedback transistor layout area 103, the first common-mode capacitor array layout area 105, the second common-mode capacitor array layout area 106, the first resistor array layout area 107 and the second resistor array layout area 108 form a common-mode feedback circuit layout, and the bias circuit layout area 111 forms a bias circuit layout.
According to the layout structure of the two-stage fully differential operational amplifier provided by the embodiment of the invention, the functional design layout is reasonable, the signal flow direction is clear, the circuit performance loss caused by parasitic parameters is small, and the post-simulation passing rate is high.
It is emphasized that, as a whole, the current mirror layout region 101 is next to the differential pair layout region 102 and the common mode feedback pair layout region 103, providing current sources for the differential pair layout region 102 and the common mode feedback pair layout region 103, and being beneficial to shortening the current path.
In the circuit configuration diagram of the two-stage fully differential operational amplifier shown in fig. 1, the G end and the D end of the first switching tube PM1 of the current mirror unit 201 are connected to the bias circuit unit 208, and the first switching tube PM1 is arranged at the center position during the process of designing the current mirror region 101, and the remaining second switching tube PM2, third switching tube PM3, fourth switching tube PM4 and fifth switching tube PM5 are disposed at two sides of the first switching tube PM1, so as to improve the matching degree of the current mirror region 101.
In some embodiments, the differential pair piping section 102, the common mode feedback piping section 103, and the first stage load piping section 104 all have a common centroid match.
Specifically, the differential pair template region 102, the common mode feedback template region 103 and the first stage load template region are subjected to common centroid matching respectively, so that the matching performance is improved. Meanwhile, the widths of the differential pair stencil region 102, the common mode feedback stencil region 103 and the first stage load stencil region 104 are the same and symmetrical in the vertical direction, so that the paths of the von1 signal and the vop1 signal shown in fig. 2, which pass through the differential pair stencil region 102, the common mode feedback stencil region 103 and the first stage load stencil region 104, are shortest and almost the same.
Specifically, when designing the layout of the two-stage fully differential operational amplifier, the matching requirement for the differential pair template region 102 is high, so that the common centroid matching is required. In addition, when designing the differential pair template region 102, a dummy tube with a proper distance is added to the matching tube to reduce the parasitic influence caused by the STI effect, so as to improve the matching degree of the transistor; the periphery of the transistor is wrapped by a P ring and an N ring, so that the noise interference of the outside is further reduced.
Specifically, when designing the layout of the two-stage fully differential operational amplifier, the layout of the first stage load tube is required to be subjected to common centroid matching, and meanwhile, the interdigital transistors are matched, for example, a transistor with the width of 4um can be divided into 4 interdigital transistors with the width of 1um, so that the mismatch of the transistors and the wide polysilicon gate resistance are reduced, and the power consumption is reduced.
In some embodiments, the bias circuit board regions 111 are symmetrically matched. In the circuit structure diagram of the two-stage fully differential operational amplifier shown in fig. 1, the G end and the D end of the sixth switching tube NM3 are connected, and in the process of designing the bias circuit board region 111, the sixth switching tube NM3 is placed at the center position, and the rest switching tubes are placed at two sides, so that the bias circuit board region 111 is matched in a symmetrical structure; in addition, dummy tubes are added around the mating tubes to increase the degree of mating.
In some embodiments, the first common mode capacitance array plate region 105 and the second common mode capacitance array plate region 106 are the same in shape and size and are symmetrically distributed about the symmetry axis; the first resistor array plate region 107 and the second resistor array plate region 108 have the same shape and size and are distributed symmetrically about the symmetry axis; the first compensation capacitor array plate area 109 and the second compensation capacitor array plate area 110 have the same shape and size and are distributed symmetrically about the symmetry axis.
It will be appreciated that, as a whole, the first version of region a and the fourth version of region D are symmetrically disposed on both sides of the overall layout, specifically, the first common mode capacitor array version of region 105 and the second common mode capacitor array version of region 106, the first resistor array version of region 107 and the second resistor array version of region 108, the first compensation capacitor array version of region 109 and the second compensation capacitor array version of region 110 are symmetrically disposed on both sides of the overall layout, respectively, such that the effective paths of the output signals von and vop shown in fig. 2 are the shortest and almost the same, thereby satisfying the design requirement of full differential. In addition, the capacitor adopts the same size, and the resistor adopts the same size, thereby being beneficial to improving the matching performance.
In some embodiments, as shown in fig. 3, the layout structure of the two-stage fully differential operational amplifier further includes: the differential signal input port and the differential signal output port are symmetrically arranged, the differential signal input port is arranged at the center position of the uppermost edge of the overall layout, and the differential signal output port is arranged at the center position of the lowermost edge of the overall layout.
Specifically, as shown in fig. 4, in the application scenario of the cascade connection of two-stage fully differential operational amplifiers, the differential signal output port of the first-stage fully differential operational amplifier OP1 is connected to the differential signal input port of the second-stage fully differential operational amplifier OP2, and a capacitor is provided between the first-stage fully differential operational amplifier OP1 and the second-stage fully differential operational amplifier OP 2.
The layout structure of the fully differential operational amplifier provided by the embodiment of the invention is applied to a multi-cascade scene through the symmetrically arranged differential signal input port and the differential signal output port. Specifically, in the cascaded application scene, the directions of the differential signal output port of the upper-stage two-stage fully-differential operational amplifier layout and the differential signal input port of the lower-stage two-stage fully-differential operational amplifier layout are close, and the parasitic resistance and capacitance caused by wiring have small influence on the operational amplifier.
In a second aspect, referring to fig. 5, fig. 5 is a schematic diagram illustrating a layout design method of a two-stage fully differential operational amplifier according to an embodiment of the present invention, including but not limited to steps S110 to S160.
Step S110: and arranging a first edition of region, a second edition of region, a third edition of region and a fourth edition of region which are sequentially arranged in parallel from left to right.
Step S120: setting the first layout area comprises the following steps: the first common mode capacitor array plate area, the first resistor array plate area and the first compensation capacitor array plate area are sequentially arranged from top to bottom.
Step S130: setting the second layout area comprises the following steps: a current mirror plate region and a bias circuit plate region which are arranged in sequence from top to bottom.
Step S140: setting the third layout area comprises the following steps: the differential pair template region, the common mode feedback template region and the first stage load template region are sequentially arranged from top to bottom.
Step S150: setting the fourth layout area comprises the following steps: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom.
Step S160: the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region; respectively connecting the common mode feedback tube plate region with the first common mode capacitor array plate region; a second common mode capacitor array plate region; the first resistor array layout area is connected with the second resistor array layout area; and the first-stage load tube plate area is respectively connected with the first compensation capacitor array plate area and the second compensation capacitor array plate area.
When designing the layout of the two-stage fully differential operational amplifier by the layout design method of the two-stage fully differential operational amplifier of the embodiment step S110 to step S160, firstly, a first version region, a second version region, a third version region and a fourth version region which are sequentially arranged in parallel from left to right are arranged; then, setting the first layout area includes: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom; next, setting the second layout region includes: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom; then, setting the third layout area includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom; then, setting the fourth layout region includes: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom; finally, the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region; respectively connecting the common mode feedback tube plate region with the first common mode capacitor array plate region; a second common mode capacitor array plate region; the first resistor array layout area is connected with the second resistor array layout area; the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region; the layout structure of the two-stage fully differential operational amplifier which is laid out according to the functions and has clear signal flow direction is obtained, and the layout structure can reduce the circuit performance loss caused by parasitic parameters, thereby improving the post-simulation passing rate. Therefore, the scheme of the embodiment of the invention can be used for carrying out layout according to the circuit function to obtain the layout structure of the two-stage fully differential operational amplifier, the signal flow of the layout structure is clear, the circuit performance loss caused by parasitic parameters is smaller, and the post-simulation passing rate is higher.
In some embodiments, the differential pair stencil region, the common mode feedback stencil region and the first stage load stencil region are subjected to common centroid matching layout respectively, so that the differential pair stencil region, the common mode feedback stencil region and the first stage load stencil region are subjected to common centroid matching.
It can be understood that the common centroid matching is respectively carried out on the differential pair template region, the common mode feedback template region and the first-stage load tube region, so that the matching performance is improved. In addition, the widths of the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region are made to be the same, and the widths are symmetrical in the vertical direction, so that the paths of the von1 signal and the vop1 signal shown in fig. 2, which pass through the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region, are ensured to be shortest and almost the same.
Specifically, when designing the differential pair transistor layout area, the common centroid matching is adopted to meet the higher matching requirement of the differential pair transistor layout area. In addition, when designing the differential pair transistor layout area, dummy tubes with proper distances are added in the matching tubes to reduce parasitic influence caused by the STI effect so as to improve the matching degree of the transistors; the periphery of the transistor is wrapped by a P ring and an N ring, so that the noise interference of the outside is further reduced.
Specifically, when designing the first stage load tube layout, common centroid matching is adopted, and simultaneously, the interdigital transistors are matched, for example, a transistor with the width of 4um can be divided into 4 interdigital transistors with the width of 1um, so that the mismatch of the transistors and the resistance of a wide polysilicon gate are reduced, and the power consumption is reduced.
In some embodiments, the bias circuit layout areas are symmetrically matched, and the bias circuit layout areas are symmetrically matched.
Specifically, when designing the bias circuit layout area, the sixth switching tube NM3 in the bias circuit unit 208 is placed at the center position, and the rest switching tubes are placed at two sides so as to realize symmetrical structure matching; and dummy tubes are added around the matched tubes to improve the matching degree.
In some embodiments, the first common-mode capacitor array layout area and the second common-mode capacitor array layout area are arranged to have the same shape and size and are distributed symmetrically left and right about a symmetry axis; setting the first resistance array plate region and the second resistance array plate region to have the same shape and size and to be distributed symmetrically about a symmetry axis; the first compensation capacitor array plate area and the second compensation capacitor array plate area are arranged to be the same in shape and size and distributed symmetrically about a symmetry axis.
Specifically, a first version region a and a fourth version region D are symmetrically arranged on two sides of the overall layout, and further, the first common-mode capacitor array version region, the second common-mode capacitor array version region, the first resistor array version region, the second resistor array version region, the first compensation capacitor array version region and the second compensation capacitor array version region are symmetrically arranged on two sides of the overall layout respectively, so that effective paths of output signals von and vop shown in fig. 2 are shortest and almost the same, and the design requirement of full difference is met. In addition, the capacitor adopts the same size, and the resistor adopts the same size, thereby being beneficial to improving the matching performance.
In some embodiments, the differential signal input port and the differential signal output port are symmetrically arranged, the differential signal input port is arranged at the center position of the uppermost edge of the overall layout, and the differential signal output port is arranged at the center position of the lowermost edge of the overall layout.
Specifically, a differential signal input port is arranged at the center of the uppermost edge of the overall layout, and correspondingly, a differential signal output port is arranged at the center of the lowermost edge of the overall layout. When the method is applied to a cascading application scene, the directions of the differential signal output port of the upper-stage two-stage fully-differential operational amplifier layout and the differential signal input port of the lower-stage two-stage fully-differential operational amplifier layout are close, and the influence of parasitic resistance and capacitance caused by wiring on the operational amplifier is small.
In summary, the embodiment of the invention has at least the following beneficial effects:
firstly, a layout structure of the two-stage fully differential operational amplifier is obtained by layout according to circuit functions, the signal flow direction of the layout structure is clear, the circuit performance loss caused by parasitic parameters is small, and the post-simulation passing rate is high.
Secondly, the differential signal input port and the differential signal output port are respectively arranged at the center positions of the uppermost edge and the lowermost edge of the overall layout, so that the layout structure provided by the embodiment of the invention can be suitable for an application scene of cascade connection of a plurality of two-stage fully differential operational amplifier layouts, and has strong universality.
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention.
Claims (8)
1. A layout structure of a two-stage fully differential operational amplifier, comprising:
the first edition region, the second edition region, the third edition region and the fourth edition region are sequentially arranged in parallel from left to right;
the first layout area comprises: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom;
the second layout area comprises: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom;
the third layout area includes: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom;
the fourth layout area comprises: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom;
the current mirror layout area is respectively connected with the bias circuit board area, the differential pair-transistor board area, the common mode feedback transistor board area and the first-stage load transistor layout area;
the common mode feedback pipe plate region is respectively connected with the first common mode capacitance array plate region, the second common mode capacitance array plate region, the first resistance array plate region and the second resistance array plate region;
the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region;
the differential pair template region, the common mode feedback template region and the first-stage load template region are all in common centroid matching; the widths of the differential pair stencil area, the common mode feedback stencil area and the first stage load stencil area are the same and are symmetrical in the vertical direction;
in the differential pair stencil region, dummy tubes are arranged around the matched tubes; and the periphery of the transistor adopts a mode of wrapping N rings by a P ring;
in the first stage load tube layout, the interdigital transistors are matched to realize common centroid matching.
2. The layout structure according to claim 1, wherein the bias circuit board areas are symmetrically matched.
3. The layout structure according to claim 1, wherein the first common-mode capacitor array layout area and the second common-mode capacitor array layout area have the same shape and size and are distributed symmetrically about a symmetry axis; the first resistor array plate region and the second resistor array plate region have the same shape and size and are distributed symmetrically about a symmetry axis; the first compensation capacitor array plate area and the second compensation capacitor array plate area have the same shape and size and are distributed symmetrically about a symmetry axis.
4. The layout structure according to claim 1, further comprising: the differential signal input port and the differential signal output port are symmetrically arranged, the differential signal input port is arranged at the center position of the uppermost edge of the overall layout, and the differential signal output port is arranged at the center position of the lowermost edge of the overall layout.
5. A layout design method of a two-stage fully differential operational amplifier is characterized by comprising the following steps:
setting a first edition of region, a second edition of region, a third edition of region and a fourth edition of region which are sequentially arranged in parallel from left to right;
setting the first layout area comprises the following steps: the first common mode capacitor array plate region, the first resistor array plate region and the first compensation capacitor array plate region are sequentially arranged from top to bottom;
setting the second layout area comprises the following steps: a current mirror plate region and a bias circuit plate region which are sequentially arranged from top to bottom;
setting the third layout area comprises the following steps: the differential pair template region, the common mode feedback template region and the first-stage load template region are sequentially arranged from top to bottom;
setting the fourth layout area comprises the following steps: the second common mode capacitor array plate area, the second resistor array plate area and the second compensation capacitor array plate area are sequentially arranged from top to bottom;
the current mirror plate region is respectively connected with the bias circuit plate region, the differential pair plate region, the common mode feedback tube plate region and the first stage load tube plate region;
the common mode feedback tube plate region and the first common mode capacitor array plate region are respectively carried out; the second common mode capacitor array version region; the first resistor array plate area is connected with the second resistor array plate area;
the first-stage load tube plate region is respectively connected with the first compensation capacitor array plate region and the second compensation capacitor array plate region;
wherein the method further comprises: carrying out common centroid matching layout on the differential pair stencil area, the common mode feedback stencil area and the first-stage load stencil area respectively to obtain common centroid matching of the differential pair stencil area, the common mode feedback stencil area and the first-stage load stencil area; the widths of the differential pair stencil area, the common mode feedback stencil area and the first stage load stencil area are the same and are symmetrical in the vertical direction;
in the differential pair stencil region, dummy tubes are arranged around the matched tubes; and the periphery of the transistor adopts a mode of wrapping N rings by a P ring;
in the first stage load tube layout, the interdigital transistors are matched to realize common centroid matching.
6. The layout design method according to claim 5, wherein the offset circuit board areas are symmetrically matched, so that the offset circuit board areas are symmetrically matched.
7. The layout design method according to claim 5, wherein the first common-mode capacitor array layout area and the second common-mode capacitor array layout area are arranged to be the same in shape and size and distributed symmetrically left and right about a symmetry axis; setting the first resistance array plate region and the second resistance array plate region to have the same shape and size and to be distributed symmetrically about a symmetry axis; the first compensation capacitor array plate area and the second compensation capacitor array plate area are arranged to be the same in shape and size and distributed symmetrically about a symmetry axis.
8. The layout design method according to claim 5, further comprising: the method comprises the steps of symmetrically arranging a differential signal input port and a differential signal output port, arranging the differential signal input port at the center position of the uppermost edge of the overall layout, and arranging the differential signal output port at the center position of the lowermost edge of the overall layout.
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