CN111244088B - Layout structure of operational amplifier in pipelined analog-to-digital converter - Google Patents
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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Abstract
The invention discloses a layout structure of an operational amplifier in a flow analog-to-digital converter, which comprises two parts of module units which are in mirror symmetry, wherein each part of module unit comprises a main operational amplifier, an auxiliary operational amplifier and a bias module, finger values are adopted for parallel connection of all mos tubes, source and drain ends of the mos tubes above and below the main operational amplifier are on the same line, the parallel connection number of all mos tubes in the operational amplifier is even, and the W values of the auxiliary operational amplifier and the bias module are consistent with the W values of the mos tubes in the main operational amplifier. Dummy tubes are added in the main operational amplifier, the auxiliary operational amplifier and the bias module to fill up the blank in the layout so as to ensure that the current is not lost. The layout structure can reduce parasitic capacitance caused by signal lines and peripheral wiring, and process mismatch caused by loose layout is reduced by adopting concentrated layout, so that the process environment of each mos tube is consistent.
Description
Technical Field
The invention belongs to the field of chip design, and particularly relates to a layout structure of an operational amplifier in a pipelined analog-to-digital converter.
Background
An analog-to-digital converter (ADC) is a circuit that converts an analog signal to a digital signal. In the fields of testing measuring instruments, high-speed data acquisition, mobile communication, optical communication, broadband radar and the like, an analog-to-digital converter plays an important role, an operational amplifier is used as one of the most important basic circuit units in an analog integrated circuit, and the performance of the operational amplifier becomes an important influence factor of the performance of the analog integrated circuit. With the rapid development of the current process technology, transistors are smaller and smaller, the speed is faster and faster, and a series of problems are also accompanied while low cost, high performance and multifunctional application are realized.
Disclosure of Invention
The invention aims to solve the problem of mismatch caused by signal node parasitic influence in a layout and small process layout in the prior art small process procedure, and provides a layout structure of an operational amplifier in a flow analog-to-digital converter, which can reduce parasitic capacitance caused by signal lines and peripheral wiring, adopts concentrated layout to reduce process mismatch caused by loose layout, and ensures that the process environments of each mos tube are consistent.
In order to achieve the purpose, the invention has the following technical scheme:
a layout structure of an operational amplifier in a water-flowing type analog-digital converter comprises two mirror-symmetrical module units, wherein each module unit comprises a main operational amplifier, an auxiliary operational amplifier and a bias module; finger values are adopted for parallel connection of all mos tubes in the operational amplifier, a single row is adopted for mos tube layout of the main operational amplifier, source and drain ends of upper mos tubes and lower mos tubes of the main operational amplifier are on the same line, the number of parallel connection of all mos tubes in the operational amplifier is even, and W values of the auxiliary operational amplifier and the bias module are consistent with those of the mos tubes in the main operational amplifier; dummy tubes are added in the main operational amplifier, the auxiliary operational amplifier and the bias module to fill the blank in the layout so as to ensure that the current is not lost; thicker metal in the top layer and the second top layer of the operational amplifier is used for power supply ground, clocks, buses and important signal interconnection lines, the overcurrent capacity of the top layer of the operational amplifier is enhanced, the voltage drop loss is reduced, and the distance between the top layer and other layers is increased.
Preferably, in an embodiment of the layout structure of the operational amplifier in the pipelined analog-to-digital converter, the two parts of module unit routing lines are both placed inside the module unit, and the differential signals of the two parts are completely identical.
Preferably, in an embodiment of the layout structure of the operational amplifier in the pipelined analog-to-digital converter of the present invention, there are 5 mos transistors of the main operational amplifier, and the W, L value is adjusted to make the 5 mos transistors of the main operational amplifier have the same width.
Preferably, in an embodiment of the layout structure of the operational amplifier in the pipelined analog-to-digital converter of the present invention, the auxiliary operational amplifier, the bias module and the mos transistor source and drain of the main operational amplifier are shared, and the power supply of the current source is shared with the ground.
Preferably, in the embodiment of the layout structure of the operational amplifier in the pipeline analog-to-digital converter, dummy tubes are added based on a 40nm process layout, 5 rows of dummy tubes are placed in mos tubes with the minimum process size, so that the threshold voltage of the mos tubes at the edges tends to be stable, and the adaptability is widened when the channel length of the mos tubes is larger than the requirement of the minimum process size.
Preferably, in an embodiment of the layout structure of the operational amplifier in the pipeline analog-to-digital converter of the present invention, when the source ends of the main mos transistor and the upper and lower mos transistors of the operational amplifier are not connected to the power ground, the dummy transistor and the main mos transistor are shared, and the source end of the dummy transistor closest to the main mos transistor is connected to the source end of the main mos transistor, the gate end, the drain end and the substrate are short-circuited to the power ground, so as to keep the environment of the main mos transistor consistent, and share one end of the working mos transistor and the closed dummy transistor.
Preferably, in an embodiment of the layout structure of the operational amplifier in the pipeline analog-to-digital converter of the present invention, when the source end of the mos transistor is connected to the power ground, but the odd transistor cannot share the source and drain ends with the mos transistors on both sides, the dummy transistor and the mos transistor are shared, and the source end of the dummy transistor closest to the mos transistor is connected to the source end of the mos transistor, the gate end, the drain end and the substrate are shorted to the power ground, so as to keep the environment of the mos transistor consistent, and share one end with the working mos transistor and the closed dummy transistor.
Compared with the prior art, the invention has the following beneficial effects: in order to ensure the complete matching of differential signals in the operational amplifier, two parts of module units which are in mirror symmetry are adopted, and a main operational amplifier, an auxiliary operational amplifier and a bias module of each part of module units are preferably made, so that the complete consistency of two sides of the differential signals can be ensured, the repeated work can be avoided by later-stage adjustment, and compared with the traditional common centroid matching layout, the layout has simpler connecting lines and smaller parasitic. Finger values are adopted for parallel connection of all mos tubes in the operational amplifier, double source-drain parallel lines caused by the use of m values can be reduced, signal channels are shortened, and the effect of reducing parasitic capacitance is achieved finally. Finger values are adopted for parallel connection of all mos tubes in the operational amplifier module, and the layout area of the module can be reduced, so that the effect of reducing the cost is achieved. The mos tubes of the main operational amplifier are all arranged in a single row, the whole width is made to be equal to the width as much as possible, and the signal flow direction can be more uniform. The number of all mos tubes in the operational amplifier in parallel connection is even, the W values of the mos tubes in the auxiliary operational amplifier and the bias module are consistent with the W values of the mos tubes in the main operational amplifier, the source and drain terminals of the mos tubes in the main operational amplifier, the auxiliary operational amplifier and the bias module can be shared, especially the power supply and the ground in the current source are shared, and the current is guaranteed not to be lost. In order to ensure the consistency of each MOS tube and protect devices from over etching, enough dummy tubes are added in a main operational amplifier, an auxiliary operational amplifier and a bias module, if the auxiliary operational amplifier and the bias module can not be made to be equal in width according to the main operational amplifier, the layout is still arranged according to the current sequence, the situation that the width of some MOS tubes is larger or smaller can exist, and when blank gaps appear in the layout, the dummy tubes are filled in the blank positions according to the actual situation so as to ensure that the current is not lost. In the top layer and the second top layer of the operational amplifier, thicker metal is used for power supply ground, clocks, buses and important signal interconnection lines, so that the overcurrent capacity of the top layer of the operational amplifier can be enhanced, the voltage drop loss is reduced, and the distance between the top layer and other layers is increased. Compared with other operational amplifiers, the layout structure of the invention has simple layout and compact modules, can reduce mismatch effect caused by small processes and parasitic capacitance caused by layout and wiring as much as possible, is easier to be adopted in a high-speed high-precision ADC chip, can reduce the area of the chip while ensuring the performance so as to reduce the cost of the chip, and has beautiful and neat layout as a whole.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the overall circuit design of the present invention;
FIG. 2 is a block diagram of a layout design main structure of the present invention;
FIG. 3 is a schematic diagram of the layout of power supply, ground, signal, etc. according to the present invention, wherein the power supply and ground layout is completed by M10 in the horizontal direction, and the signal line layout is completed by M9 in the vertical direction;
FIG. 4 is a schematic diagram of an actual effect of the layout in the cadence;
FIG. 5 is a schematic diagram of the parallel connection of all mos transistors in a prior art operational amplifier using the value of m;
FIG. 6 is a schematic diagram of the parallel use of finger values for all mos transistors in an operational amplifier of the present invention;
FIG. 7 is a schematic diagram of manually adjusting the spacing between mos tube source drain holes and polycrystals so that the upper and lower mos tube source drains are on the same line;
FIG. 8 is a schematic view of the placement of the dummy tubes of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention.
Based on the embodiments of the present invention, those skilled in the art can make several simple modifications and decorations without creative efforts, and all other embodiments obtained are also within the protection scope of the present invention.
Reference in the present specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example may be included in at least one embodiment of the present invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described in the present invention can be combined with other embodiments.
In the embodiment of the layout structure, in order to ensure the matching of the differential signals of the operational amplifier module, the module is generally laid out into an AA type, half of Acell (a mos tube and a signal line are symmetrically laid out and put into the Acell) is firstly made to be mirrored, and the routing is placed inside, so that the complete consistency of two sides of the differential module can be ensured, as shown in figure 2, the repeated work can be avoided by later-stage adjustment, and compared with the traditional common centroid matching layout, the layout has simpler connection line and smaller parasitic.
The Acell module comprises a main operational amplifier, an auxiliary operational amplifier and a bias module, wherein the auxiliary operational amplifier is used for improving the gain of the main operational amplifier, and the bias module is used for providing bias current for the main operational amplifier and the auxiliary operational amplifier.
Referring to fig. 1, a main operational amplifier: five MOS tubes on the path are arranged in a layout according to the plan in the schematic diagram, and each MOS tube is arranged in a single row to form five rows (MOS tubes in the layout are consistent with the layout sequence of the upper part and the lower part in the schematic diagram), so that the smoothness of the current path is ensured, and the signal routing in the layout is ensured to be as short as possible. The main operational amplifier has large current, and a single layer of bottom metal is difficult to meet the current requirement under the current layout area according to the metal overcurrent capacity requirement, so that metal level superposition is required.
The layout of the auxiliary operational amplifier is consistent with that of the main operational amplifier, and the layout is carried out according to the plan in a schematic diagram, the mos tube adopts a W value which is consistent with that of the main operational amplifier as far as possible so as to ensure the sharing of a power supply, a ground and a signal of the auxiliary operational amplifier and the main operational amplifier, and the two mos tubes in the middle are arranged according to the current trend sequence to avoid current loss.
A biasing module: the current source mos tube is close to the auxiliary operational amplifier to ensure the sharing of a power supply, a ground and a signal of the current source mos tube in the bias circuit and the auxiliary operational amplifier circuit, and the middle mos tubes are arranged according to the current trend sequence to avoid current loss.
Compared with the graph shown in the figure 5 and the graph shown in the figure 6, the parallel connection of mos tubes in the layout structure of the invention adopts finger values, compared with the existing layout structure, double source-drain parallel lines caused by using m values can be reduced, meanwhile, the signal channel is shortened, the effect of reducing parasitic capacitance is finally achieved, and the layout area of a module can also be reduced, thereby achieving the effect of reducing cost.
When the 5 mos tubes of the main operational amplifier signal flow are arranged in a single row, the overall width of the 5 mos tubes is approximately made to be equal (the W, L value of the five tubes is adjusted in a matching mode), and the signal flow direction can be more uniform. Because the main operational amplifier needs to be of the same width, the L value of a single mos tube cannot meet the requirement sometimes only by adjusting, at the moment, the distance from a source drain hole of the mos tube to a polycrystal needs to be adjusted manually, the widths of an upper mos tube and a lower mos tube are matched, and the source drain of the upper mos tube and the source drain of the lower mos tube are kept on the same line, as shown in fig. 7.
The main operational amplifier of the invention is difficult to adjust the L of mos tubes to be consistent due to various factors, especially, limit values exist in some parameters of pmos and nmos tubes (for example, a single pmos tube W is required to be less than or equal to 1.5um), and the distance between a source drain end hole and polycrystal of the mos tube needs to be adjusted manually to match the integral width of the upper mos tube and the lower mos tube, so that the source drain of the upper mos tube and the source drain of the lower mos tube in the signal flow of the operational amplifier are ensured to be on the same line as much as possible, and communication with a designer is needed before the operation is carried out, and the influence caused by the operation can be accepted or not. The number of mos tubes is adjusted to be even, the W values of the mos tubes in the auxiliary operational amplifier and the main operational amplifier are consistent, and the source and the drain of the mos tubes of the main operational amplifier, the auxiliary operational amplifier and the bias module can be shared.
Enough dummy tubes are added in a main operational amplifier, an auxiliary operational amplifier and a bias module (especially if the width of the auxiliary operational amplifier and the width of the bias module are not strictly equal to that of the main operational amplifier, the width of a single mos tube is larger, the width of the single mos tube is smaller, a blank gap exists, and the blank is filled with the dummy tubes according to actual conditions so as to ensure that current is not lost).
And (3) under the 40nm process, after 5 rows of dummy tubes are placed on the mos tube with the minimum process size obtained through multiple verification, the threshold voltage of the edge mos tube basically tends to be stable, and the requirement can be properly relaxed when the channel length of the mos tube is larger than the minimum process size.
When the similar situation that the source ends of the input tube and the upper and lower mos tubes of the operational amplifier main tube part are not connected with the power ground occurs, the source end of the dummy tube closest to the main tube is connected with the source end of the main tube while the dummy tube and the main tube are shared, the grid end, the drain end and the substrate are in short circuit with the power ground, and the main tube environment is kept consistent as much as possible (as shown in the placement mode of fig. 8, the working tube and the closed dummy tube share one end). When the source end of the individual mos tube is connected with the power supply ground, and the source end and the drain end cannot be shared with the mos tubes on two sides due to the singular number, the dummy tube can be added to the singular number mos tube by adopting the same method as the main mos tube.
The top layer and the second top layer in the operational amplifier are thicker metal used for power supply ground, clocks, buses, important signal interconnecting wires and the like, and the top layer has the advantages of strong overcurrent capacity, small parasitic, longer separation from other layers and the like.
The signal line in the layout structure of the operational amplifier is extremely sensitive to the parasitic, the speed of the circuit is directly influenced, the first important consideration for reducing the parasitic capacitance of the signal line node is the layout, and the integrated circuit layout is formed by overlapping a plurality of layers, such as a poly layer, an nwell layer, a metal1 layer, a metal2 layer and the like. When wiring, metal2 may pass through metal1, and metal1 and metal2 form a parasitic capacitor. Parasitic capacitances can be generated among metals in the same layer or different layers and between the metals and the substrate, the parasitic capacitances are everywhere, if the circuit design is not sensitive to the capacitance, the parasitic capacitances can be directly ignored, but when the chip speed is high or the frequency is high, the parasitic capacitances need special attention and the whole chip can be damaged.
Meanwhile, in order to ensure the manufacturability of the chip, prevent etching failure caused by overexposure or underexposure of the chip in the manufacturing process, reduce parasitic capacitance and consider a mismatch effect caused by a small process, when mos tubes in an operational amplifier are arranged side by side, the mos tubes at the edge of an array are influenced by etching rate change, the grid of the mos tube only faces to one side adjacent grid, the grid of the mos tube in the middle faces to two side adjacent grids, the outer edge of the mos tube at the edge is etched more seriously than the corresponding edge of the mos tube in the middle, therefore, the mos tube at the edge is slightly shorter than the middle mos grid, so that transistors to achieve medium or accurate matching need to use poly dummy and dummy devices to ensure uniform etching, otherwise, current mismatch is caused. The layout of the invention is relatively simple, thus relatively small parasitic influence can be generated, particularly, the signal path is particularly sensitive to the parasitic, the speed of the circuit is directly influenced, on one hand, the signal routing is reduced as much as possible, thus reducing the parasitic capacitance caused by the signal line and the peripheral routing, on the other hand, the process mismatch caused by loose layout can be reduced by adopting the concentrated layout in the layout structure of the invention, and each mos is ensured to have almost consistent process environment.
The operational amplifier adopts a gain bootstrap sleeve type cascode operational amplifier, a circuit comprises a main operational amplifier, an auxiliary operational amplifier and a bias, wherein a layout is based on a 40nm CMOS process under a cadence environment, multiple times of simulation verification shows that under the process, an MOS tube is very sensitive, node parasitic and process environment factors can generate great influence on the functions of a module, and the simulation performance of the operational amplifier before a circuit schematic diagram can be perfectly physically realized, so the layout design of the layout is very important. The layout structure of the operational amplifier provided by the invention is adopted in the sub-circuit ADC of the 3Gsps 12Bit ADC product, the layout is simple and easy to realize, and the layout structure can be well mastered and applied by a layout designer.
While the invention has been described above with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention, and those modifications and variations are within the scope of the claims of the invention and their equivalents.
Claims (5)
1. A layout structure of an operational amplifier in a pipelined analog-to-digital converter is characterized in that: the circuit comprises two mirror-symmetrical part module units, wherein each part module unit comprises a main operational amplifier, an auxiliary operational amplifier and a bias module, the auxiliary operational amplifier is used for improving the gain of the main operational amplifier, and the bias module is used for providing bias current for the main operational amplifier and the auxiliary operational amplifier; finger values are adopted for parallel connection of all mos tubes in the operational amplifier, a single row is adopted for mos tube layout of the main operational amplifier, source and drain ends of upper mos tubes and lower mos tubes of the main operational amplifier are on the same line, the number of parallel connection of all mos tubes in the operational amplifier is even, and W values of the auxiliary operational amplifier and the bias module are consistent with those of the mos tubes in the main operational amplifier; dummy tubes are added in the main operational amplifier, the auxiliary operational amplifier and the bias module to fill the blank in the layout so as to ensure that the current is not lost; thicker metal in the top layer and the second top layer of the operational amplifier is used for power supply ground, a clock, a bus and an important signal interconnection line, so that the overcurrent capacity of the top layer of the operational amplifier is enhanced, the voltage drop loss is reduced, and the distance between the top layer and other layers is increased;
when the source ends of the main mos tube and the upper and lower mos tubes of the operational amplifier are not connected with a power ground, the source end of the dummy tube closest to the main mos tube is connected with the source end of the main mos tube while the dummy tube and the main mos tube are shared, the grid end, the drain end and the substrate are in short circuit with the power ground, the environment of the main mos tube is kept consistent, and the main mos tube and the closed dummy tube share one end;
when the source ends of a main mos tube and an upper mos tube and a lower mos tube of an operational amplifier are connected with a power ground, the number of the main mos tubes is odd, and the main mos tubes cannot share the source ends and the drain ends with the mos tubes on two sides, so that the source ends of the dummy tubes closest to the main mos tubes are connected with the source ends of the main mos tubes while the dummy tubes and the main mos tubes share the source ends and the drain ends, the gate ends, the drain ends and the substrate are in short circuit with the power ground, the environment of the main mos tubes is kept consistent, and the main mos tubes and the closed dummy tubes share one end.
2. The layout structure of the operational amplifier in the pipelined analog-to-digital converter according to claim 1, characterized in that: the two parts of module unit wires are all arranged in the module unit, and the differential signals of the two parts are completely consistent.
3. The layout structure of the operational amplifier in the pipelined analog-to-digital converter according to claim 1, characterized in that: the number of mos tubes of the main operational amplifier is 5, and the W, L value is adjusted to make the width of the 5 mos tubes of the main operational amplifier equal.
4. The layout structure of the operational amplifier in the pipelined analog-to-digital converter according to claim 1, characterized in that: the auxiliary operational amplifier, the bias module and mos tube sources and drains in the main operational amplifier are shared, and power sources in the current sources are shared with the ground.
5. The layout structure of the operational amplifier in the pipelined analog-to-digital converter according to claim 1, characterized in that: adding dummy tubes based on a 40nm process layout, placing 5 rows of dummy tubes in the mos tube with the minimum process size, enabling the threshold voltage of the edge mos tube to tend to be stable, and widening the adaptability when the channel length of the mos tube is larger than the minimum process size requirement.
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| CN117151014B (en) * | 2023-09-12 | 2024-04-12 | 南京朗立微集成电路有限公司 | Layout structure of symmetrical master-slave amplifier |
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| 应用于认知无线电接收机的流水线型ADC研究与设计;吴嘉士;《中国优秀硕士学位论文全文数据库（电子期刊）》;20180715;第50-58页、第82-88页 * |
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