CN107528557A - A kind of operational amplifier of data-driven - Google Patents

A kind of operational amplifier of data-driven Download PDF

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Publication number
CN107528557A
CN107528557A CN201710801461.2A CN201710801461A CN107528557A CN 107528557 A CN107528557 A CN 107528557A CN 201710801461 A CN201710801461 A CN 201710801461A CN 107528557 A CN107528557 A CN 107528557A
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China
Prior art keywords
nmos tube
pmos
drain electrode
grid
nmos
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CN201710801461.2A
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Chinese (zh)
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CN107528557B (en
Inventor
魏琦
周斌
李享
陈志勇
张嵘
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Tsinghua University
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Tsinghua University
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45031—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are compositions of multiple transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45074—A comparator circuit compares the common mode signal to a reference before controlling the differential amplifier or related stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45424—Indexing scheme relating to differential amplifiers the CMCL comprising a comparator circuit

Abstract

The embodiment of the invention discloses a kind of operational amplifier of data-driven, the operational amplifier includes：The N-type of interconnection and the circularly folding operational transconductance amplifier circuit of p-type Complementary input structure and the operational amplifier biasing circuit of data-driven；The operational amplifier biasing circuit of the data-driven includes input differential signal comparator；Input differential signal comparator is used to detect input differential signal, and when input differential signal be more than or equal to input differential signal comparator opening threshold value when increasing circuit bias current, when input differential signal is less than the opening threshold value of input differential signal comparator, the bias current of holding circuit will not become.And threshold value and comparator speed can be opened according to application demand dynamic adjustment amplifier current size, and comparator, control the operation window of high current.By the embodiment scheme, the speed of high performance switch condenser network is improved, and reduces power consumption, improve yield.

Description

A kind of operational amplifier of data-driven
Technical field
The present embodiments relate to the VLSI designs technology in Microelectronics and Solid State Electronics field, especially Refer to a kind of operational amplifier of data-driven.
Background technology
Operational amplifier is one of most important module of many analog circuits, is widely used in analog to digital conversion circuit, filtering In the analog signal processing circuits such as device, precision, speed and power consumption that high performance switch condenser network can reach are generally determined Etc. index.In switched-capacitor circuit, load is usually purely capacitive property, and now single stage op trsanscondutance amplifier OTA is better than more The operational amplifier of level.Therefore, traditional collapsible operation transconductance amplifier is widely applied.But traditional folding Formula OTA has the shortcomings that speed is slow, power consumption is big, and the speed of operational amplifier turns into system particularly when load capacitance is larger The about main bottleneck of switched-capacitor circuit speed.
The content of the invention
In order to solve the above-mentioned technical problem, can the embodiments of the invention provide a kind of operational amplifier of data-driven The speed of high performance switch condenser network is improved, and reduces power consumption, improve yield.
In order to reach purpose of the embodiment of the present invention, the embodiments of the invention provide a kind of operational amplifier of data-driven, The operational amplifier includes：The N-type of interconnection and the circularly folding operational transconductance amplifier circuit and number of p-type Complementary input structure According to the operational amplifier biasing circuit of driving；The operational amplifier biasing circuit of the data-driven includes input differential signal ratio Compared with device；
The input differential signal comparator, for detecting input differential signal, and when the input differential signal is more than Or equal to the input differential signal comparator opening threshold value when increasing circuit bias current, when the input differential signal Less than the input differential signal comparator opening threshold value when, the bias current of holding circuit will not become.
Alternatively, the circularly folding operational transconductance amplifier circuit of N-type and the p-type Complementary input structure includes：
N-type Complementary input structure differential pair unit and the N-type bias voltage being connected with the N-type Complementary input structure differential pair unit Transistor unit, N-type biasing tail current transistor unit and N-type cascode transistors are to unit；And
P-type Complementary input structure differential pair unit and the p-type bias voltage being connected with the p-type Complementary input structure differential pair unit Transistor unit, p-type biasing tail current transistor unit and p-type cascode transistors are to unit.
Alternatively,
The N-type Complementary input structure differential pair unit includes：First NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube；Wherein, the grid of first NMOS tube and second NMOS tube connects first in the input differential signal Differential signal VINN；The grid of 3rd NMOS tube and the 4th NMOS tube connects second in the input differential signal Differential signal VINP；
The N-type voltage bias transistor unit includes：5th NMOS tube；The grid of 5th NMOS tube and first inclined Put voltage to be connected, source ground, drain electrode and first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube Source electrode is connected.
Alternatively,
The p-type Complementary input structure differential pair unit includes：9th PMOS, the tenth PMOS, the 11st PMOS and 12 PMOSs；Wherein, the grid of the 9th PMOS and the tenth PMOS meets the first differential signal VINN； The grid of 11st PMOS and the 12nd PMOS meets the second differential signal VINP；
The p-type biasing tail current transistor unit includes：First PMOS, the second PMOS, the 3rd PMOS and Four PMOSs；Wherein, again with the described 4th after the grid of first PMOS is connected with the grid of second PMOS The drain electrode of NMOS tube is connected, the grid of the 3rd PMOS be connected with the grid of the 4th PMOS after again with described second The drain electrode of NMOS tube is connected, first PMOS, second PMOS, the 3rd PMOS and the 4th PMOS Source electrode be connected with supply voltage；
The p-type cascode transistors include to unit：5th PMOS, the 6th PMOS, the 7th PMOS and Eight PMOSs；Wherein, the grid of the 5th PMOS be connected with the grid of the 6th PMOS after with the second bias voltage It is connected；The grid of 7th PMOS be connected with the grid of the 8th PMOS after also with the second bias voltage phase Even；The source electrode of 5th PMOS is connected with the drain electrode of second PMOS, the source electrode of the 6th PMOS with it is described The drain electrode of 3rd PMOS is connected, and the drain electrode of the 5th PMOS is connected with the drain electrode of the 4th NMOS tube, and the described 6th The drain electrode of PMOS is connected with the drain electrode of second NMOS tube, source electrode and first NMOS tube of the 7th PMOS Drain electrode after drain electrode is connected again with first PMOS is connected, source electrode and the 3rd NMOS tube of the 8th PMOS Drain electrode after drain electrode is connected again with the 4th PMOS is connected；
The p-type voltage bias transistor unit includes：13rd PMOS；The grid of 13rd PMOS is together Mould control signal is connected, and source electrode is connected with the supply voltage, drain electrode and the 9th PMOS, the tenth PMOS, institute The source electrode that the 11st PMOS is stated with the 12nd PMOS is connected.
Alternatively,
The N-type biasing tail current transistor unit includes：6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube and Nine NMOS tubes；The grid of wherein described 6th NMOS tube be connected with the grid of the 7th NMOS tube after again with the described 12nd The drain electrode of PMOS is connected, the grid of the 8th NMOS tube be connected with the grid of the 9th NMOS tube after again with the described tenth The drain electrode of PMOS is connected, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube and the 9th NMOS tube Source ground；
The N-type cascode transistors include to unit：Tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube With the 13rd NMOS tube；Wherein, with the 3rd after the grid of the tenth NMOS tube is connected with the grid of the 11st NMOS tube Bias voltage is connected, the grid of the 12nd NMOS tube be connected with the grid of the 13rd NMOS tube after also with the described 3rd Bias voltage is connected, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the 7th NMOS tube, the 11st NMOS tube Source electrode be connected with the drain electrode of the 8th NMOS tube, drain electrode and the drain electrode of the 12nd PMOS of the tenth NMOS tube It is connected, the drain electrode of the 11st NMOS tube is connected with the drain electrode of the tenth PMOS, the source electrode of the 12nd NMOS tube Drain electrode again with the 6th NMOS tube is connected after drain electrode with the 9th PMOS is connected, the source of the 13rd NMOS tube Drain electrode again with the 9th NMOS tube is connected after pole is connected with the drain electrode of the 11st PMOS.
Alternatively,
The drain electrode of 7th PMOS is connected with the drain electrode of the 12nd NMOS tube exports the first output difference signal VOUTP, the drain electrode of the 8th PMOS is connected with the drain electrode of the 13rd NMOS tube exports the second output difference signal VOUTN, the first output difference signal VOUTP and the second output difference signal VOUTN collectively form fully differential output Signal.
Alternatively, the operational amplifier biasing circuit of the data-driven includes：Bias-voltage generating circuit, input difference Signal comparator and data driving current branch road.
Alternatively,
The bias-voltage generating circuit includes：First bias current sources, the 14th NMOS tube, the 15th NMOS tube, 16 NMOS tubes, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS Pipe, the 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS Pipe, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS tube, the 14th PMOS, the 15th PMOS, 16 PMOSs, the 17th PMOS, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS Pipe, the 22nd PMOS, the 23rd PMOS, the 24th PMOS, the 25th PMOS, the 26th PMOS With the 27th PMOS；
Wherein, the first bias current sources negative pole is connected with the supply voltage, the first bias current sources positive pole Drain electrode with the 14th NMOS tube be connected after again with the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the grid phase of the 20th NMOS tube and the 21st NMOS tube Even, the source electrode of the 14th NMOS tube is connected with the drain electrode of the 15th NMOS tube, the source electrode of the 16th NMOS tube Drain electrode with the 17th NMOS tube is connected, the source electrode and the drain electrode phase of the 19th NMOS tube of the 18th NMOS tube Even, the source electrode of the 20th NMOS tube is connected with the drain electrode of the 21st NMOS tube, the 22nd NMOS tube Grid after drain and gate is connected again with the 23rd NMOS tube and the 24th NMOS tube is connected, and described second The source electrode of 12 NMOS tubes be connected with the drain electrode of the 23rd NMOS tube and the 24th NMOS tube after again with it is described The source electrode of 25th NMOS tube is connected, the source electrode and the drain electrode phase of the 28th NMOS tube of the 23rd NMOS tube Even, the source electrode of the 24th NMOS tube is connected with the drain electrode of the 29th NMOS tube, the 28th NMOS tube Grid connect the first control word, the grid of the 29th NMOS tube connects the second control word, the 25th NMOS tube Grid is connected with the grid of the 26th NMOS tube again after being connected with drain electrode is used as the 3rd bias voltage, and the described 26th The drain electrode of NMOS tube is connected with the grid of the 27th NMOS tube is used as first bias voltage, and the described 26th The source electrode of NMOS tube is connected with the drain electrode of the 27th NMOS tube, the 15th NMOS tube, the 17th NMOS tube, the tenth Nine NMOS tubes, the 21st NMOS tube, the 27th NMOS tube, the source electrode of the 28th NMOS tube and the 29th NMOS tube connect Ground, the grid of the 14th PMOS and drain electrode and the grid of the 15th PMOS and the grid of the 16th PMOS Drain electrode after being extremely connected again with the 16th NMOS tube is connected, source electrode and the 15th PMOS of the 14th PMOS Source electrode after the drain electrode of pipe and the drain electrode of the 16th PMOS are connected again with the 17th PMOS is connected, and the described tenth The source electrode of five PMOSs is connected with the drain electrode of the 26th PMOS, the source electrode of the 16th PMOS and the 27th PMOS The drain electrode of pipe is connected, and the grid of the 26th PMOS connects the 3rd control word, and the grid of the 27th PMOS connects Drain electrode phase continuous cropping with the 18th NMOS tube again after 4th control word, the grid of the 17th PMOS and drain electrode are connected For second bias voltage, second bias voltage and the 18th PMOS, the 20th PMOS, the 22nd PMOS is connected with the grid of the 24th PMOS, the drain electrode and the leakage of the 20th NMOS tube of the 18th PMOS Extremely it is connected, the source electrode of the 18th PMOS is connected with the drain electrode of the 19th PMOS, the 19th PMOS Grid is connected inclined as the 4th with the drain electrode of the 18th PMOS again after being connected with the grid of the 21st PMOS Voltage is put, the 4th bias voltage is connected with the grid of the 23rd PMOS and the 25th PMOS, and described The source electrode of 20 PMOSs is connected with the drain electrode of the 21st PMOS, the drain electrode of the 20th PMOS and described the The drain electrode of 22 NMOS tubes is connected, the source electrode and the drain electrode phase of the 23rd PMOS of the 22nd PMOS Even, the drain electrode of the 22nd PMOS is connected with the drain electrode of the 25th NMOS tube, the 24th PMOS Source electrode be connected with the drain electrode of the 25th PMOS, the drain electrode and the described 26th of the 24th PMOS The drain electrode of NMOS tube is connected, the 19th PMOS, the 21st PMOS, the 23rd PMOS, the 25th PMOS Pipe, the 26th PMOS, the source electrode of the 27th PMOS connect the supply voltage；
The input differential signal comparator includes：First comparator and the second comparator；Wherein, the first comparator Negative input end and the positive input of second comparator terminate the first differential signal VINN, the first comparator is just The negative input of input and second comparator terminates the second differential signal VINP, the first comparator output first Control signal VC1, second comparator export the second control signal VC2；
The data-driven current branch includes：Second bias current sources, the 3rd bias current sources, the 30th NMOS tube, 31st NMOS tube, the 32nd NMOS tube, the 33rd NMOS tube, the 34th NMOS tube and the 35th NMOS tube；
Wherein, the second bias current sources negative pole and the 3rd bias current sources negative pole and the supply voltage phase Even, after the source electrode of the 30th NMOS tube is connected with the source electrode of the 31st NMOS tube again with second bias current Source positive pole is connected, and the grid of the 30th NMOS tube connects the first control signal VC1, the grid of the 31st NMOS tube Pole meets the second control signal VC2, and the drain electrode of the 30th NMOS tube is connected with the drain electrode of the 31st NMOS tube The drain electrode again with the 34th NMOS tube is connected afterwards, and the grid of the 34th NMOS tube connects the 5th control word, The source electrode of 32nd NMOS tube be connected with the source electrode of the 33rd NMOS tube after again with the 3rd bias current Source positive pole is connected, and the grid of the 32nd NMOS tube meets the first control signal VC1, the 33rd NMOS tube Grid connects the second control signal VC2, the drain electrode and the drain electrode of the 33rd NMOS tube of the 32nd NMOS tube Drain electrode after being connected again with the 35th NMOS tube is connected, and the grid of the 35th NMOS tube connects the 6th control word, The source electrode of 34th NMOS tube and the source electrode and the drain electrode phase of the 14th NMOS tube of the 35th NMOS tube Even.
Alternatively, the first comparator and the second comparator include：Comparator main circuit and bias current are adjustable Biasing circuit；
The comparator main circuit includes：36th NMOS tube, the 37th NMOS tube, the 38th NMOS tube, 39 NMOS tubes, the 40th NMOS tube, the 41st NMOS tube, the 42nd NMOS tube, the 43rd NMOS tube, the 40th Four NMOS tubes, the 45th NMOS tube, the 46th NMOS tube, the 47th NMOS tube, the 48th NMOS tube, the 28th PMOS, the 29th PMOS, the 30th PMOS, the 31st PMOS, the 32nd PMOS, the 33rd PMOS Pipe, the 34th PMOS, the 35th PMOS, the 36th PMOS, the 37th PMOS, the 38th PMOS Pipe, the 39th PMOS, the 40th PMOS, the 41st PMOS, the 42nd PMOS and the 43rd PMOS；
Wherein, the 36th NMOS tube, the 37th NMOS tube grid with the input differential signal 3rd differential signal VCN is connected, and the 38th NMOS tube, the grid of the 39th NMOS tube are believed with the input difference The 4th differential signal VCP in number is connected, and the 40th NMOS tube grid connects the 5th bias voltage, source ground, and drain electrode connects 36th NMOS tube, the 37th NMOS tube, the source electrode of the 38th NMOS tube and the 39th NMOS tube, described Leakage with the 39th NMOS tube again after the grid of 28 PMOSs is connected with the grid of the 29th PMOS Extremely it is connected, the 28th PMOS, the 29th PMOS, the source electrode of the 30th PMOS and the 31st PMOS connect Supply voltage, the grid of the 32nd PMOS is connected with the grid of the 33rd PMOS is followed by the 6th biased electrical Pressure, the grid of the 34th PMOS also connect the 6th biased electrical after being connected with the grid of the 35th PMOS Pressure, the source electrode of the 32nd PMOS are connected with the drain electrode of the 29th PMOS, the 33rd PMOS Source electrode be connected with the drain electrode of the 30th PMOS, the drain electrode of the 32nd PMOS and the 39th NMOS The drain electrode of pipe is connected, and the drain electrode of the 33rd PMOS is connected with the drain electrode of the 37th NMOS tube, and the described 3rd Drain electrode with the 28th PMOS again after the source electrode of 14 PMOSs is connected with the drain electrode of the 36th NMOS tube Be connected, the source electrode of the 35th PMOS be connected with the drain electrode of the 38th NMOS tube after again with the described 31st The drain electrode of PMOS is connected, the grid of the 36th PMOS and the 37th PMOS all with the 3rd differential signal VCN is connected, and the grid of the 38th PMOS and the 39th PMOS is connected with the 4th differential signal VCP, The grid of 40th PMOS and the 41st PMOS connects the 7th bias voltage, and the source electrode of the 40th PMOS connects The drain electrode of 42nd PMOS, the source electrode of the 41st PMOS connect the drain electrode of the 43rd PMOS, The grid of 42nd PMOS connects the 7th control word, and the grid of the 43rd PMOS connects the 8th control word, institute The source electrode for stating the 42nd PMOS and the 43rd PMOS connects the supply voltage, the 40th PMOS and the 40th The drain electrode of one PMOS connects the 36th PMOS, the 37th PMOS, the 38th PMOS and the 39th The source electrode of PMOS, the grid of the 41st NMOS tube be connected with the grid of the 42nd NMOS tube after again with it is described The drain electrode of 39th PMOS is connected, the grid and the grid phase of the 44th NMOS tube of the 43rd NMOS tube Lian Houzai is connected with the drain electrode of the 37th PMOS, the 41st NMOS tube, the 42nd NMOS tube, the 40th The source ground of three NMOS tubes and the 44th NMOS tube, grid and the 46th NMOS of the 45th NMOS tube The grid of pipe, which is connected, is followed by the 8th bias voltage, the grid of the 47th NMOS tube and the grid of the 48th NMOS tube Also the 8th bias voltage, the source electrode of the 45th NMOS tube and the leakage of the 42nd NMOS tube are connect after being extremely connected Extremely it is connected, the source electrode of the 46th NMOS tube is connected with the drain electrode of the 43rd NMOS tube, and the described 45th The drain electrode of NMOS tube is connected with the drain electrode of the 39th PMOS, the drain electrode and the described 3rd of the 46th NMOS tube The drain electrode of 17 PMOSs is connected, after the source electrode of the 47th NMOS tube is connected with the drain electrode of the 36th PMOS The drain electrode with the 41st NMOS tube is connected again, source electrode and the 38th PMOS of the 48th NMOS tube Drain electrode be connected after drain electrode again with the 44th NMOS tube be connected, the drain electrode of the 48th NMOS tube and described the 35 PMOSs drain electrode be connected after again with the grid of the 30th PMOS and the grid of the 31st PMOS It is connected, the 47th NMOS tube is connected with the 34th PMOS as comparator output VCOUT；
The adjustable biasing circuit of bias current includes：4th bias current sources, the 5th bias current sources, the 49th NMOS tube, the 50th NMOS tube, the 51st NMOS tube, the 52nd NMOS tube, the 53rd NMOS tube, the 54th NMOS Pipe, the 55th NMOS tube, the 56th NMOS tube, the 57th NMOS tube, the 58th NMOS tube, the 59th NMOS Pipe, the 60th NMOS tube, the 61st NMOS tube, the 62nd NMOS tube, the 63rd NMOS tube, the 44th PMOS, 45th PMOS, the 46th PMOS, the 47th PMOS, the 48th PMOS, the 49th PMOS, 50 PMOSs, the 51st PMOS, the 52nd PMOS, the 53rd PMOS and the 54th PMOS；
Wherein, the 4th bias current sources negative pole and the 5th bias current sources negative pole and the supply voltage phase Even, the drain electrode of the 49th NMOS tube and the 49th NMOS tube, the 50th NMOS tube, the 51st NMOS tube, 52nd NMOS tube, the 53rd NMOS tube, the 54th NMOS tube, the 55th NMOS tube and the 56th NMOS tube Grid is connected, and the source electrode of the 49th NMOS tube is connected with the drain electrode of the 50th NMOS tube, and the described 51st The source electrode of NMOS tube is connected with the drain electrode of the 52nd NMOS tube, the source electrode and the described 5th of the 53rd NMOS tube The drain electrode of 14 NMOS tubes is connected, and the source electrode of the 55th NMOS tube is connected with the drain electrode of the 56th NMOS tube, Grid after the drain and gate of 57th NMOS tube is connected again with the 58th NMOS tube is connected, and the described 5th Source electrode with the 59th NMOS tube again after the drain electrode of the source electrode of 17 NMOS tubes and the 58th NMOS tube is connected Be connected, the grid of the 59th NMOS tube with drain be connected after be connected with the grid of the 60th NMOS tube be used as institute again State the 8th bias voltage, the drain electrode of the 60th NMOS tube is connected with the grid of the 61st NMOS tube as described the Five bias voltages, the source electrode of the 60th NMOS tube are connected with the drain electrode of the 61st NMOS tube, and the described 50th NMOS tube, the 52nd NMOS tube, the 54th NMOS tube, the 56th NMOS tube, the 58th NMOS tube, the 61st The source ground of NMOS tube, the grid of the 44th PMOS are connected with the grid of the 45th PMOS and drain electrode The drain electrode again with the 51st NMOS tube is connected afterwards, source electrode and the 45th PMOS of the 44th PMOS Source electrode again with the 46th PMOS is connected after the drain electrode of pipe is connected, the grid of the 46th PMOS and drain electrode Be connected again with the drain electrode of the 53rd NMOS tube after being connected as the 6th bias voltage, second bias voltage and 47th PMOS, the 49th PMOS, the 51st PMOS are connected with the grid of the 53rd PMOS, institute The drain electrode for stating the 47th PMOS is connected with the drain electrode of the 55th NMOS tube, the source electrode of the 47th PMOS Drain electrode with the 48th PMOS is connected, the grid of the 48th PMOS and the grid of the 50th PMOS It is connected again with the drain electrode of the 47th PMOS after being extremely connected as the 7th bias voltage, the 4th bias voltage Be connected with the grid of the 52nd PMOS and the 54th PMOS, the source electrode of the 49th PMOS with it is described The drain electrode of 50th PMOS is connected, the drain electrode of the 49th PMOS and the drain electrode phase of the 57th NMOS tube Even, the source electrode of the 51st PMOS is connected with the drain electrode of the 52nd PMOS, the 51st PMOS Drain electrode be connected with the drain electrode of the 59th NMOS tube, the source electrode and the described 54th of the 53rd PMOS The drain electrode of PMOS is connected, and the drain electrode of the 53rd PMOS is connected with the drain electrode of the 60th NMOS tube, and described 45 PMOSs, the 48th PMOS, the 50th PMOS, the 52nd PMOS, the source electrode of the 54th PMOS The supply voltage is connect, the positive pole of the 4th bias current sources is connected with the drain electrode of the 62nd NMOS tube, and described The grid of 62 NMOS tubes connects the 9th control word, positive pole and the 63rd NMOS tube of the 5th bias current sources Drain electrode is connected, and the grid of the 63rd NMOS tube connects the tenth control word, the source electrode of the 62nd NMOS tube and The source electrode of 63rd NMOS tube is connected with the drain electrode of the 49th NMOS tube.
Alternatively, the circularly folding operational transconductance amplifier circuit of N-type and the p-type Complementary input structure also includes：Common mode is anti- Current feed circuit；The common mode feedback circuit includes：Fully differential signal and common-mode signal input crystal pipe unit, voltage bias transistor Unit and common-mode feedback control signal generation unit；
The fully differential signal includes with common-mode signal input crystal pipe unit：64th NMOS tube, the 65th NMOS tube, the 66th NMOS tube, the 67th NMOS tube；
Wherein, the grid of the 64th NMOS tube meets the second output difference signal VOUTN, and the described 67th The grid of NMOS tube connects the first output difference signal VOUTP, the grid and the described 60th of the 65th NMOS tube The grid of six NMOS tubes, which is connected, is followed by input common mode voltage VCM；
The voltage bias transistor unit includes：68th NMOS tube and the 69th NMOS tube；
Wherein, the drain electrode of the 68th NMOS tube and the source electrode and the described 65th of the 64th NMOS tube The source electrode of NMOS tube is connected, the drain electrode of the 69th NMOS tube and the source electrode and the described 6th of the 66th NMOS tube The source electrode of 17 NMOS tubes is connected, after the grid of the 68th NMOS tube is connected with the grid of the 69th NMOS tube It is connected with first bias voltage, the source electrode of the 68th NMOS tube and the source electrode of the 69th NMOS tube connect Ground；
The common-mode feedback control signal generation unit includes：55th PMOS, the 56th PMOS and phase The first resistor R1 and second resistance R2 mutually concatenated；
Wherein, with described the after the grid of the 55th PMOS is connected with the grid of the 56th PMOS One resistance R1 is connected with second resistance R2 series side, and draining for the 55th PMOS is non-with the first resistor R1 Series side is connected with the drain electrode of the 64th NMOS tube and the drain electrode of the 67th NMOS tube again after being connected, and in phase Company is followed by common mode control signal VCMFB, the drain electrode of the 56th PMOS and the non-series side phase of the second resistance R2 Lian Houzai is connected with the drain electrode of the 65th NMOS tube and the drain electrode of the 66th NMOS tube, the 55th PMOS The source electrode of source electrode and the 56th PMOS connect the supply voltage.
The embodiment of the present invention includes：The N-type of interconnection and the circularly folding operational transconductance amplifier electricity of p-type Complementary input structure Road and the operational amplifier biasing circuit of data-driven；It is poor that the operational amplifier biasing circuit of the data-driven includes input Sub-signal comparator；The input differential signal comparator, for detecting input differential signal, and work as the input differential signal More than or equal to the input differential signal comparator opening threshold value when increasing circuit bias current, when the input difference When signal is less than the opening threshold value of the input differential signal comparator, the bias current of holding circuit will not become.And can root Threshold value and comparator speed are opened according to application demand dynamic adjustment amplifier current size, and comparator, controls high current Operation window.By the embodiment scheme, the speed of high performance switch condenser network is improved, and reduces power consumption, improve Yield.
The further feature and advantage of the embodiment of the present invention will illustrate in the following description, also, partly from explanation Become apparent in book, or understood by implementing the embodiment of the present invention.The purpose of the embodiment of the present invention and other advantages It can realize and obtain by specifically noted structure in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used for providing further understanding technical scheme of the embodiment of the present invention, and one of constitution instruction Point, the technical scheme for explaining the embodiment of the present invention is used for together with embodiments herein, is not formed to the embodiment of the present invention The limitation of technical scheme.
Fig. 1 is the schematic diagram of the operational amplifier of the data-driven of the embodiment of the present invention；
Fig. 2 is the first comparator of the embodiment of the present invention and the circuit diagram of the second comparator；
Fig. 3 is the circuit diagram of the common mode feedback circuit of the embodiment of the present invention.
Embodiment
For the purpose, technical scheme and advantage of the embodiment of the present invention are more clearly understood, below in conjunction with accompanying drawing pair Embodiments of the invention are described in detail.It should be noted that in the case where not conflicting, embodiment and reality in the application Applying the feature in example can mutually be combined.
In order to reach purpose of the embodiment of the present invention, the embodiments of the invention provide a kind of operational amplifier of data-driven, The operational amplifier includes：The N-type of interconnection and the circularly folding operational transconductance amplifier circuit and number of p-type Complementary input structure According to the operational amplifier biasing circuit of driving；The operational amplifier biasing circuit of the data-driven includes input differential signal ratio Compared with device；
The input differential signal comparator, for detecting input differential signal, and when the input differential signal is more than Or equal to the input differential signal comparator opening threshold value when increasing circuit bias current, when the input differential signal Less than the input differential signal comparator opening threshold value when, the bias current of holding circuit will not become.
In embodiments of the present invention, in order to overcome, current collapsible OTA (single stage op trsanscondutance amplifier) speed is slow, power consumption Big deficiency, the embodiment of the present invention devise the operational amplifier of data-driven.The embodiment of the present invention is detected defeated by comparator Enter differential signal, when input differential signal is more than the bias current of increasing circuit when comparator opens threshold value to improve amplifier Speed, when input differential signal, which is less than comparator, opens threshold value, the bias current of circuit will not increase, so as to save power consumption, Further according to different application demands, the bias current or comparator that can adjust data-driven branch road open threshold value or comparator Speed.By scheme of the embodiment of the present invention, the high performance switching capacity such as high-performance analog-digital converter, wave filter can be improved The speed of circuit, the compromise avoided between traditional class ab ammplifier quiescent dissipation and maximum output current and intermodulation distortion are closed System, compared with traditional class-a amplifier, both had at a high speed, high linearity the advantages of, overcome that quiescent bias current is big to be lacked again Point.
Alternatively, the circularly folding operational transconductance amplifier circuit of N-type and the p-type Complementary input structure includes：
N-type Complementary input structure differential pair unit and the N-type bias voltage being connected with the N-type Complementary input structure differential pair unit Transistor unit, N-type biasing tail current transistor unit and N-type cascode transistors are to unit；And
P-type Complementary input structure differential pair unit and the p-type bias voltage being connected with the p-type Complementary input structure differential pair unit Transistor unit, p-type biasing tail current transistor unit and p-type cascode transistors are to unit.
In embodiments of the present invention, Fig. 1 is a Complementary input structure circularly folding operational transconductance amplifier with being driven with data The biasing circuit of dynamic branch road.The Complementary input structure loop collapsing OTA is different from conventional OTA, and which employs NMOS (N- ChannelMetal-Oxide-Semiconductor, N-channel Metal-oxide-semicondutor) manage and PMOS (P-channel Metal-Oxide-Semiconductor, P-channel Metal-oxide-semicondutor) pipe branch road Complementary input structure.
In embodiments of the present invention, transistor P1a, P1b, P2a, P2b are p-type entering apparatus in Fig. 1, N1a, N1b, N2a, N2b is N-type entering apparatus.VINN and VINP is input differential signal, and VINN is added to P1a, P1b, N1a, N1b grid, VINP It is added to P2a, P2b, N2a, N2b grid.Transistor P0 inputs branch road P1a, P1b, P2a, P2b for p-type and provides bias current, brilliant Body pipe N0 inputs branch road N1a, N1b, N2a, N2b for N-type and provides bias current.Transistor N5, N6, N7, N8 are that p-type inputs branch road Biasing tail current transistor, transistor P5, P6, P7, P8 be N-type input branch road biasing tail current transistor.Transistor N3, N4, N9, N10 are the cascode transistors pair that p-type inputs branch road, and transistor P3, P4, P9, P10 are that N-type inputs being total to for branch road The common gate transistor pair in source.Transistor P9 drain electrode is connected with transistor N9 drain electrode provides a difference output VOUTP, transistor P10 drain electrode is connected with transistor N10 drain electrode provides another difference output VOUTN.VOUTP and VOUTN forms fully differential Output.Transistor N0 bias voltage is Vb1, and transistor N3, N4, N9, N10 bias voltage is Vb2, transistor P3, P4, P9, P10 bias voltage are Vb3, and transistor P0 bias voltage is then caused common mode control signal in common mode feedback circuit VCMFB.The complementary cycle that the present invention uses folds OTA, cascode transistors N9, N10 of p-type input branch road and N-type input Cascode transistors P9, P10 of branch road have shared identical electric current, thus more fully make use of the electric current of each branch road, Improve the unity gain bandwidth GBW of amplifier.The annexation of unit in Fig. 1 will be described in detail below.
The N-type Complementary input structure differential pair unit includes：First NMOS tube (N1a), the second NMOS tube (N1b), the 3rd NMOS tube (N2a), the 4th NMOS tube (N2b), wherein the grid of the first NMOS tube (N1a), the second NMOS tube (N1b) all with input One of differential signal VINN (i.e. the first differential signal VINN) in fully differential signal is connected, the 3rd NMOS tube (N2a), the The grid of four NMOS tubes (N2b) all with it is foregoing input fully differential signal in another differential signal VINP (the second differential signals VINP) it is connected；
The N-type voltage bias transistor unit includes：5th NMOS tube (N0), the 5th NMOS tube (N0) grid connect One bias voltage (Vb1), source ground (GND), drain electrode meet the first NMOS tube (N1a), the second NMOS tube (N1b), the 3rd NMOS Manage (N2a) and the source electrode of the 4th NMOS tube (N2b).
The p-type Complementary input structure differential pair unit includes：9th PMOS (P1a), the tenth PMOS (P1b), the 11st PMOS (P2a) and the 12nd PMOS (P2b)；Wherein, the 9th PMOS (P1a), the tenth PMOS (P1b) grid all with One of differential signal VINN in input fully differential signal is connected, the 11st PMOS (P2a), the 12nd PMOS (P2b) grid is all connected with another differential signal VINP in foregoing input fully differential signal.
The p-type biasing tail current transistor unit includes：First PMOS (P5), the second PMOS (P6), the 3rd PMOS (P7) and the 4th PMOS (P8)；Wherein, the grid of the first PMOS (P5) and the grid phase of the second PMOS (P6) Lian Houzai is connected with the drain electrode of the 4th NMOS tube (N2b), the grid of the 3rd PMOS (P7) and the 4th PMOS (P8) Drain electrode again with second NMOS tube (N1b) is connected after grid is connected, the first PMOS (P5), the second PMOS (P6), the The source electrode of three PMOSs (P7) and the 4th PMOS (P8) connects supply voltage (VDD).
The p-type cascode transistors include to unit：5th PMOS (P3), the 6th PMOS (P4), the 7th PMOS (P9) and the 8th PMOS (P10)；Wherein, the grid and the grid phase of the 6th PMOS (P4) of the 5th PMOS (P3) Company is followed by the second bias voltage (Vb3), and the grid of the 7th PMOS (P9) also connects after being connected with the grid of the 8th PMOS (P10) Second bias voltage (Vb3), the source electrode of the 5th PMOS (P3) are connected with the drain electrode of second PMOS (P6), the 6th PMOS The source electrode of pipe (P4) is connected with the drain electrode of the 3rd PMOS (P7), drain electrode and the 4th NMOS of the 5th PMOS (P3) The drain electrode of pipe (N2b) is connected, and the drain electrode of the 6th PMOS (P4) is connected with the drain electrode of second NMOS tube (N1b), and the 7th Drain electrode with first PMOS (P5) again after the source electrode of PMOS (P9) is connected with the drain electrode of first NMOS tube (N1a) Be connected, the source electrode of the 8th PMOS (P10) be connected with the drain electrode of the 3rd NMOS tube (N2a) after again with the 4th PMOS (P8) drain electrode is connected.
The p-type voltage bias transistor unit includes：13rd PMOS (P0)；13rd PMOS (P0) grid Common mode control signal (VCMFB) is connect, source electrode connects supply voltage (VDD), and drain electrode connects the 9th PMOS (P1a), the tenth PMOS (P1b), the source electrode of the 11st PMOS (P2a) and the 12nd PMOS (P2b).
The N-type biasing tail current transistor unit includes：6th NMOS tube (N5), the 7th NMOS tube (N6), the 8th NMOS tube (N7) and the 9th NMOS tube (N8)；Wherein, the grid and the grid phase of the 7th NMOS tube (N6) of the 6th NMOS tube (N5) Lian Houzai is connected with the drain electrode of the 12nd PMOS (P2b), the grid and the 9th NMOS tube (N8) of the 8th NMOS tube (N7) Grid be connected after drain electrode again with the tenth PMOS (P1b) be connected, the 6th NMOS tube (N5), the 7th NMOS tube (N6), The source ground (GND) of 8th NMOS tube (N7) and the 9th NMOS tube (N8).
The N-type cascode transistors include to unit：Tenth NMOS tube (N3), the 11st NMOS tube (N4), the tenth Two NMOS tubes (N9) and the 13rd NMOS tube (N10)；Wherein, the grid of the tenth NMOS tube (N3) and the 11st NMOS tube (N4) Grid, which is connected, is followed by the 3rd bias voltage (Vb2), the grid of the 12nd NMOS tube (N9) and the grid of the 13rd NMOS tube (N10) The 3rd bias voltage (Vb2), the source electrode and the drain electrode phase of the 7th NMOS tube (N6) of the tenth NMOS tube (N3) are also connect after being connected Even, the source electrode of the 11st NMOS tube (N4) is connected with the drain electrode of the 8th NMOS tube (N7), the drain electrode of the tenth NMOS tube (N3) Drain electrode with the 12nd PMOS (P2b) is connected, drain electrode and the tenth PMOS (P1b) of the 11st NMOS tube (N4) Drain electrode be connected, the source electrode of the 12nd NMOS tube (N9) be connected with the drain electrode of the 9th PMOS (P1a) after again with described The drain electrode of six NMOS tubes (N5) is connected, the source electrode and the drain electrode phase of the 11st PMOS (P2a) of the 13rd NMOS tube (N10) Lian Houzai is connected with the drain electrode of the 9th NMOS tube (N8).
The drain electrode of 7th PMOS (P9) is connected output difference signal with the drain electrode of the 12nd NMOS tube (N9) (VOUTP), i.e. the first output difference signal VOUTP；The drain electrode of 8th PMOS (P10) and the 13rd NMOS tube (N10) Drain electrode be connected export another differential signal (VOUTN), i.e. the second output difference signal VOUTN；The differential signal VOUTP Fully differential output signal is collectively formed with VOUTN.
Alternatively, the operational amplifier biasing circuit of the data-driven includes：Bias-voltage generating circuit, input difference Signal comparator and data driving current branch road.
In embodiments of the present invention, the biasing circuit of the OTA is different from normal bias circuit, is put in common offer computing Outside the circuit of big device bias voltage, a data-driven branch road and two comparators also add.Transistor M1, M2, M3, M4、M5、M6a、M6b、M7、M8、M9、M10、M11、M12、M13、M14、M15、M16、M17a、M17b、M18、M19、M20、M21、 M22, M23, M24, MK3, MK4, MK5, MK6 form operational amplifier biasing main circuit, and transistor M24 grid connects bias voltage Vb1, transistor M18, M23 grid meet bias voltage Vb2, and transistor M7, M12, M14, M19, M21 grid connect bias voltage Vb3, transistor M13, M15, M20, M22 grid meet bias voltage Vb4.By control word EN3, EN4 controlling transistor MK3, MK4 break-make, M6a, M6b parallel with one another can be optionally set to access circuit, so as to change bias voltage Vb3 value.It is logical The break-make of control word EN5, EN6 controlling transistor MK5, MK6 is crossed, can access optionally M17a, M17b parallel with one another Circuit, so as to change bias voltage Vb2 value.Current source I1 provides the bias current of routine for biasing circuit.Comparator COMP1 Negative input end and comparator COMP2 positive input termination differential input signal VINN, comparator COMP1 positive input terminal and ratio Negative input termination differential input signal VINP compared with device COMP2.Data-driven branch route transistor MS1, MS2, MS3, MS4, MK1, MK2 and current source I2, I3 are formed, and transistor MS1, MS3 grid meet comparator COMP1 output, transistor MS2, MS4 Grid connect comparator COMP2 output.When input differential signal is larger, its in comparator COMP1 and comparator COMP2 In a meeting be triggered, high level is exported, so as to one of them in transistor MS1 and transistor MS2, transistor MS3 and crystalline substance One of them in body pipe MS4 can be turned on accordingly, and current source I2 or I3 electric current are added into biasing circuit, so as to improve OTA speed.Control word EN1, EN2 optionally turns on transistor MK1, MK2, so as to control data driving branch current Size.The annexation of each circuit in the operational amplifier biasing circuit of the data-driven will be done in detail respectively below It is thin to introduce.
The bias-voltage generating circuit includes：First bias current sources (I1), the 14th NMOS tube (M1), the 15th NMOS tube (M2), the 16th NMOS tube (M3), the 17th NMOS tube (M4), the 18th NMOS tube (M8), the 19th NMOS tube (M9), the 20th NMOS tube (M10), the 21st NMOS tube (M11), the 22nd NMOS tube (M16), the 23rd NMOS tube (M17a), the 24th NMOS tube (M17b), the 25th NMOS tube (M18), the 26th NMOS tube (M23), the 27th NMOS tube (M24), the 28th NMOS tube (MK5), the 29th NMOS tube (MK6), the 14th PMOS (M5), the 15th PMOS (M6a), the 16th PMOS (M6b), the 17th PMOS (M7), the 18th PMOS (M12), the 19th PMOS (M13), the 20th PMOS (M14), the 21st PMOS (M15), the 22nd PMOS (M19), the 23rd PMOS Manage (M20), the 24th PMOS (M21), the 25th PMOS (M22), the 26th PMOS (MK3) and the 27th PMOS (MK4)；
Wherein, the first bias current sources (I1) negative pole is connected with supply voltage (VDD), the first bias current sources (I1) positive pole Drain electrode with the 14th NMOS tube (M1) be connected after again with the 14th NMOS tube (M1), the 15th NMOS tube (M2), the 16th NMOS tube (M3), the 17th NMOS tube (M4), the 18th NMOS tube (M8), the 19th NMOS tube (M9), the 20th NMOS tube (M10) grid with the 21st NMOS tube (M11) is connected, the source electrode and the 15th NMOS tube (M2) of the 14th NMOS tube (M1) Drain electrode be connected, the source electrode of the 16th NMOS tube (M3) is connected with the drain electrode of the 17th NMOS tube (M4), the 18th NMOS tube (M8) source electrode is connected with the drain electrode of the 19th NMOS tube (M9), the source electrode and the 21st NMOS of the 20th NMOS tube (M10) The drain electrode of pipe (M11) is connected, the drain and gate of the 22nd NMOS tube (M16) be connected after again with the 23rd NMOS tube (M17a) grid with the 24th NMOS tube (M17b) is connected, the source electrode and the 23rd of the 22nd NMOS tube (M16) Source electrode phase with the 25th NMOS tube (M18) again after the drain electrode of NMOS tube (M17a) and the 24th NMOS tube (M17b) is connected Even, the source electrode of the 23rd NMOS tube (M17a) is connected with the drain electrode of the 28th NMOS tube (MK5), the 24th NMOS tube (M17b) source electrode is connected with the drain electrode of the 29th NMOS tube (MK6), and the grid of the 28th NMOS tube (MK5) connects the first control Word (EN5) processed, the grid of the 29th NMOS tube (MK6) connect the second control word (EN6), the grid of the 25th NMOS tube (M18) Pole is connected with the grid of the 26th NMOS tube (M23) again after being connected with drain electrode is used as the 3rd bias voltage (Vb2), and the 26th The drain electrode of NMOS tube (M23) is connected with the grid of the 27th NMOS tube (M24) is used as the first bias voltage (Vb1), and the 20th The source electrode of six NMOS tubes (M23) is connected with the drain electrode of the 27th NMOS tube (M24), the 15th NMOS tube (M2), the 17th NMOS tube (M4), the 19th NMOS tube (M9), the 21st NMOS tube (M11), the 27th NMOS tube (M24), the 28th The source ground (GND) of NMOS tube (MK5), the 29th NMOS tube (MK6), the grid of the 14th PMOS (M5) and drain electrode with The grid of 15th PMOS (M6a) and the grid of the 16th PMOS (M6b) be connected after again with foregoing 16th NMOS tube (M3) drain electrode is connected, the source electrode of the 14th PMOS (M5) and drain electrode and the 16th PMOS of the 15th PMOS (M6a) (M6b) source electrode after drain electrode is connected again with the 17th PMOS (M7) is connected, the source electrode and second of the 15th PMOS (M6a) The drain electrode of 16 PMOSs (MK3) is connected, the source electrode of the 16th PMOS (M6b) and the drain electrode of the 27th PMOS (MK4) It is connected, the grid of the 26th PMOS (MK3) connects the 3rd control word (EN3), and the 27th PMOS (MK4) grid connects the 4th Drain electrode with foregoing 18th NMOS tube (M8) again after control word (EN4), the grid of the 17th PMOS (M7) and drain electrode are connected It is connected and is used as the second bias voltage (Vb3), second bias voltage (Vb3) and the 18th PMOS (M12), the 20th PMOS (M14), the 22nd PMOS (M19) is connected with the grid of the 24th PMOS (M21), the 18th PMOS (M12) Drain electrode is connected with the drain electrode of foregoing 20th NMOS tube (M10), the source electrode and the 19th PMOS of the 18th PMOS (M12) (M13) drain electrode is connected, the grid of the 19th PMOS (M13) be connected with the grid of the 21st PMOS (M15) after again with The drain electrode of 18th PMOS (M12), which is connected, is used as the 4th bias voltage (Vb4), the 4th bias voltage (Vb4) and the 20th Three PMOSs (M20) are connected with the grid of the 25th PMOS (M22), the source electrode and the 20th of the 20th PMOS (M14) The drain electrode of one PMOS (M15) is connected, the drain electrode of the 20th PMOS (M14) and the leakage of foregoing 22nd NMOS tube (M16) Extremely it is connected, the source electrode of the 22nd PMOS (M19) is connected with the drain electrode of the 23rd PMOS (M20), the 22nd PMOS Pipe (M19) drain electrode be connected with the drain electrode of foregoing 25th NMOS tube (M18), the source electrode of the 24th PMOS (M21) and The drain electrode of 25th PMOS (M22) is connected, drain electrode and foregoing 26th NMOS tube of the 24th PMOS (M21) (M23) drain electrode is connected, the 19th PMOS (M13), the 21st PMOS (M15), the 23rd PMOS (M20), 25 PMOSs (M22), the 26th PMOS (MK3), the source electrode of the 27th PMOS (MK4) connect supply voltage (VDD)。
The input differential signal comparator includes：Two comparators (COMP1, COMP2), i.e. first comparator COMP1 With the second comparator COMP2；Wherein, the positive input of the negative input end of first comparator (COMP1) and the second comparator (COMP2) Terminate input differential signal VINN (i.e. the first differential signal VINN), the positive input terminal of first comparator (COMP1) and the second ratio Compared with the negative input termination input differential signal VINP (i.e. the second differential signal VINP) of device (COMP2), first comparator (COMP1) The first control signal VC1 is exported, the second comparator (COMP2) exports the second control signal VC2.
The data-driven current branch includes：Second bias current sources (I2), the 3rd bias current sources (I3), the 30th NMOS tube (MS1), the 31st NMOS tube (MS2), the 32nd NMOS tube (MS3), the 33rd NMOS tube (MS4), the 3rd 14 NMOS tubes (MK1) and the 35th NMOS tube (MK2)；
Wherein, the second bias current sources (I2) negative pole and the 3rd bias current sources (I3) negative pole and supply voltage (VDD) phase Even, after the source electrode of the 30th NMOS tube (MS1) is connected with the source electrode of the 31st NMOS tube (MS2) again with the second bias current sources (I2) positive pole is connected, and the grid of the 30th NMOS tube (MS1) connects the first control signal VC1, the grid of the 31st NMOS tube (MS2) Pole meets the second control signal VC2, after the drain electrode of the 30th NMOS tube (MS1) is connected with the drain electrode of the 31st NMOS tube (MS2) The drain electrode with the 34th NMOS tube (MK1) is connected again, and the grid of the 34th NMOS tube (MK1) connects the 5th control word (EN1), The source electrode of 32nd NMOS tube (MS3) be connected with the source electrode of the 33rd NMOS tube (MS4) after again with the 3rd bias current sources (I3) positive pole is connected, and the grid of the 32nd NMOS tube (MS3) meets the first control signal VC1, the 33rd NMOS tube (MS4) Grid connects the second control signal VC2, the drain electrode of the 32nd NMOS tube (MS3) and the drain electrode phase of the 33rd NMOS tube (MS4) Lian Houzai is connected with the drain electrode of the 35th NMOS tube (MK2), and the grid of the 35th NMOS tube (MK2) connects the 6th control word (EN2), the source electrode of the 34th NMOS tube (MK1) and the source electrode of the 35th NMOS tube (MK2) and foregoing 14th NMOS tube (M1) drain electrode is connected.
Alternatively, the first comparator and the second comparator include：Comparator main circuit and bias current are adjustable Biasing circuit.
In embodiments of the present invention, Fig. 2 is the circuit diagram of comparator in the present invention.The main circuit of comparator is also using complementation Input loop structure, by transistor MK7, MK8, PC0a, PC0b, PC1a, PC1b, PC2a, PC2b, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, NC0, NC1a, NC1b, NC2a, NC2b, NC3, NC4, NC5, NC6, NC7, NC8, NC9, NC10 structure Into.According to different application demands, by the break-make of control word EN7, EN8 controlling transistor MK7, MK8, optionally by crystalline substance Body pipe PC0a or PC0b access circuit, to adjust the bias current of P input branch roads, change the opening threshold value of comparator.Transistor MC1、MC2、MC3、MC4、MC5、MC6、MC7、MC8、MC9、MC10、MC11、MC12、MC13、MC14、MC15、MC16、MC17、 MC18, MC19, MC20, MC21, MC22, MC23, MC24 form comparator offset main circuit.The bias current of comparator is by electric current Source IC1, IC2 is provided, according to different application demands, by the break-make of control word EN9, EN10 controlling transistor MK9, MK10, The size of adjustable comparator offset electric current, so as to adjust the speed of comparator.Pass through control word EN7, EN8, EN9, EN10 Set, the operation window of high current can be controlled.
The comparator main circuit includes：36th NMOS tube (NC1a), the 37th NMOS tube (NC1b), the 30th Eight NMOS tubes (NC2a), the 39th NMOS tube (NC2b), the 40th NMOS tube (NC0), the 41st NMOS tube (NC5), 42 NMOS tubes (NC6), the 43rd NMOS tube (NC7), the 44th NMOS tube (NC8), the 45th NMOS tube (NC3), the 46th NMOS tube (NC4), the 47th NMOS tube (NC9), the 48th NMOS tube (NC10), the 28th PMOS (PC5), the 29th PMOS (PC6), the 30th PMOS (PC7), the 31st PMOS (PC8), the 30th Two PMOSs (PC3), the 33rd PMOS (PC4), the 34th PMOS (PC9), the 35th PMOS (PC10), 36 PMOSs (PC1a), the 37th PMOS (PC1b), the 38th PMOS (PC2a), the 39th PMOS (PC2b), the 40th PMOS (PC0a), the 41st PMOS (PC0b), the 42nd PMOS (MK7) and the 43rd PMOS (MK8)；
Wherein, the 36th NMOS tube (NC1a), the grid of the 37th NMOS tube (NC1b) are all believed with input fully differential One of differential signal VCN (i.e. the 3rd differential signal VCN) in number is connected, the 38th NMOS tube (NC2a), the 30th The grid of nine NMOS tubes (NC2b) all (i.e. believe with another differential signal VCP in foregoing input fully differential signal by the 4th difference Number VCP) it is connected, the 40th NMOS tube (NC0) grid connects the 5th bias voltage (VCb1), source ground (GND), and drain electrode connects the 3rd 16 NMOS tubes (NC1a), the 37th NMOS tube (NC1b), the 38th NMOS tube (NC2a) and the 39th NMOS tube (NC2b) source electrode, the grid of the 28th PMOS (PC5) be connected with the grid of the 29th PMOS (PC6) after again with The drain electrode of 39 NMOS tubes (NC2b) is connected, the 28th PMOS (PC5), the 29th PMOS (PC6), the 30th The source electrode of PMOS (PC7) and the 31st PMOS (PC8) connects supply voltage (VDD), the grid of the 32nd PMOS (PC3) Pole is connected with the grid of the 33rd PMOS (PC4) is followed by the 6th bias voltage (VCb3), the 34th PMOS (PC9) Grid also connects the 6th bias voltage (VCb3), the 32nd PMOS after being connected with the grid of the 35th PMOS (PC10) (PC3) source electrode is connected with the drain electrode of the 29th PMOS (PC6), the source electrode and the 30th of the 33rd PMOS (PC4) The drain electrode of PMOS (PC7) is connected, the drain electrode of the 32nd PMOS (PC3) and the drain electrode phase of the 39th NMOS tube (NC2b) Even, the drain electrode of the 33rd PMOS (PC4) is connected with the drain electrode of the 37th NMOS tube (NC1b), the 34th PMOS (PC9) the drain electrode phase with the 28th PMOS (PC5) again after source electrode is connected with the drain electrode of the 36th NMOS tube (NC1a) Even, again with the 31st after the source electrode of the 35th PMOS (PC10) is connected with the drain electrode of the 38th NMOS tube (NC2a) The drain electrode of PMOS (PC8) is connected, the 36th PMOS (PC1a), the 37th PMOS (PC1b) grid all with input One of differential signal VCN (i.e. the 3rd differential signal VCN) in fully differential signal is connected, the 38th PMOS (PC2a), the grid of the 39th PMOS (PC2b) all with it is foregoing input fully differential signal in another differential signal VCP (i.e. the 4th differential signal VCP) is connected, and the grid of the 40th PMOS (PC0a) and the 41st PMOS (PC0b) connects the 7th Bias voltage (VCb4), the source electrode of the 40th PMOS (PC0a) connect the drain electrode of the 42nd PMOS (MK7), and the 41st The source electrode of PMOS (PC0b) connects the drain electrode of the 43rd PMOS (MK8), and the grid of the 42nd PMOS (MK7) connects the 7th Control word (EN7), the grid of the 43rd PMOS (MK8) connect the 8th control word (EN8), the 42nd PMOS (MK7) and The source electrode of 43rd PMOS (MK8) connects supply voltage (VDD), the 40th PMOS (PC0a) and the 41st PMOS (PC0b) drain electrode connects the 36th PMOS (PC1a), the 37th PMOS (PC1b), the 38th PMOS (PC2a) With the source electrode of the 39th PMOS (PC2b), the grid of the 41st NMOS tube (NC5) and the 42nd NMOS tube (NC6) Drain electrode after grid is connected again with the 39th PMOS (PC2b) is connected, the grid and the 4th of the 43rd NMOS tube (NC7) Drain electrode after the grid of 14 NMOS tubes (NC8) is connected again with the 37th PMOS (PC1b) is connected, the 41st NMOS tube (NC5) source ground of, the 42nd NMOS tube (NC6), the 43rd NMOS tube (NC7) and the 44th NMOS tube (NC8) (GND), the grid of the 45th NMOS tube (NC3) is connected with the grid of the 46th NMOS tube (NC4) is followed by the 8th biased electrical Press (VCb2), the grid of the 47th NMOS tube (NC9) also connects the 8th after being connected with the grid of the 48th NMOS tube (NC10) Bias voltage (VCb2), the source electrode of the 45th NMOS tube (NC3) are connected with the drain electrode of the 42nd NMOS tube (NC6), and the 4th The source electrode of 16 NMOS tubes (NC4) is connected with the drain electrode of the 43rd NMOS tube (NC7), the leakage of the 45th NMOS tube (NC3) Pole is connected with the drain electrode of the 39th PMOS (PC2b), drain electrode and the 37th PMOS of the 46th NMOS tube (NC4) (PC1b) drain electrode is connected, after the source electrode of the 47th NMOS tube (NC9) is connected with the drain electrode of the 36th PMOS (PC1a) The drain electrode with the 41st NMOS tube (NC5) is connected again, the source electrode and the 38th PMOS of the 48th NMOS tube (NC10) (PC2a) drain electrode after drain electrode is connected again with the 44th NMOS tube (NC8) is connected, the leakage of the 48th NMOS tube (NC10) Grid and the 31st PMOS with the 30th PMOS (PC7) again after the drain electrode of pole and the 35th PMOS (PC10) is connected The grid of pipe (PC8) is connected, and the 47th NMOS tube (NC9) is connected with the 34th PMOS (PC9) to be exported as comparator VCOUT。
The adjustable biasing circuit of bias current includes：4th bias current sources (IC1), the 5th bias current sources (IC2), the 49th NMOS tube (MC1), the 50th NMOS tube (MC2), the 51st NMOS tube (MC3), the 52nd NMOS Manage (MC4), the 53rd NMOS tube (MC8), the 54th NMOS tube (MC9), the 55th NMOS tube (MC10), the 56th NMOS tube (MC11), the 57th NMOS tube (MC16), the 58th NMOS tube (MC17), the 59th NMOS tube (MC18), 60th NMOS tube (MC23), the 61st NMOS tube (MC24), the 62nd NMOS tube (MK9), the 63rd NMOS tube (MK10), the 44th PMOS (MC5), the 45th PMOS (MC6), the 46th PMOS (MC7), the 47th PMOS (MC12), the 48th PMOS (MC13), the 49th PMOS (MC14), the 50th PMOS (MC15), 51 PMOSs (MC19), the 52nd PMOS (MC20), the 53rd PMOS (MC21) and the 54th PMOS (MC22)；
Wherein, the 4th bias current sources (IC1) negative pole and the 5th bias current sources (IC2) negative pole and supply voltage (VDD) It is connected, drain electrode and the 49th NMOS tube (MC1), the 50th NMOS tube (MC2), the 50th of the 49th NMOS tube (MC1) One NMOS tube (MC3), the 52nd NMOS tube (MC4), the 53rd NMOS tube (MC8), the 54th NMOS tube (MC9), 55 NMOS tubes (MC10) are connected with the grid of the 56th NMOS tube (MC11), the source electrode of the 49th NMOS tube (MC1) Drain electrode with the 50th NMOS tube (MC2) is connected, the source electrode and the 52nd NMOS tube (MC4) of the 51st NMOS tube (MC3) Drain electrode be connected, the source electrode of the 53rd NMOS tube (MC8) is connected with the drain electrode of the 54th NMOS tube (MC9), the 55th The source electrode of NMOS tube (MC10) is connected with the drain electrode of the 56th NMOS tube (MC11), the drain electrode of the 57th NMOS tube (MC16) Grid after being connected with grid again with the 58th NMOS tube (MC17) is connected, the source electrode of the 57th NMOS tube (MC16) and Source electrode after the drain electrode of 58 NMOS tubes (MC17) is connected again with the 59th NMOS tube (MC18) is connected, the 59th NMOS The grid of pipe (MC18) is connected with the grid of the 60th NMOS tube (MC23) again after being connected with drain electrode is used as the 8th bias voltage (VCb2), the drain electrode of the 60th NMOS tube (MC23) is connected with the grid of the 61st NMOS tube (MC24) is used as the 5th biased electrical Press (VCb1), the source electrode of the 60th NMOS tube (MC23) is connected with the drain electrode of the 61st NMOS tube (MC24), the 50th NMOS Manage (MC2), the 52nd NMOS tube (MC4), the 54th NMOS tube (MC9), the 56th NMOS tube (MC11), the 58th The source ground (GND) of NMOS tube (MC17), the 61st NMOS tube (MC24), the grid of the 44th PMOS (MC5) with Drain electrode after the grid of 45th PMOS (MC6) and drain electrode are connected again with foregoing 51st NMOS tube (MC3) is connected, the The source electrode of 44 PMOSs (MC5) be connected with the drain electrode of the 45th PMOS (MC6) after again with the 46th PMOS (MC7) source electrode is connected, the grid of the 46th PMOS (MC7) and drain electrode be connected after again with foregoing 53rd NMOS tube (MC8) drain electrode, which is connected, is used as the 6th bias voltage (VCb3), second bias voltage (Vb3) and the 47th PMOS (MC12), the grid of the 49th PMOS (MC14), the 51st PMOS (MC19) and the 53rd PMOS (MC21) It is connected, the drain electrode of the 47th PMOS (MC12) is connected with the drain electrode of foregoing 55th NMOS tube (MC10), and the 47th The source electrode of PMOS (MC12) is connected with the drain electrode of the 48th PMOS (MC13), the grid of the 48th PMOS (MC13) It is connected again with the drain electrode of the 47th PMOS (MC12) after being connected with the grid of the 50th PMOS (MC15) inclined as the 7th Put voltage (VCb4), the 4th bias voltage (Vb4) and the 52nd PMOS (MC20) and the 54th PMOS (MC22) Grid be connected, the source electrode of the 49th PMOS (MC14) is connected with the drain electrode of the 50th PMOS (MC15), the 49th The drain electrode of PMOS (MC14) is connected with the drain electrode of foregoing 57th NMOS tube (MC16), the 51st PMOS (MC19) Source electrode is connected with the drain electrode of the 52nd PMOS (MC20), the drain electrode and the foregoing 59th of the 51st PMOS (MC19) The drain electrode of NMOS tube (MC18) is connected, the source electrode of the 53rd PMOS (MC21) and the drain electrode of the 54th PMOS (MC22) It is connected, the drain electrode of the 53rd PMOS (MC21) is connected with the drain electrode of foregoing 60th NMOS tube (MC23), and the 45th PMOS (MC6), the 48th PMOS (MC13), the 50th PMOS (MC15), the 52nd PMOS (MC20), the 5th The source electrode of 14 PMOSs (MC22) connects supply voltage (VDD), the positive pole and the 62nd NMOS of the 4th bias current sources (IC1) The drain electrode of pipe (MK9) is connected, and the grid of the 62nd NMOS tube (MK9) connects the 9th control word (EN9), the 5th bias current sources (IC2) positive pole is connected with the drain electrode of the 63rd NMOS tube (MK10), and the grid of the 63rd NMOS tube (MK10) connects the tenth Control word (EN10), the source electrode of the 62nd NMOS tube (MK9) and the source electrode and the 49th of the 63rd NMOS tube (MK10) The drain electrode of NMOS tube (MC1) is connected.
Alternatively, the circularly folding operational transconductance amplifier circuit of N-type and the p-type Complementary input structure also includes：Common mode is anti- Current feed circuit；The common mode feedback circuit includes：Fully differential signal and common-mode signal input crystal pipe unit, voltage bias transistor Unit and common-mode feedback control signal generation unit.
In embodiments of the present invention, Fig. 3 is common mode feedback circuit connection figure.N-type transistor M25, M26, M27, M28 are common The input transistors of cmfb circuit, wherein transistor M25 grid connect fully differential output signal VOUTN, transistor M28 grid Pole meets another way fully differential output signal VOUTP, and transistor M26 and M27 grid meet input common mode voltage VCM.Transistor M29 Bias current is provided for input transistors, M29 and M30 grid meet bias voltage Vb1 with M30.Input transistors M25, M28 and M26, M27 voltage difference produce the common mode control signal in Fig. 1 used in OTA by transistor M31, M32 and series resistor R1, R2 VCMFB.VDD and GND can be respectively 2.5V and 0V supply voltage.
The fully differential signal includes with common-mode signal input crystal pipe unit：64th NMOS tube (M25), the 60th Five NMOS tubes (M26), the 66th NMOS tube (M27) and the 67th NMOS tube (M28)；
Wherein, the grid of the 64th NMOS tube (M25) connects the output difference signal VOUTN, the 67th NMOS tube (M28) grid connects another output difference signal VOUTP, the grid and the 66th of the 65th NMOS tube (M26) The grid of NMOS tube (M27), which is connected, is followed by input common mode voltage (VCM).
The voltage bias transistor unit includes：68th NMOS tube (M29) and the 69th NMOS tube (M30)；
Wherein, the drain electrode of the 68th NMOS tube (M29) and the source electrode and the 60th of the 64th NMOS tube (M25) The source electrode of five NMOS tubes (M26) is connected, drain electrode and the 66th NMOS tube (M27) of the 69th NMOS tube (M30) Source electrode and the source electrode of the 67th NMOS tube (M28) are connected, the grid and the 69th NMOS tube of the 68th NMOS tube (M29) (M30) grid is connected after being connected with first bias voltage (Vb1), the source electrode and the 6th of the 68th NMOS tube (M29) The source ground (GND) of 19 NMOS tubes (M30).
The common-mode feedback control signal generation unit includes：55th PMOS (M31), the 56th PMOS (M32) and two concatenation resistance, i.e., the first resistor R1 and second resistance R2 mutually concatenated；
Wherein, the grid of the 55th PMOS (M31) be connected with the grid of the 56th PMOS (M32) after and resistance R1 is connected with resistance R2 series side, the drain electrode of the 55th PMOS (M31) be connected with resistance R1 non-series side after again with The drain electrode of 64th NMOS tube (M25) is connected with the drain electrode of the 67th NMOS tube (M28) is followed by common mode control signal (VCMFB) after, the drain electrode of the 56th PMOS (M32) is connected with resistance R2 non-series side again with the 65th NMOS The drain electrode of pipe (M26) is connected with the drain electrode of the 66th NMOS tube (M27), the source electrode and the 5th of the 55th PMOS (M31) The source electrode of 16 PMOSs (M32) connects supply voltage (VDD).
The embodiment of the present invention includes：The N-type of interconnection and the circularly folding operational transconductance amplifier electricity of p-type Complementary input structure Road and the operational amplifier biasing circuit of data-driven；It is poor that the operational amplifier biasing circuit of the data-driven includes input Sub-signal comparator；The input differential signal comparator, for detecting input differential signal, and work as the input differential signal More than or equal to the input differential signal comparator opening threshold value when increasing circuit bias current, when the input difference When signal is less than the opening threshold value of the input differential signal comparator, the bias current of holding circuit will not become.Pass through the reality A scheme is applied, improves the speed of high performance switch condenser network, and reduces power consumption, improve yield, there is high speed, high line The advantages of property is spent.
Differential input signal is compared by the embodiment of the present invention by comparator (COMP1, COMP2), is closed for detecting Ring amplifier positive-negative input end (VINN, VINP) virtual earth state, the output level of comparator are used for control electric current source, such as comparator Output level controlling switch (MS1, MS2), bias current can be increased when differential input signal is larger, improve the speed of circuit Degree, and threshold value and comparator speed, control can be opened according to application demand dynamic adjustment amplifier current size, and comparator The operation window of high current processed.This circuit is applied to the larger switched-capacitor circuit of load capacitance, such as analog to digital conversion circuit, filtering Device etc., can improve the speed of circuit, and reduce power consumption, improve yield, meet different application demand by configuring, and meet integrated electricity The direction of the current research and development in road.
Although the embodiment disclosed by the embodiment of the present invention is as above, described content be only readily appreciate the present invention and The embodiment of use, is not limited to the embodiment of the present invention.Technical staff in any art of the embodiment of the present invention, On the premise of the spirit and scope disclosed by the embodiment of the present invention are not departed from, it can be appointed in the form and details of implementation What modification and change, but the scope of patent protection of the embodiment of the present invention, the model that must be still defined with appended claims Enclose and be defined.

Claims (10)

1. a kind of operational amplifier of data-driven, it is characterised in that the operational amplifier includes：The N-type and P of interconnection The circularly folding operational transconductance amplifier circuit of type Complementary input structure and the operational amplifier biasing circuit of data-driven；The number Include input differential signal comparator according to the operational amplifier biasing circuit of driving；
The input differential signal comparator, for detecting input differential signal, and when the input differential signal is more than or waited The bias current of increasing circuit when the opening threshold value of the input differential signal comparator, when the input differential signal is less than During the opening threshold value of the input differential signal comparator, the bias current of holding circuit will not become.
2. the operational amplifier of data-driven according to claim 1, it is characterised in that N-type and the p-type Complementary input structure Circularly folding operational transconductance amplifier circuit include：
N-type Complementary input structure differential pair unit and the N-type bias voltage crystal being connected with the N-type Complementary input structure differential pair unit Pipe unit, N-type biasing tail current transistor unit and N-type cascode transistors are to unit；And
P-type Complementary input structure differential pair unit and the p-type bias voltage crystal being connected with the p-type Complementary input structure differential pair unit Pipe unit, p-type biasing tail current transistor unit and p-type cascode transistors are to unit.
3. the operational amplifier of data-driven according to claim 2, it is characterised in that
The N-type Complementary input structure differential pair unit includes：First NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS Pipe；Wherein, the grid of first NMOS tube and second NMOS tube connects the first difference in the input differential signal Signal VINN；The grid of 3rd NMOS tube and the 4th NMOS tube connects the second difference in the input differential signal Signal VINP；
The N-type voltage bias transistor unit includes：5th NMOS tube；The grid and the first biased electrical of 5th NMOS tube Pressure is connected, source ground, drain electrode and the source electrode of first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube It is connected.
4. the operational amplifier of data-driven according to claim 3, it is characterised in that
The p-type Complementary input structure differential pair unit includes：9th PMOS, the tenth PMOS, the 11st PMOS and the 12nd PMOS；Wherein, the grid of the 9th PMOS and the tenth PMOS meets the first differential signal VINN；It is described The grid of 11st PMOS and the 12nd PMOS meets the second differential signal VINP；
The p-type biasing tail current transistor unit includes：First PMOS, the second PMOS, the 3rd PMOS and the 4th PMOS；Wherein, after the grid of first PMOS is connected with the grid of second PMOS again with the 4th NMOS The drain electrode of pipe is connected, the grid of the 3rd PMOS be connected with the grid of the 4th PMOS after again with the 2nd NMOS The drain electrode of pipe is connected, first PMOS, second PMOS, the source of the 3rd PMOS and the 4th PMOS Pole is connected with supply voltage；
The p-type cascode transistors include to unit：5th PMOS, the 6th PMOS, the 7th PMOS and the 8th PMOS；Wherein, the grid of the 5th PMOS be connected with the grid of the 6th PMOS after with the second bias voltage phase Even；The grid of 7th PMOS is also connected after being connected with the grid of the 8th PMOS with second bias voltage； The source electrode of 5th PMOS is connected with the drain electrode of second PMOS, the source electrode and the described 3rd of the 6th PMOS The drain electrode of PMOS is connected, and the drain electrode of the 5th PMOS is connected with the drain electrode of the 4th NMOS tube, the 6th PMOS The drain electrode of pipe is connected with the drain electrode of second NMOS tube, the source electrode of the 7th PMOS and the drain electrode of first NMOS tube Drain electrode after being connected again with first PMOS is connected, the source electrode of the 8th PMOS and the drain electrode of the 3rd NMOS tube Drain electrode after being connected again with the 4th PMOS is connected；
The p-type voltage bias transistor unit includes：13rd PMOS；The grid of 13rd PMOS and common mode control Signal processed is connected, and source electrode is connected with the supply voltage, drain electrode and the 9th PMOS, the tenth PMOS, described the 11 PMOSs are connected with the source electrode of the 12nd PMOS.
5. the operational amplifier of data-driven according to claim 4, it is characterised in that
The N-type biasing tail current transistor unit includes：6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube and the 9th NMOS tube；The grid of wherein described 6th NMOS tube be connected with the grid of the 7th NMOS tube after again with the 12nd PMOS The drain electrode of pipe is connected, the grid of the 8th NMOS tube be connected with the grid of the 9th NMOS tube after again with the tenth PMOS The drain electrode of pipe is connected, the 6th NMOS tube, the 7th NMOS tube, the source of the 8th NMOS tube and the 9th NMOS tube Pole is grounded；
The N-type cascode transistors include to unit：Tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube and 13 NMOS tubes；Wherein, biased after the grid of the tenth NMOS tube is connected with the grid of the 11st NMOS tube with the 3rd Voltage is connected, the grid of the 12nd NMOS tube be connected with the grid of the 13rd NMOS tube after also with the described 3rd biasing Voltage is connected, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the 7th NMOS tube, the source of the 11st NMOS tube Pole is connected with the drain electrode of the 8th NMOS tube, the drain electrode of the tenth NMOS tube and the drain electrode phase of the 12nd PMOS Even, the drain electrode of the 11st NMOS tube is connected with the drain electrode of the tenth PMOS, the source electrode of the 12nd NMOS tube and Drain electrode again with the 6th NMOS tube is connected after the drain electrode of 9th PMOS is connected, the source electrode of the 13rd NMOS tube Drain electrode again with the 9th NMOS tube is connected after drain electrode with the 11st PMOS is connected.
6. the operational amplifier of data-driven according to claim 5, it is characterised in that
The drain electrode of 7th PMOS is connected with the drain electrode of the 12nd NMOS tube exports the first output difference signal VOUTP, the drain electrode of the 8th PMOS is connected with the drain electrode of the 13rd NMOS tube exports the second output difference signal VOUTN, the first output difference signal VOUTP and the second output difference signal VOUTN collectively form fully differential output Signal.
7. the operational amplifier of data-driven according to claim 1 or 5, it is characterised in that the fortune of the data-driven Calculating amplifier bias circuit includes：Bias-voltage generating circuit, input differential signal comparator and data driving current branch road.
8. the operational amplifier of data-driven according to claim 7, it is characterised in that
The bias-voltage generating circuit includes：First bias current sources, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, 22 NMOS tubes, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, second 17 NMOS tubes, the 28th NMOS tube, the 29th NMOS tube, the 14th PMOS, the 15th PMOS, the 16th PMOS Pipe, the 17th PMOS, the 18th PMOS, the 19th PMOS, the 20th PMOS, the 21st PMOS, the 20th Two PMOSs, the 23rd PMOS, the 24th PMOS, the 25th PMOS, the 26th PMOS and the 20th Seven PMOSs；
Wherein, the first bias current sources negative pole is connected with the supply voltage, the first bias current sources positive pole and institute State the 14th NMOS tube drain electrode be connected after again with the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the tenth Seven NMOS tubes, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube are connected with the grid of the 21st NMOS tube, institute The source electrode for stating the 14th NMOS tube is connected with the drain electrode of the 15th NMOS tube, the source electrode of the 16th NMOS tube with it is described The drain electrode of 17th NMOS tube is connected, and the source electrode of the 18th NMOS tube is connected with the drain electrode of the 19th NMOS tube, institute The source electrode for stating the 20th NMOS tube is connected with the drain electrode of the 21st NMOS tube, the drain electrode of the 22nd NMOS tube and Grid after grid is connected again with the 23rd NMOS tube and the 24th NMOS tube is connected, and the described 22nd The source electrode of NMOS tube be connected with the drain electrode of the 23rd NMOS tube and the 24th NMOS tube after again with described second The source electrode of 15 NMOS tubes is connected, and the source electrode of the 23rd NMOS tube is connected with the drain electrode of the 28th NMOS tube, The source electrode of 24th NMOS tube is connected with the drain electrode of the 29th NMOS tube, the grid of the 28th NMOS tube Pole connects the first control word, and the grid of the 29th NMOS tube connects the second control word, the grid of the 25th NMOS tube It is connected again with the grid of the 26th NMOS tube as the 3rd bias voltage, the 26th NMOS after being connected with drain electrode The drain electrode of pipe is connected with the grid of the 27th NMOS tube as first bias voltage, the 26th NMOS tube Source electrode be connected with the drain electrode of the 27th NMOS tube, the 15th NMOS tube, the 17th NMOS tube, the 19th NMOS The source ground of pipe, the 21st NMOS tube, the 27th NMOS tube, the 28th NMOS tube and the 29th NMOS tube, institute State the grid and drain electrode and the grid of the 15th PMOS and the grid phase of the 16th PMOS of the 14th PMOS Lian Houzai is connected with the drain electrode of the 16th NMOS tube, source electrode and the 15th PMOS of the 14th PMOS Source electrode after drain electrode and the drain electrode of the 16th PMOS are connected again with the 17th PMOS is connected, and the described 15th The source electrode of PMOS is connected with the drain electrode of the 26th PMOS, the source electrode of the 16th PMOS and the 27th PMOS Drain electrode be connected, the grid of the 26th PMOS connects the 3rd control word, and the grid of the 27th PMOS connects Four control words, the grid of the 17th PMOS and drain electrode are connected conduct with the drain electrode of the 18th NMOS tube again after being connected Second bias voltage, second bias voltage and the 18th PMOS, the 20th PMOS, the 22nd PMOS Pipe is connected with the grid of the 24th PMOS, the drain electrode of the 18th PMOS and the drain electrode phase of the 20th NMOS tube Even, the source electrode of the 18th PMOS is connected with the drain electrode of the 19th PMOS, the grid of the 19th PMOS It is connected again with the drain electrode of the 18th PMOS after being connected with the grid of the 21st PMOS and is used as the 4th biased electrical Pressure, the 4th bias voltage are connected with the grid of the 23rd PMOS and the 25th PMOS, and the described 20th The source electrode of PMOS is connected with the drain electrode of the 21st PMOS, the drain electrode and the described 20th of the 20th PMOS The drain electrode of two NMOS tubes is connected, and the source electrode of the 22nd PMOS is connected with the drain electrode of the 23rd PMOS, institute The drain electrode for stating the 22nd PMOS is connected with the drain electrode of the 25th NMOS tube, the source electrode of the 24th PMOS Drain electrode with the 25th PMOS is connected, drain electrode and the 26th NMOS tube of the 24th PMOS Drain electrode is connected, the 19th PMOS, the 21st PMOS, the 23rd PMOS, the 25th PMOS, the 20th Six PMOSs, the source electrode of the 27th PMOS connect the supply voltage；
The input differential signal comparator includes：First comparator and the second comparator；Wherein, the first comparator is negative The positive input of input and second comparator terminates the first differential signal VINN, the positive input of the first comparator The negative input of end and second comparator terminates the second differential signal VINP, the control of first comparator output first Signal VC1, second comparator export the second control signal VC2；
The data-driven current branch includes：Second bias current sources, the 3rd bias current sources, the 30th NMOS tube, the 3rd 11 NMOS tubes, the 32nd NMOS tube, the 33rd NMOS tube, the 34th NMOS tube and the 35th NMOS tube；
Wherein, the second bias current sources negative pole and the 3rd bias current sources negative pole are connected with the supply voltage, institute State the 30th NMOS tube source electrode be connected with the source electrode of the 31st NMOS tube after again with second bias current sources just Extremely it is connected, the grid of the 30th NMOS tube meets the first control signal VC1, and the grid of the 31st NMOS tube connects The second control signal VC2, the drain electrode of the 30th NMOS tube be connected with the drain electrode of the 31st NMOS tube after again Drain electrode with the 34th NMOS tube is connected, and the grid of the 34th NMOS tube connects the 5th control word, described The source electrode of 32nd NMOS tube be connected with the source electrode of the 33rd NMOS tube after again with the 3rd bias current sources just Extremely it is connected, the grid of the 32nd NMOS tube connects the first control signal VC1, the grid of the 33rd NMOS tube The second control signal VC2 is met, the drain electrode of the 32nd NMOS tube is connected with the drain electrode of the 33rd NMOS tube The drain electrode again with the 35th NMOS tube is connected afterwards, and the grid of the 35th NMOS tube connects the 6th control word, described The source electrode of 34th NMOS tube and the source electrode of the 35th NMOS tube are connected with the drain electrode of the 14th NMOS tube.
9. the operational amplifier of data-driven according to claim 8, it is characterised in that the first comparator and second Comparator includes：Comparator main circuit and the adjustable biasing circuit of bias current；
The comparator main circuit includes：36th NMOS tube, the 37th NMOS tube, the 38th NMOS tube, the 30th Nine NMOS tubes, the 40th NMOS tube, the 41st NMOS tube, the 42nd NMOS tube, the 43rd NMOS tube, the 44th NMOS tube, the 45th NMOS tube, the 46th NMOS tube, the 47th NMOS tube, the 48th NMOS tube, the 28th PMOS, the 29th PMOS, the 30th PMOS, the 31st PMOS, the 32nd PMOS, the 33rd PMOS Pipe, the 34th PMOS, the 35th PMOS, the 36th PMOS, the 37th PMOS, the 38th PMOS Pipe, the 39th PMOS, the 40th PMOS, the 41st PMOS, the 42nd PMOS and the 43rd PMOS；
Wherein, the 36th NMOS tube, the 37th NMOS tube grid with the 3rd in the input differential signal Differential signal VCN is connected, the 38th NMOS tube, the 39th NMOS tube grid with the input differential signal The 4th differential signal VCP be connected, the 40th NMOS tube grid connects the 5th bias voltage, source ground, and drain electrode connects described 36th NMOS tube, the 37th NMOS tube, the source electrode of the 38th NMOS tube and the 39th NMOS tube, the described 20th Drain electrode phase with the 39th NMOS tube again after the grid of eight PMOSs is connected with the grid of the 29th PMOS Even, the source electrode of the 28th PMOS, the 29th PMOS, the 30th PMOS and the 31st PMOS connects power supply Voltage, the grid of the 32nd PMOS is connected with the grid of the 33rd PMOS is followed by the 6th bias voltage, The grid of 34th PMOS also connects the 6th bias voltage after being connected with the grid of the 35th PMOS, The source electrode of 32nd PMOS is connected with the drain electrode of the 29th PMOS, the source of the 33rd PMOS Pole is connected with the drain electrode of the 30th PMOS, drain electrode and the 39th NMOS tube of the 32nd PMOS Drain electrode is connected, and the drain electrode of the 33rd PMOS is connected with the drain electrode of the 37th NMOS tube, and the described 34th Drain electrode again with the 28th PMOS is connected after the source electrode of PMOS is connected with the drain electrode of the 36th NMOS tube, The source electrode of 35th PMOS be connected with the drain electrode of the 38th NMOS tube after again with the 31st PMOS The drain electrode of pipe is connected, the grid of the 36th PMOS and the 37th PMOS all with the 3rd differential signal VCN It is connected, the grid of the 38th PMOS and the 39th PMOS is connected with the 4th differential signal VCP, described The grid of 40th PMOS and the 41st PMOS connects the 7th bias voltage, and the source electrode of the 40th PMOS connects described The drain electrode of 42nd PMOS, the source electrode of the 41st PMOS connects the drain electrode of the 43rd PMOS, described The grid of 42nd PMOS connects the 7th control word, and the grid of the 43rd PMOS connects the 8th control word, and described The source electrode of 42 PMOSs and the 43rd PMOS connects the supply voltage, the 40th PMOS and the 41st The drain electrode of PMOS meets the 36th PMOS, the 37th PMOS, the 38th PMOS and the 39th PMOS The source electrode of pipe, the grid of the 41st NMOS tube be connected with the grid of the 42nd NMOS tube after again with the described 3rd The drain electrode of 19 PMOSs is connected, after the grid of the 43rd NMOS tube is connected with the grid of the 44th NMOS tube The drain electrode with the 37th PMOS is connected again, the 41st NMOS tube, the 42nd NMOS tube, the 43rd The source ground of NMOS tube and the 44th NMOS tube, grid and the 46th NMOS tube of the 45th NMOS tube Grid be connected and be followed by the 8th bias voltage, the grid of the 47th NMOS tube and the grid of the 48th NMOS tube Also the 8th bias voltage, the source electrode of the 45th NMOS tube and the drain electrode of the 42nd NMOS tube are connect after being connected It is connected, the source electrode of the 46th NMOS tube is connected with the drain electrode of the 43rd NMOS tube, the 45th NMOS The drain electrode of pipe is connected with the drain electrode of the 39th PMOS, the drain electrode and the described 37th of the 46th NMOS tube The drain electrode of PMOS is connected, the source electrode of the 47th NMOS tube be connected with the drain electrode of the 36th PMOS after again with The drain electrode of 41st NMOS tube is connected, the source electrode of the 48th NMOS tube and the leakage of the 38th PMOS Drain electrode after being extremely connected again with the 44th NMOS tube is connected, the drain electrode and the described 30th of the 48th NMOS tube The drain electrode of five PMOSs is connected with the grid of the 30th PMOS and the grid of the 31st PMOS again after being connected, 47th NMOS tube is connected with the 34th PMOS as comparator output VCOUT；
The adjustable biasing circuit of bias current includes：4th bias current sources, the 5th bias current sources, the 49th NMOS Pipe, the 50th NMOS tube, the 51st NMOS tube, the 52nd NMOS tube, the 53rd NMOS tube, the 54th NMOS tube, 55th NMOS tube, the 56th NMOS tube, the 57th NMOS tube, the 58th NMOS tube, the 59th NMOS tube, 60 NMOS tubes, the 61st NMOS tube, the 62nd NMOS tube, the 63rd NMOS tube, the 44th PMOS, the 40th Five PMOSs, the 46th PMOS, the 47th PMOS, the 48th PMOS, the 49th PMOS, the 50th PMOS, the 51st PMOS, the 52nd PMOS, the 53rd PMOS and the 54th PMOS；
Wherein, the 4th bias current sources negative pole and the 5th bias current sources negative pole are connected with the supply voltage, institute State drain electrode and the 49th NMOS tube, the 50th NMOS tube, the 51st NMOS tube, the 50th of the 49th NMOS tube Two NMOS tubes, the 53rd NMOS tube, the 54th NMOS tube, the grid phase of the 55th NMOS tube and the 56th NMOS tube Even, the source electrode of the 49th NMOS tube is connected with the drain electrode of the 50th NMOS tube, the 51st NMOS tube Source electrode is connected with the drain electrode of the 52nd NMOS tube, source electrode and the 54th NMOS of the 53rd NMOS tube The drain electrode of pipe is connected, and the source electrode of the 55th NMOS tube is connected with the drain electrode of the 56th NMOS tube, and the described 5th Grid after the drain and gate of 17 NMOS tubes is connected again with the 58th NMOS tube is connected, the 57th NMOS Source electrode again with the 59th NMOS tube is connected after the drain electrode of the source electrode of pipe and the 58th NMOS tube is connected, described The grid of 59th NMOS tube is connected inclined as the described 8th with the grid of the 60th NMOS tube again after being connected with drain electrode Voltage is put, the drain electrode of the 60th NMOS tube is connected with the grid of the 61st NMOS tube is used as the 5th biased electrical Pressure, the source electrode of the 60th NMOS tube are connected with the drain electrode of the 61st NMOS tube, the 50th NMOS tube, the 5th 12 NMOS tubes, the 54th NMOS tube, the 56th NMOS tube, the 58th NMOS tube, the source electrode of the 61st NMOS tube Ground connection, the grid of the grid of the 44th PMOS and the 45th PMOS and draining be connected after again with described the The drain electrode of 51 NMOS tubes is connected, and the source electrode of the 44th PMOS is connected with the drain electrode of the 45th PMOS The source electrode again with the 46th PMOS is connected afterwards, the grid of the 46th PMOS and drain electrode be connected after again with institute The drain electrode for stating the 53rd NMOS tube is connected as the 6th bias voltage, second bias voltage and the described 47th PMOS, the 49th PMOS, the 51st PMOS are connected with the grid of the 53rd PMOS, and the described 47th The drain electrode of PMOS is connected with the drain electrode of the 55th NMOS tube, the source electrode and the described 4th of the 47th PMOS The drain electrode of 18 PMOSs is connected, the grid of the 48th PMOS be connected with the grid of the 50th PMOS after again Drain electrode with the 47th PMOS is connected as the 7th bias voltage, the 4th bias voltage and the described 5th 12 PMOSs are connected with the grid of the 54th PMOS, source electrode and the 50th PMOS of the 49th PMOS The drain electrode of pipe is connected, and the drain electrode of the 49th PMOS is connected with the drain electrode of the 57th NMOS tube, and the described 5th The source electrode of 11 PMOSs is connected with the drain electrode of the 52nd PMOS, the drain electrode of the 51st PMOS with it is described The drain electrode of 59th NMOS tube is connected, the source electrode and the drain electrode phase of the 54th PMOS of the 53rd PMOS Even, the drain electrode of the 53rd PMOS is connected with the drain electrode of the 60th NMOS tube, the 45th PMOS, the 48 PMOSs, the 50th PMOS, the 52nd PMOS, the source electrode of the 54th PMOS connect the supply voltage, The positive pole of 4th bias current sources is connected with the drain electrode of the 62nd NMOS tube, the grid of the 62nd NMOS tube Pole connects the 9th control word, and the positive pole of the 5th bias current sources is connected with the drain electrode of the 63rd NMOS tube, and described The grid of 63 NMOS tubes connects the tenth control word, the source electrode and the 63rd NMOS of the 62nd NMOS tube The source electrode of pipe is connected with the drain electrode of the 49th NMOS tube.
10. the operational amplifier of data-driven according to claim 8, it is characterised in that N-type and the p-type complementation is defeated The circularly folding operational transconductance amplifier circuit entered also includes：Common mode feedback circuit；The common mode feedback circuit includes：Fully differential Signal and common-mode signal input crystal pipe unit, voltage bias transistor unit and common-mode feedback control signal generation unit；
The fully differential signal includes with common-mode signal input crystal pipe unit：64th NMOS tube, the 65th NMOS tube, 66th NMOS tube, the 67th NMOS tube；
Wherein, the grid of the 64th NMOS tube meets the second output difference signal VOUTN, the 67th NMOS The grid of pipe connects the first output difference signal VOUTP, the grid and the described 66th of the 65th NMOS tube The grid of NMOS tube, which is connected, is followed by input common mode voltage VCM；
The voltage bias transistor unit includes：68th NMOS tube and the 69th NMOS tube；
Wherein, source electrode and six ten five NMOS of the drain electrode of the 68th NMOS tube with the 64th NMOS tube The source electrode of pipe is connected, the drain electrode of the 69th NMOS tube and the source electrode and the described 67th of the 66th NMOS tube The source electrode of NMOS tube is connected, after the grid of the 68th NMOS tube is connected with the grid of the 69th NMOS tube and institute State the first bias voltage to be connected, the source electrode of the 68th NMOS tube and the source ground of the 69th NMOS tube；
The common-mode feedback control signal generation unit includes：55th PMOS, the 56th PMOS and mutual string The first resistor R1 and second resistance R2 connect；
Wherein, it is electric with described first after the grid of the 55th PMOS is connected with the grid of the 56th PMOS Resistance R1 is connected with second resistance R2 series side, and the drain electrode of the 55th PMOS concatenates with the non-of first resistor R1 End is connected with the drain electrode of the 64th NMOS tube and the drain electrode of the 67th NMOS tube again after being connected, and after being connected Common mode control signal VCMFB is met, after the drain electrode of the 56th PMOS is connected with the non-series side of the second resistance R2 It is connected again with the drain electrode of the 65th NMOS tube and the drain electrode of the 66th NMOS tube, the source of the 55th PMOS Pole and the source electrode of the 56th PMOS connect the supply voltage.
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