CN102035486A - Complementary input circular folded transconductance operational amplifier with preamplifier - Google Patents
Complementary input circular folded transconductance operational amplifier with preamplifier Download PDFInfo
- Publication number
- CN102035486A CN102035486A CN 201010621165 CN201010621165A CN102035486A CN 102035486 A CN102035486 A CN 102035486A CN 201010621165 CN201010621165 CN 201010621165 CN 201010621165 A CN201010621165 A CN 201010621165A CN 102035486 A CN102035486 A CN 102035486A
- Authority
- CN
- China
- Prior art keywords
- pipe
- nmos
- drain electrode
- pmos
- nmos pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a complementary input circular folded transconductance operational amplifier with a preamplifier, which belongs to the technical field of operational amplifiers. The transconductance operational amplifier is characterized by comprising a preamplifier which consists of N type transistors (N5, N1, N2, N3, N4), wherein complementary input is performed by P type transistors (P1, P2, P4, P3) and N type transistors (N16, N17, N19, N18) and the unit gain bandwidth of the transconductance operational amplifier is increased by a circular folded transconductance operational amplifier structure. A circuit has the characteristics of high unit gain bandwidth and low power consumption and is accordant with the current research and development directions of integrated circuits.
Description
Technical field
The invention belongs to the VLSI (very large scale integrated circuit) designs in Microelectronics and Solid State Electronics field, relate to a kind of novel transconductance amplifier circuit, can be used for analog to digital conversion circuit, the design of analog signal processing circuits such as filter.
Background technology
The present invention relates to design such as the contour performance switched-capacitor circuit of high-speed AD converter high speed operational transconductance amplifier.Operational amplifier is one of most important module of a lot of analog circuits, is widely used in analog to digital conversion circuit, in the analog signal processing circuits such as filter.Usually the indexs such as precision, speed and power consumption that the high performance switch condenser network can reach have been determined.In switched-capacitor circuit, load is generally pure capacitive properties, and this moment, single-stage operation transconductance amplifier OTA was better than multistage operational amplifier.Therefore, traditional collapsible OTA amplifier has obtained to use widely.But traditional collapsible OTA has shortcomings such as speed is slow, power consumption is big.
At above-mentioned situation, the present invention proposes a kind of loop collapsing operation transconductance amplifier that has prime amplifier and complementary input.
Summary of the invention
In order to overcome the existing deficiency that collapsible OTA speed is slow, power consumption is big, the present invention has designed the loop collapsing operation transconductance amplifier of the complementation input that has prime amplifier.The object of the invention is to improve the unity gain bandwidth GBW of OTA, with the operating rate of raising operational amplifier, and the power consumption of reduction OTA.Use the present invention, can improve speed, perhaps reduce power consumption such as high-performance analog to digital converter, the contour performance switching capacity of filter.
The invention is characterized in
Contain: the prime amplifier circuit, complementary input circuit of P type and the voltage bias transistor that connected thereof to part, N type biasing tail current transistor part and cascode transistors to part, complementary input circuit of N type and the N type voltage bias transistor part that is connected thereof, P type biasing tail current transistor part and tribute mountain, park transistor are to part, wherein:
The prime amplifier circuit, contain: a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4 and the 5th NMOS pipe N5, wherein:
The source class ground connection of described the 5th NMOS pipe N5, grid meets the N type first bias voltage Vbn1;
The grid of the grid of described NMOS pipe N1 and the 2nd NMOS pipe N2 meets fully differential signal VINN and VINP successively separately, connects the grid of described the 5th NMOS pipe N5 after the source class of a NMOS pipe N1, the 2nd NMOS pipe N2 is connected with each other again;
Described the 3rd NMOS pipe N3, the 4th NMOS pipe N4 grid each other meets N type zero offset voltage Vbn0 after linking to each other, drain electrode meets power vd D after linking to each other each other, the source class of the 3rd NMOS pipe N3 links to each other with the drain electrode of NMOS pipe N1, and the source class of the 4th NMOS pipe N4 links to each other with the drain electrode of the 2nd NMOS pipe N4;
The complementary input of P type branch road, contain: a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3 and the 4th PMOS pipe P4, connect the drain electrode of described the 2nd NMOS pipe N2 after the gate interconnection of the one PMOS pipe P1 and the 2nd PMOS pipe P2, connect the drain electrode of NMOS pipe N1 after the gate interconnection of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4;
The described P type voltage bias transistor part that links to each other with the complementary input of P type branch road, the source class of the 5th PMOS pipe P5 meets described supply voltage VDD in addition, and grid meets the P type first bias voltage Vbp1, and drain electrode and described first to the 4th totally four PMOS pipe P1, P2, P3, the source class of P4 links to each other;
The N type bias current transistor part that links to each other with the complementary branch road of described P type, contain: the 6th NMOS manages N6, the 7th NMOS manages N7, the 8th NMOS pipe N8 and the 9th NMOS pipe N9, wherein, described the 6th to the 9th NMOS pipe N6, N7, N8, the source class interconnection ground connection of N9, the described the 6th to the 7th totally two NMOS pipe N6, connect the drain electrode of described the 3rd PMOS pipe P3 after the gate interconnection of N7, the described the 8th, the 9 two NMOS pipe N8 connects the drain electrode of described the 2nd PMOS pipe P2 after the gate interconnection of N9, the drain electrode of described the 6th NMOS pipe N6 connects the drain electrode of PMOS pipe P1, and the drain electrode of described the 9th NMOS pipe N9 connects the drain electrode of the 4th PMOS pipe P4;
The cascode transistors of the complementary input of the described P type branch road that links to each other with the complementary branch road of described P type is to part, contain: the tenth NMOS manages N10, the 11 NMOS manages N11, the 12 NMOS manages N12, the 13 NMOS manages N13, the 14 NMOS pipe N14 and the 15 NMOS pipe N15, wherein, described the 12 NMOS pipe N12, meet the N type second bias voltage Vbn2 after both gate interconnect of the 13 NMOS pipe N13, described the tenth NMOS pipe N10, meet the described N type second bias voltage Vbn2 after both gate interconnection of the 11 NMOS pipe N11, described the 14 NMOS pipe N14, after linking to each other, both grids of the 15 NMOS pipe N15 meet N type the 3rd bias voltage Vbn3, the drain electrode of described the 12 NMOS pipe N12 connects the drain electrode of described the 3rd PMOS pipe P3, the drain electrode of the 12 NMOS pipe N12 connects the drain electrode of described the 3rd PMOS pipe P3, the source class of the 12 NMOS pipe N12 connects the drain electrode of described the 7th NMOS pipe N7, the drain electrode of described the 13 NMOS pipe N13 connects the drain electrode of described the 2nd PMOS pipe P2, the source class of the 13 NMOS pipe N13 connects the drain electrode of described the 8th NMOS pipe N8, the source class of described the tenth NMOS pipe N10 connects the drain electrode of described the 6th NMOS pipe N6, the source class of described the 11 NMOS pipe N11 connects the drain electrode of described the 9th NMOS pipe N9, the drain electrode of described the tenth NMOS pipe P10 connects the source class of the 14 NMOS pipe N14, the source class of described the 11 NMOS pipe N11 connects the drain electrode that described the 9th NMOS closes N9, and the drain electrode that the tenth NMOS closes N11 connects the source class that the 14 NMOS manages N15;
The complementary input of N type branch road, contain: four NMOS pipes that source class links to each other, be expressed as: the 16 NMOS pipe N16, the 17 NMOSN17 pipe, the 18 NMOS pipe N18 and the 19 NMOS pipe N19, wherein, be connected the drain electrode that meets described the 2nd NMOS pipe N2 after described both gate interconnection of the 16 NMOS pipe N16, the 17 NMOS pipe N17, connect the drain electrode of described NMOS pipe N1 after both gate interconnection of the 18 NMOS pipe N18, the 19 NMOS pipe N19;
With the voltage bias transistor part that the complementary input of described N type branch road links to each other, be the 20 NMOS pipe N20, source class ground connection, grid meets common mode control signal VCMFB, and drain electrode is total to four NMOS pipe N16, N17 with the described the 16 to the 19, N18, the source class of N19 links to each other;
Biasing tail current transistor part with the complementary branch road of described N type links to each other, contain: the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 8th PMOS pipe P8 and the 9th PMOS pipe P9 meet described supply voltage VDD after the source class interconnection separately;
The cascode transistors that links to each other with the complementary input of described N type branch road is to part, contain: the tenth PMOS manages P10, the 11 PMOS manages P11, the 12 PMOS pipe P12 and the 13 PMOS pipe P13, the 14 PMOS pipe P15 and the 15 PMOS pipe P15, wherein, described the tenth PMOS pipe P10, after linking to each other, both grids of the 11 PMOS pipe P11 meet the P type second bias voltage Vbp2, described the 12 PMOS pipe P12, after linking to each other, both grids of the 13 PMOS pipe P13 meet the described P type second bias voltage Vbp2, the source class of the tenth PMOS pipe P10 connects the drain electrode of the 6th PMOS pipe P6, the source class of the 11 PMOS pipe P11 connects the drain electrode of the 9th PMOS pipe P9, the source class of the 12 PMOS pipe P12 connects the drain electrode of the 7th PMOS pipe P7, the source class of the 13 PMOS pipe P13 connects the drain electrode of the 8th PMOS pipe P8, the drain electrode of the 12 PMOS pipe P12 is connected to the described the 6th simultaneously, the 7 two PMOS pipe P6, the drain electrode of the grid of P7 and described the 18 NMOS pipe N18, the drain electrode of the 13 PMOS pipe P13 receives the described the 8th simultaneously, the 9th PMOS manages P8, the drain electrode of the grid of P9 and described the 17 NMOS pipe N17, the described the 14, the 15 PMOS pipe P14, meet P type the 3rd bias voltage Vbp3 after the gate interconnection of P15, after linking to each other, the drain electrode of the drain electrode of the 14 PMOs pipe P14 and described the 14 NMOS pipe N14 meets the 3rd fully differential signal VOUTP, after linking to each other, the drain electrode of the drain electrode of the 15 PMOS pipe P15 and described the 15 NMOS pipe N15 meets the 4th fully differential signal VOUTN, the source class of the 14 PMOS pipe P14 links to each other with the drain electrode of the tenth PMOS pipe P10, and the source class of the 15 PMOS pipe P15 links to each other with the drain electrode of the 11 PMOS pipe P11.
The invention has the beneficial effects as follows: carry out SPICE emulation at the CADENCE platform, simulation result shows that at the 3pF capacitive load, unity gain bandwidth is 2500MHz, DC current gain 88dB.
Description of drawings
Fig. 1. the present invention has the circuit diagram of loop collapsing operation transconductance amplifier of the complementation input of prime amplifier
Embodiment
Contain two complementary input branch roads of N type and P type and wherein each input voltage bias transistor that branch road was connected part, biasing tail current transistor part and cascode transistors to part, the prime amplifier circuit, wherein:
The complementary input of P type branch road, contain: a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3 and the 4th PMOS pipe P4, wherein: the grid of the grid of PMOS pipe P1, the 2nd PMOS pipe P2 all links to each other with the VN node, and the grid of the grid of the 3rd PMOS pipe P3, the 4th PMOS pipe P4 all links to each other with the VP node;
The 5th PMOS transistor P5 is that the complementary input of P type branch road constitutes P type biasing tail current transistor part, wherein: the grid of the 5th PMOS transistor P5 meets the first bias voltage Vbp1, the drain electrode of the 5th PMOS transistor P5 links to each other with the source electrode of a PMOS transistor P1, the source electrode of the 2nd PMOS transistor P2, the source electrode of the 3rd PMOS transistor P3 and the source electrode of the 4th PMOS transistor P4 simultaneously, the source electrode of the 5th PMOS transistor P5 meets supply voltage VDD
Four NMOS pipes altogether of the one NMOS pipe N6, the 2nd NMOS pipe N7, the 3rd NMOS pipe N8, the 4th NMOS pipe N9 have been formed the N type biasing tail current transistor part of the complementary input of described P type branch road, wherein: link to each other with the drain electrode of described the 3rd PMOS pipe P3 again after the grid of the grid of NMOS pipe N6 and the 2nd NMOS pipe N7 links to each other, link to each other with the drain electrode that described the 2nd PMOS manages P2 again after the grid that the grid of the 3rd NMOS pipe N8 and the 4th NMOS manage N9 links to each other; The 5th NMOS manages N1O, the 6th NMOS manages N11, the 7th NMOS manages N12, the 8th NMOS manages N13, the 9th NMOS manages N14, these six NMOS pipes of the tenth NMOS pipe N15 have constituted the cascode transistors of the complementary input of described P type branch road jointly to part, wherein: the source electrode of the 5th NMOS pipe N10 is managed the drain electrode of P1 simultaneously with a described PMOS, the drain electrode of the one NMOS pipe N6 links to each other, the source electrode of the 6th NMOS pipe N11 is managed the drain electrode of P4 simultaneously with described the 4th PMOS, the drain electrode of the 4th NMOS pipe N9 connects, the source electrode of the 7th NMOS pipe N12 links to each other with the drain electrode of described the 2nd NMOS pipe N7, the source electrode of the 8th NMOS pipe N13 links to each other with the drain electrode of described the 3rd NMOS pipe N8, the drain electrode of the 7th NMOS pipe N12 links to each other with the drain electrode of affiliated the 3rd PMOS pipe P3, the drain electrode of the 8th NMOS pipe N13 links to each other with the drain electrode of described the 2nd PMOS pipe P2, meet the second bias voltage Vbn2 after the gate interconnection of the grid of the 7th NMOS pipe N12 and the 8th NMOS pipe N13, after linking to each other, the grid of the grid of the 5th nmos pass transistor N10 and the 6th nmos pass transistor N11 also meets the second bias voltage Vbn2, the source electrode of the 9th NMOS pipe N14 links to each other with the drain electrode of described the 5th NMOS pipe N10, the source electrode of the tenth NMOS pipe N15 links to each other with the drain electrode of described the 6th NMOS pipe N11, also meets the second bias voltage Vbn3 after the grid of the grid of the 9th nmos pass transistor N14 and the tenth nmos pass transistor N15 links to each other;
The complementary input circuit of N type, contain: the nmos pass transistor of four source electrode interconnection: the 11 NMOS pipe N16, the 12 NMOS pipe N17, the 13 NMOS pipe N18, the 14 NMOS manage N19, wherein: the grid of these two NMOS pipes of the 11 NMOS pipe N16, the 12 NMOS pipe N17 all is connected to described VN node, and the grid of these two NMOS pipes of the 13 NMOS pipe N18, the 14 NMOS pipe N19 all is connected to described VP node; The voltage bias transistor part is made of the 15 NMOS pipe N20, and the source ground of the 15 nmos pass transistor N20, grid meet common mode control signal VCMFB, and drain electrode links to each other with the source electrode of described four NMOS pipe.
Biasing tail current transistor part is made of these four PMOS pipes of the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 9th PMOS pipe P9, wherein: the described the 6th to the 9th the source electrode of totally four PMOS pipes P6, P7, P8, P9 all link described supply voltage VDD; Cascode transistors is managed P10 to part by the tenth PMOS, the 11 PMOS manages P11, the 12 PMOS manages P12, the 13 PMOS pipe P13 constitutes, the 14 PMOS manages P14, the 15 PMOS pipe P15 constitutes, wherein: the grid of the tenth PMOS pipe P10, the grid of the 11 PMOS transistor P11, the grid of 12 PMOS transistor N20 and the grid of the 13 PMOS transistor P13 all meet the 3rd bias voltage Vbp2, the source electrode while of the tenth PMOS transistor P10 and the source electrode of the 6th PMOS transistor P6, the drain electrode of the 11 nmos pass transistor N16 links to each other, the source electrode while of the 11 PMOS transistor P11 and the drain electrode of the 9th PMOS transistor P9, the drain electrode of the 14 nmos pass transistor N19 links to each other, the source electrode of the 14 PMOS transistor P14 links to each other with the drain electrode of the tenth PMOS transistor P10 simultaneously, the source electrode of the 15 PMOS transistor P15 links to each other with the drain electrode of the 11 PMOS transistor P11 simultaneously, the grid of the 14 PMOS transistor P14 and the grid of the 15 PMOS transistor P15 all meet the 4th bias voltage Vbp3, the drain electrode of the 12 PMOS pipe P12 links to each other with the drain electrode of the 7th PMOS pipe P7, drain electrode links to each other the source electrode of the 13 PMOS pipe P13 with the 8th PMOS pipe P8 simultaneously, in addition, after the gate interconnection of the grid of the 6th PMOS transistor P6 and the 7th PMOS transistor P7 again with the drain electrode of the 12 PMOS transistor P12, the drain electrode of the 13 NMOS pipe N18 links to each other, after the gate interconnection of the grid of the 8th PMOS transistor P8 and the 9th PMOS transistor P9 again with the drain electrode of the 13 PMOS transistor P13, the drain electrode interconnection of the tenth bi-NMOS transistor N17, the drain electrode of the drain electrode of described the 14 PMOS pipe P14 and the 9th NMOS pipe N14 links to each other and exports differential signal VOUTP, the 15 PMOS pipe P15 links to each other with the drain electrode of the tenth NMOS pipe N15, export another differential signal VOUTN, these two differential signals of described VOUTP and VOUTN constitute fully differential output jointly;
The prime amplifier circuit, contain the 16 NMOS pipe N1, contain the 17 NMOS pipe N2, contain the 18 NMOS pipe N5, contain the 19 NMOS pipe N3, contain the 20 NMOS pipe N4, the grid of the 16 NMOS pipe N1 all links to each other with a VINN differential signal in two fully differential signals of input, the grid of the 17 NMOS pipe N2 all links to each other with another VINP differential signal in two fully differential signals of described input, the 18 nmos pass transistor N5 is that prime amplifier constitutes biasing tail current transistor part, the grid of the 18 nmos pass transistor N5 meets the 5th bias voltage Vbn1, the drain electrode while of the 18 nmos pass transistor N5 and the source electrode of the 16 nmos pass transistor N1, the source electrode of the 17 nmos pass transistor N2 links to each other, described the 18 NMOS pipe N3, described supply voltage VDD is all linked in the drain electrode of the 19 NMOS pipe N4, the grid of the 19 nmos pass transistor N3 and the grid of the 20 nmos pass transistor N4 all meet the 5th bias voltage Vbn0, the source electrode of the 19 NMOS pipe N3 links to each other with the drain electrode of the 16 NMOS pipe N1, and be connected to node VP, the source electrode of the 20 NMOS pipe N4 links to each other with the drain electrode of the 17 NMOS pipe N2, and is connected to node VN.
Technical solution of the present invention is consulted Fig. 1.Fig. 1 is a loop collapsing operation transconductance amplifier that has the complementation input of prime amplifier, different with conventional OTA, the prime amplifier that it has adopted N type metal-oxide-semiconductor to constitute, possess the complementary input of N type metal-oxide-semiconductor and P type metal-oxide-semiconductor branch road, and two branch roads have all adopted the loop collapsing OTA structure of being reported in the article " The Recycling Folded Cascode:A General Enhancement of the Folded Cascode Amplifier " of the 9th volume 2535-2542 page or leaf September in 2009 at IEEE solid-state circuit magazine by Rida S.Assaad and Jose Silva-Martinez.
Transistor N5, N1, N2, N3, N4 constitute prime amplifier among Fig. 1, and transistor P1, P2, P4, P3 are P type entering apparatus, and N16, N17, N19, N18 are N type entering apparatus.VP, VN are the fully differential input signal, prime amplifier output VINP, VINN, and VINP is added to the grid of P4, P3 and N19, N18, and VINN is added to the grid of P1, P2 and N16, N17.Transistor P5 provides bias current for P type input branch road P1, P2, P4, P3, and N20 provides bias current for N type input branch road N16, N17, N19, N18.Meanwhile, N20 provides a path, with the signal VCMFB control common mode component by producing in common mode feedback circuit.Transistor N6, N7 and N9, N8 are the biasing tail current transistor of P input branch, and N10, N11, N12, N13 and N14, N15 are that the cascode transistors of P input branch is right.Transistor P6, P7 and P9, P8 are the biasing tail current transistor of N input branch.P10, P11, P12, P13 and P14, P15 are that the cascode transistors of N input branch is right.VOUTP and VOUTN are fully differential output.Vbn0 is the bias voltage of transistor N3, N4, and Vbp1 is the bias voltage of transistor P5, and Vpb2 is the bias voltage of transistor P10, P11, P12, P13.Vbn2 is the bias voltage of transistor N10, N11, N12, N13.Vpb3 is the bias voltage of transistor P14, P15.Vbn3 is the bias voltage of transistor N14, N15.VDD and GND have the supply voltage of 2.5V and 0V respectively.
The circularly folding operational transconductance amplifier that the present invention has the complementation input of prime amplifier has increased N type prime amplifier, N type entering apparatus branch road, and cascode transistors N10, the N11 of N type entering apparatus branch road and P type entering apparatus branch road and P10, P11 shared identical electric current.The electric current of each branch road that has therefore utilized more fully effectively raises the unity gain bandwidth GBW of amplifier, improving the speed of amplifier.
In order to verify performance, carry out SPICE emulation at the CADENCE platform.
Simulation result shows that under the 3pF capacitive load, unity gain bandwidth is 2500MHz.
Table 1:OTA characteristic is summed up
The characteristic of OTA is summed up as table 1.
Claims (1)
1. the circularly folding operational transconductance amplifier that has prime amplifier and complementary input, it is characterized in that, contain the prime amplifier circuit, complementary input circuit of P type and the voltage bias transistor that connected thereof to part, N type biasing tail current transistor part and cascode transistors to part, complementary input circuit of N type and the N type voltage bias transistor part that is connected thereof, P type biasing tail current transistor part and tribute mountain, park transistor are to part, wherein:
The prime amplifier circuit, contain: NMOS pipe (N1), the 2nd NMOS pipe (N2), the 3rd NMOS pipe (N3), the 4th NMOS pipe (N4) and the 5th NMOS pipe (N5), wherein:
The source class ground connection of described the 5th NMOS pipe (N5), grid connects N type first bias voltage (Vbn1);
The grid of the grid of described NMOS pipe (N1) and the 2nd NMOS pipe (N2) connects fully differential signal (VINN) and (VINP) successively separately, connects the grid that described the 5th NMOS manages (N5) again after the source class of NMOS pipe (N1), the 2nd NMOS pipe (N2) is connected with each other;
Described the 3rd NMOS pipe (N3), the 4th NMOS pipe (N4) grid each other connect N type zero offset voltage (Vbn0) after linking to each other, drain electrode connects power supply (VDD) after linking to each other each other, the source class of the 3rd NMOS pipe (N3) links to each other with the drain electrode that a NMOS manages (N1), and the source class of the 4th NMOS pipe (N4) links to each other with the drain electrode that the 2nd NMOS manages (N4);
The complementary input of P type branch road, contain: PMOS pipe (P1), the 2nd PMOS pipe (P2), the 3rd PMOS pipe (P3) and the 4th PMOS pipe (P4), connect the drain electrode of described the 2nd NMOS pipe (N2) after the gate interconnection of the one PMOS pipe (P1) and the 2nd PMOS pipe (P2), connect the drain electrode of NMOS pipe (N1) after the gate interconnection of the 3rd PMOS pipe (P3) and the 4th PMOS pipe (P4);
The described P type voltage bias transistor part that links to each other with the complementary input of P type branch road, the source class of the 5th PMOS pipe (P5) connects described supply voltage (VDD) in addition, grid connects P type first bias voltage (Vbp1), and drain electrode and described first to the 4th totally four PMOS pipe (P1, P2, P3, source class P4) links to each other;
The N type bias current transistor part that links to each other with the complementary branch road of described P type, contain: the 6th NMOS manages (N6), the 7th NMOS manages (N7), the 8th NMOS pipe (N8) and the 9th NMOS pipe (N9), wherein, described the 6th to the 9th NMOS pipe (N6, N7, N8, N9) source class interconnection ground connection, the described the 6th to the 7th totally two NMOS pipe (N6, N7) connect the drain electrode of described the 3rd PMOS pipe (P3) after the gate interconnection, the described the 8th, the 9 two NMOS pipe (N8, N9) connect the drain electrode of described the 2nd PMOS pipe (P2) after the gate interconnection, the drain electrode of described the 6th NMOS pipe (N6) connects the drain electrode of PMOS pipe (P1), and the drain electrode of described the 9th NMOS pipe (N9) connects the drain electrode of the 4th PMOS pipe (P4);
The cascode transistors of the complementary input of the described P type branch road that links to each other with the complementary branch road of described P type is to part, contain: the tenth NMOS manages (N10), the 11 NMOS manages (N11), the 12 NMOS manages (N12), the 13 NMOS manages (N13), the 14 NMOS pipe (N14) and the 15 NMOS pipe (N15), wherein, described the 12 NMOS pipe (N12), connect N type second bias voltage (Vbn2) after the 13 NMOS pipe (N13) both gate interconnect, described the tenth NMOS pipe (N10), connect described N type second bias voltage (Vbn2) after the 11 NMOS pipe (N11) both gate interconnection, described the 14 NMOS pipe (N14), after linking to each other, the 15 NMOS pipe (N15) both grids connect N type the 3rd bias voltage (Vbn3), the drain electrode of described the 12 NMOS pipe (N12) connects the drain electrode of described the 3rd PMOS pipe (P3), the drain electrode of the 12 NMOS pipe (N12) connects the drain electrode of described the 3rd PMOS pipe (P3), the source class of the 12 NMOS pipe (N12) connects the drain electrode of described the 7th NMOS pipe (N7), the drain electrode of described the 13 NMOS pipe (N13) connects the drain electrode of described the 2nd PMOS pipe (P2), the source class of the 13 NMOS pipe (N13) connects the drain electrode of described the 8th NMOS pipe (N8), the source class of described the tenth NMOS pipe (N10) connects the drain electrode of described the 6th NMOS pipe (N6), the source class of described the 11 NMOS pipe (N11) connects the drain electrode of described the 9th NMOS pipe (N9), the drain electrode of described the tenth NMOS pipe (P10) connects the source class of the 14 NMOS pipe (N14), the source class of described the 11 NMOS pipe (N11) connects the drain electrode that described the 9th NMOS closes (N9), and the drain electrode that the tenth NMOS closes (N11) connects the source class that the 14 NMOS manages (N15);
The complementary input of N type branch road, contain: four NMOS pipes that source class links to each other, be expressed as: the 16 NMOS pipe (N16), the 17 NMOS (N17) pipe, the 18 NMOS pipe (N18) and the 19 NMOS pipe (N19), wherein, be connected the drain electrode that connects described the 2nd NMOS pipe (N2) after described the 16 NMOS pipe (N16), the 17 NMOS pipe (N17) both gate interconnection, connect the drain electrode of described NMOS pipe (N1) after the 18 NMOS pipe (N18), the 19 NMOS pipe (N19) both gate interconnection;
With the voltage bias transistor part that the complementary input of described N type branch road links to each other, be the 20 NMOS pipe (N20), source class ground connection, grid connects common mode control signal (VCMFB), and drain electrode is total to four NMOS pipe (N16, N17 with the described the 16 to the 19, N18, source class N19) links to each other;
Biasing tail current transistor part with the complementary branch road of described N type links to each other, contain: the 6th PMOS pipe (P6), the 7th PMOS pipe (P7), the 8th PMOS pipe (P8) and the 9th PMOS pipe (P9) connect described supply voltage (VDD) after the source class interconnection separately;
The cascode transistors that links to each other with the complementary input of described N type branch road is to part, contain: the tenth PMOS manages (P10), the 11 PMOS manages (P11), the 12 PMOS pipe (P12) and the 13 PMOS pipe (P13), the 14 PMOS pipe (P15) and the 15 PMOS pipe (P15), wherein, described the tenth PMOS pipe (P10), after linking to each other, the 11 PMOS pipe (P11) both grids connect P type second bias voltage (Vbp2), described the 12 PMOS pipe (P12), after linking to each other, the 13 PMOS pipe (P13) both grids connect described P type second bias voltage (Vbp2), the source class of the tenth PMOS pipe (P10) connects the drain electrode of the 6th PMOS pipe (P6), the source class of the 11 PMOS pipe (P11) connects the drain electrode of the 9th PMOS pipe (P9), the source class of the 12 PMOS pipe (P12) connects the drain electrode of the 7th PMOS pipe (P7), the source class of the 13 PMOS pipe (P13) connects the drain electrode of the 8th PMOS pipe (P8), the drain electrode of the 12 PMOS pipe (P12) is connected to the described the 6th simultaneously, the 7 two PMOS pipe (P6, the drain electrode of grid P7) and described the 18 NMOS pipe (N18), the drain electrode of the 13 PMOS pipe (P13) receives the described the 8th simultaneously, the 9th PMOS manages (P8, the drain electrode of grid P9) and described the 17 NMOS pipe (N17), the described the 14, the 15 PMOS pipe (P14, P15) connect P type the 3rd bias voltage (Vbp3) after the gate interconnection, after linking to each other, the drain electrode that the drain electrode of the 14 PMOs pipe (P14) and described the 14 NMOS manage (N14) connects the 3rd fully differential signal (VOUTP), after linking to each other, the drain electrode that the drain electrode of the 15 PMOS pipe (P15) and described the 15 NMOS manage (N15) connects the 4th fully differential signal (VOUTN), the source class of the 14 PMOS pipe (P14) links to each other with the drain electrode that the tenth PMOS manages (P10), and the source class of the 15 PMOS pipe (P15) links to each other with the drain electrode of the 11 PMOS pipe (P11).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010621165 CN102035486A (en) | 2010-12-24 | 2010-12-24 | Complementary input circular folded transconductance operational amplifier with preamplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010621165 CN102035486A (en) | 2010-12-24 | 2010-12-24 | Complementary input circular folded transconductance operational amplifier with preamplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102035486A true CN102035486A (en) | 2011-04-27 |
Family
ID=43887922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010621165 Pending CN102035486A (en) | 2010-12-24 | 2010-12-24 | Complementary input circular folded transconductance operational amplifier with preamplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102035486A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105913120A (en) * | 2016-04-08 | 2016-08-31 | 北京大学深圳研究生院 | Transconductance operation amplification circuit and cell nerve network |
| CN107528557A (en) * | 2017-09-07 | 2017-12-29 | 清华大学 | A kind of operational amplifier of data-driven |
| CN107579713A (en) * | 2017-09-29 | 2018-01-12 | 清华大学 | A kind of new operational transconductance amplifier circuit |
| WO2020159586A1 (en) | 2019-01-28 | 2020-08-06 | Intel Corporation | Low voltage class ab operational trans-conductance amplifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321370A (en) * | 1992-05-14 | 1994-06-14 | Nec Corporation | Operational amplifier with common-mode feedback amplifier circuit |
| CN101741328A (en) * | 2009-12-16 | 2010-06-16 | 清华大学 | Complementary input circularly folding operational transconductance amplifier |
-
2010
- 2010-12-24 CN CN 201010621165 patent/CN102035486A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321370A (en) * | 1992-05-14 | 1994-06-14 | Nec Corporation | Operational amplifier with common-mode feedback amplifier circuit |
| CN101741328A (en) * | 2009-12-16 | 2010-06-16 | 清华大学 | Complementary input circularly folding operational transconductance amplifier |
Non-Patent Citations (1)
| Title |
|---|
| 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 20090930 Rida S. Assaad et al The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier 第2535-2536页 1 第44卷, 第9期 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105913120A (en) * | 2016-04-08 | 2016-08-31 | 北京大学深圳研究生院 | Transconductance operation amplification circuit and cell nerve network |
| CN105913120B (en) * | 2016-04-08 | 2018-03-20 | 北京大学深圳研究生院 | Operational transconductance amplifying circuit and cell neural network |
| CN107528557A (en) * | 2017-09-07 | 2017-12-29 | 清华大学 | A kind of operational amplifier of data-driven |
| CN107528557B (en) * | 2017-09-07 | 2021-03-02 | 清华大学 | Data-driven operational amplifier |
| CN107579713A (en) * | 2017-09-29 | 2018-01-12 | 清华大学 | A kind of new operational transconductance amplifier circuit |
| WO2020159586A1 (en) | 2019-01-28 | 2020-08-06 | Intel Corporation | Low voltage class ab operational trans-conductance amplifier |
| EP3918711A4 (en) * | 2019-01-28 | 2022-10-12 | INTEL Corporation | Low voltage class ab operational trans-conductance amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101741328A (en) | Complementary input circularly folding operational transconductance amplifier | |
| CN101741329B (en) | Complementary input circularly folding gain bootstrap operational transconductance amplifier | |
| US9634685B2 (en) | Telescopic amplifier with improved common mode settling | |
| CN107315441B (en) | A kind of on piece low pressure difference linear voltage regulator with fast transient response | |
| CN110289838B (en) | Comparator and analog-to-digital converter | |
| CN102176659B (en) | Transconductance-enhanced recovery current folded MOS (metal oxide semiconductor) transistor cascade amplifier | |
| CN102075151A (en) | Complementary circulation folding gain bootstrapping operational amplifier circuit with preamplifier | |
| TW201112618A (en) | Balun amplifier | |
| CN102176658B (en) | Symmetrically-folded MOS (metal oxide semiconductor) transistor cascade amplifier with broadband and low-power consumption | |
| CN102035486A (en) | Complementary input circular folded transconductance operational amplifier with preamplifier | |
| CN103219951A (en) | Low-power consumption and low-noise amplifier adopting noise cancellation technology | |
| CN109120243A (en) | Clock driver circuit | |
| Ahmed et al. | An improved recycling folded cascode amplifier with gain boosting and phase margin enhancement | |
| CN102098014A (en) | Complementary circularly-folded gain bootstrap transconductance operation amplifier with preamplifier | |
| CN106849938B (en) | Input buffer circuit | |
| WO2022027750A1 (en) | Comparator and analog-to-digital converter | |
| CN102158188B (en) | Low-power consumption bandwidth-multiplying operational amplifier realized by metal oxide semiconductor (MOS) devices | |
| CN101860334B (en) | Operational transconductance amplifier (OTA) of circulating current for separating AC path from DC patch path | |
| CN102355212A (en) | Rail-to-rail input stage with current compensation function | |
| CN104980112B (en) | The circular form Folded-cascode amplifier of consumption high gain | |
| CN106059516A (en) | Rail-to-rail operational amplifier circuit, ADC converter, DCDC converter and power amplifier | |
| CN107528557A (en) | A kind of operational amplifier of data-driven | |
| Kai et al. | A 168 dB high gain folded cascode operational amplifier for Delta-Sigma ADC | |
| Chunfeng et al. | A wide-band feedback amplifier based on a new operational current amplifier in 130nm CMOS | |
| CN104218907A (en) | Bulk-driven low-voltage rail-to-rail operational amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110427 |