CN106849938B - Input buffer circuit - Google Patents
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- CN106849938B CN106849938B CN201611208519.4A CN201611208519A CN106849938B CN 106849938 B CN106849938 B CN 106849938B CN 201611208519 A CN201611208519 A CN 201611208519A CN 106849938 B CN106849938 B CN 106849938B
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Abstract
The invention provides an input buffer circuit which comprises a comparator circuit and a level conversion circuit, wherein the comparator circuit comprises a rail-to-rail folding type cascode circuit, the rail-to-rail folding type cascode circuit is used for realizing differential input, the level conversion circuit is used for converting an auxiliary power supply into a kernel power supply and outputting a logic level signal to the interior of a chip according to a detection signal of the rail-to-rail folding type cascode circuit. The comparator circuit adopts the rail-to-rail folding type cascode circuit, the rail-to-rail folding type cascode circuit can realize differential input, the common mode and common difference voltage in a wide range are realized, and the problem that the conventional input buffer circuit is limited by the comparator circuit and can only support the input range of the common mode and differential mode voltage is solved.
Description
Technical Field
The present invention relates to the Field of FPGA (Programmable logic device) digital clocks, and in particular, to an input buffer circuit for an FPGA.
Background
In high performance chip ICs such as FPGAs, input/output module structures (IO) can be designed to be programmed according to specific I/O interface standards required by users, including output driving capability, output slew rate, input types and the like, so that the same input/output module can support multiple I/O interface standards.
The programmable input buffer is an important module in the structure of the input/output module, a specific input interface standard can be accurately selected by programming the programmable input buffer, and the traditional input/output modules such as CMOS, TTL and the like are adopted to mainly support interface standards such as LVCMOS, LVTTL, PCI33, PCI66 and the like at lower speed.
With the higher requirements for low power consumption, faster and more accurate transmission rate, and the continuous reduction of process size, new I/O standards are continuously generated, such as LVPECL, HSTL _ I/II/III/IV (1.2V to 1.8V), SSTL _ I/II (2.5V to 1.8V), and high-speed serial data transmission standards LVDS _25, lvdnext _25, HT _25, etc., at this time, the conventional input/output module cannot meet the requirements for high-speed signal transmission. A conventional differential signal receiver includes a comparator circuit and a level shifter circuit, where the level shifter circuit converts an external IO power supply into a core power supply and outputs a logic high or logic low level.
As shown in fig. 1 and fig. 2, the conventional comparator circuit is implemented by using NMOS differential input pair transistors or PMOS differential input pair transistors, and when the conventional comparator circuit is applied to a high-speed single-ended input standard (an input voltage is higher than a reference voltage and is logic "high", and vice versa, and the reference voltage VREF is logic "low", and is equivalent to an inverted reference level), the conventional comparator circuit can only implement high-speed single-ended standards with reference voltages higher than 0.7V and lower than 0.7V, such as GTL (VREF ═ 0.8V), HSTL _ I _12(VREF ═ 0.6V); when the differential input circuit is applied to differential input standards, only a limited common-mode input range can be supported; in addition, a single NMOS or PMOS differential comparator has smaller output resistance, and the transconductance changes along with the change of an input common mode, so that the gain changes along with the input, and the minimum differential mode voltage (precision) which can be identified is limited; the two-stage open-loop comparator has lower pole frequency under the condition of low slew rate, has larger transmission delay, and needs large bias current under the condition of high slew rate, thereby introducing larger parasitic capacitance and power consumption.
Disclosure of Invention
The invention provides an input buffer circuit for an FPGA (field programmable gate array), which at least solves the problem that the existing input buffer circuit can only support a limited voltage common mode input range.
The present invention provides an input buffer circuit, comprising: a comparator circuit and a level conversion circuit; the comparator circuit comprises a rail-to-rail folding type cascode circuit, and the rail-to-rail folding type cascode circuit is used for realizing differential input; the level conversion circuit is used for converting the auxiliary power supply into an inner core power supply and outputting a logic level signal to the inside of the chip according to a detection signal of the rail-to-rail folding type cascode circuit.
Further, the comparator circuit comprises two rail-to-rail folded cascode circuits; the two rail-to-rail folding type cascode circuits are used for realizing differential input and differential output of the comparator, widening the input range of a common mode signal and a differential mode signal and improving the voltage gain.
Furthermore, the level conversion circuit is a fully differential circuit and comprises an input circuit, a load circuit and an output circuit, wherein the input circuit adopts NMOS transistors to realize differential input, the load circuit adopts transistors connected with a cross-coupled current source and a diode as loads and is used for carrying out delayed amplification on the detected differential signals, and the output circuit is used for adjusting the current driving capability according to the load requirements of the output circuit, further amplifying and shaping the output signals of the load circuit and outputting logic level signals.
Further, the output circuit is implemented by an active current mirror circuit using PMOS as a differential input pair.
Further, the output circuit is implemented by an active current mirror circuit using NMOS as a differential input pair.
Furthermore, the level conversion circuit is a double-input single-output level conversion circuit, and the comparator circuit comprises two rail-to-rail folding type cascode circuits; the two rail-to-rail folding type cascode circuits are used for realizing differential input and differential output, and the double-input single-output level conversion circuit comprises a differential input circuit and a differential-to-single-end output circuit and is used for realizing differential input and single-end output.
Furthermore, the level conversion circuit is a single-input single-output circuit, and the comparator circuit comprises a rail-to-rail folding type cascode circuit, so that differential input and single-end output are realized.
Furthermore, the auxiliary power supply is the same as the core power supply, the comparator circuit directly adopts the core power supply as the power supply of the rail-to-rail folding type cascode circuit, and the detection signal is directly output to the inside of the chip by shaping of the output buffer OUTBUF without passing through a level conversion circuit.
Further, the rail-to-rail folding type cascode circuit comprises an NMOS input differential pair transistor, a PMOS input differential pair transistor and a cascode current source composed of the NMOS and the PMOS as an output load.
Furthermore, the rail-to-rail folding type cascode circuit further comprises a bias voltage difference generating circuit, and the bias voltage generating circuit is used for generating a bias voltage and outputting the bias voltage to the cascode current source.
The invention has the beneficial effects that:
the invention provides an input buffer circuit, wherein a comparator circuit adopts a rail-to-rail folding type cascode circuit, the rail-to-rail folding type cascode circuit can realize differential input, the common mode and common difference voltage in a wide range is realized, and the problem that the conventional input buffer circuit can only support the limited common mode and differential mode voltage input range due to the comparator circuit is solved.
Drawings
FIG. 1 is a circuit diagram of a prior art NMOS differential input pair comparator;
FIG. 2 is a circuit diagram of a prior art PMOS differential input pair comparator;
FIG. 3 is a schematic diagram of an input buffer circuit according to a first embodiment of the present invention;
FIG. 4 is a circuit diagram of a dual-input dual-output input buffer circuit according to a second embodiment of the present invention;
FIG. 5 is a circuit diagram of a transmission gate according to a second embodiment of the present invention;
FIG. 6 is a circuit diagram of a dual-input single-output input buffer circuit according to a second embodiment of the present invention;
FIG. 7 is another circuit diagram of a dual-input single-output input buffer circuit according to a second embodiment of the present invention;
FIG. 8 is another circuit diagram of a level shifter circuit according to a second embodiment of the present invention;
fig. 9 is another circuit diagram of an output circuit in a level shifter circuit according to a second embodiment of the present invention.
Detailed Description
The invention will now be further explained by means of embodiments in conjunction with the accompanying drawings.
The first embodiment:
fig. 3 is a schematic structural diagram of an input buffer circuit according to a first embodiment of the present invention, and it can be seen from fig. 3 that, in this embodiment, the input buffer circuit according to the present invention includes: a comparator circuit 31 and a level conversion circuit 32; the comparator circuit 31 includes a rail-to-rail folded cascode circuit for implementing differential input; the level conversion circuit 32 is configured to convert an auxiliary power supply such as an external input/output interface power supply into a core power supply, and output a logic level signal to the inside of the chip according to a detection signal of the rail-to-rail folded cascode circuit.
In some embodiments, the comparator circuit 31 in the above embodiments comprises two rail-to-rail folded cascode circuits; the two rail-to-rail folding type cascode circuits are used for realizing differential input and differential output of the comparator and widening the input range of a common-mode signal and a differential-mode signal.
As shown in fig. 4, in some embodiments, the level shift circuit 32 in the above embodiments is a fully differential circuit, and includes an input circuit (M1, M2), a load circuit (M3, M4, M6, M7) and an output circuit (M8-M15), where the input circuit uses NMOS transistors to implement differential input, the load circuit uses cross-coupled current sources and diode-connected transistors as loads to perform hysteresis amplification on the detected differential signal, and the output circuit is used to adjust the current driving capability according to the load requirement of the output circuit, further amplify and shape the output signal of the load circuit, and output a logic level signal.
In some embodiments, the output circuit in the above embodiments is implemented by an active current mirror circuit using PMOS as a differential input pair, as shown in fig. 4.
In some embodiments, the output circuit in the above embodiments is implemented by an active current mirror circuit using PMOS as a differential input pair, as shown in fig. 4.
In some embodiments, as shown in fig. 9, the output circuit in the above embodiments is implemented by an active current mirror circuit using NMOS as a differential input pair, and in this case, the level shift circuit shown in fig. 4 needs to be improved.
In some embodiments, the level shift circuit in the above embodiments is a dual-input single-output level shift circuit, and the comparator circuit includes two rail-to-rail folded cascode circuits; the two rail-to-rail folding type cascode circuits are used for realizing differential input and differential output, and the double-input single-output level conversion circuit comprises a differential input circuit and a differential-to-single-end output circuit and is used for realizing differential input and single-end output.
In some embodiments, as shown in fig. 6, the level shift circuit in the above embodiments is a single-input single-output circuit, and the comparator circuit includes a rail-to-rail folded cascode circuit.
As shown in fig. 7, in some embodiments, the auxiliary power supply in the above embodiments is the same as the core power supply, the comparator circuit directly uses the core power supply as a power supply of the rail-to-rail folded cascode circuit, and the detection signal is directly output to the inside of the chip by using OUTBUF shaping without passing through the level conversion circuit.
As shown in fig. 4, in some embodiments, the rail-to-rail folded cascode circuit in the above embodiments includes NMOS and PMOS input differential pair transistors, and a cascode current source composed of NMOS and PMOS as an output load.
As shown in fig. 4, in some embodiments, the rail-to-rail folded cascode circuit in the above embodiments further includes a bias voltage difference circuit (i.e., the transmission gate circuit, the P14 transistor and the corresponding control signals and circuits in the dashed line frame of fig. 4, which outputs a bias voltage VB), and the bias voltage difference circuit is configured to generate a bias voltage output to the cascode current source.
Correspondingly, the invention provides a programmable logic device which is provided with the input buffer circuit provided by the invention.
The present invention will now be further explained with reference to specific application scenarios.
Second embodiment:
the embodiment provides a differential input buffer circuit which is applied to an FPGA chip, can support a wide common-mode input range and a wide differential-mode input range, and supports high speed and low propagation delay, and comprises two working voltages, namely a kernel working power supply VCCINT and an auxiliary power supply VCCAUX.
The differential input buffer adopts rail-to-rail folding type cascode differential input differential output as a comparator, supports a common mode input range from the ground to the power supply voltage, and supports a differential mode input range from dozens of mV to the power supply voltage; the comparator circuit adopts fully differential output, so that the voltage gain is improved; the rail-to-rail differential input comparator adopts self-bias, and reduces a bias voltage generation circuit, thereby reducing the circuit design complexity, saving the area and reducing the power consumption; the hysteresis comparator is used as a level converter, and when the hysteresis comparator is used for realizing a high-speed single-ended input standard with a reference voltage VREF, the noise tolerance is improved, and the anti-interference capability is enhanced; the output stage of the hysteresis comparator is realized by adopting an active current mirror, the output voltage is converted into the output current, and the driving capability of the output current can be designed according to the load requirement; the method supports various true differential input standards including LVDS _25, LVDSEXT _25 and HT _25, the speed reaches 1.25Gbps, and the propagation delay is about 300 ps; support a variety of pseudo-differential input standards, including LVPECL _25, DIFF _ HSTL _ I/II/III/IV (1.5V or 1.8V), DIFF _ SSTL _ I/II (2.5V or 1.8V); support input standards of different reference voltages VREF, such as GTL, GTLP, HSTL _ I/II/III/IV (1.2V/1.5V/1.8V), SSTL _ I/II (2.5V/1.8V), etc.;
the fully differential input buffer circuit provided in this embodiment is shown in fig. 4: the first-stage comparator circuit adopts a rail-to-rail folding type cascode to realize differential input and differential output. INP and INN are adjacent PAD inputs, and NMOS input differential pair transistors N11-N12 and N21-N22 and PMOS input differential pair transistors P11-P12 and P21-P22 are adopted, so that wide-range common mode and differential mode input can be realized. N13 and N23 are NMOS input differential pair tail current sources, P13 and P23 are PMOS input differential pair tail current sources, P15-P18 and P25-P28, N14-N17 and N24-N27 form a cascode current source as an output load, and the cascode current source has output impedance up to { (gmp18 × rop18 × rop 16)/(gmn 17 × ron17 × ron15) }, so that high gain is realized.
EN is an ENABLE enabling signal, and when the ENABLE enabling signal is not used, a comparator DISABLE is used, so that power consumption is reduced; when the EN is enabled, the EN is at a high level, the inverted signal ENB of the EN is at a low level, the EN and the ENB signal enable a transmission gate (a specific circuit is shown in figure 5) to be conducted, a self-bias voltage VB is generated and supplied to the bias voltage of the cascode device, and the self-bias voltage design reduces the design of an extra multi-bias voltage generating circuit, simplifies the circuit structure, saves the chip area and reduces the power consumption.
The rail-to-rail fully differential circuit can keep stable performance in a wide common mode input range (typically 0.3V-2.2V) and a wide differential mode input range (typically 0.1V-power voltage), and correctly identifies and receives signals. True differential input interface standards such as LVDS _25, LVDSEXT _25, HT _25, RSDS _25, etc., and pseudo differential input standards such as LVPECL _25, DIFF _ HSTL _ I/II (1.5V or 1.8V), DIFF _ SSTL _ I/II (2.5V or 1.8V), etc., may be supported.
The second level conversion circuit converts a power supply VCCAUX into a kernel voltage VCCINT, simultaneously adopts a differential input, a cross-coupled current source and a diode-connected transistor as a load, further quickly amplifies and shapes the first level differential detection output, has hysteresis characteristics, and outputs a logic level from GND to VCCINT.
The circuit is provided with two feedback paths, wherein the first feedback path is current series negative feedback through M1 and M2 common source nodes, the second feedback path is series voltage positive feedback connecting M6 and M7 drain-source electrodes, when a positive feedback coefficient is larger than a negative feedback coefficient, the whole circuit shows positive feedback, hysteresis appears in a voltage transmission curve, and the hysteresis appears as long as beta 6/beta 3 is larger than 1. Assuming that the input voltage of M1 is OUT2 is VCCINT/2, the input OUT1 of M2 is 0, then M1 is on, M2 is off, M3 and M6 will be on, M4 and M7 will be off, and I5 all flows through M1 and M3, so VO1 is high, at which time M6 attempts to provide the following current:
as the M2 input increases toward the threshold point, the current of I5 begins to flow through M2, which continues until the current through M2 equals the current through M6, which changes state when exceeded, which is the first transition point. At this time:
I2＝I6；
I5＝I1+I2；
from the above equation 3, it follows:
I2＝I5-I1；
from the currents of M1 and M2, VGS of M1 and M2 can be calculated,
V+ TRP＝VGS2-VGS1；
the comparator changes state once the gate voltage of the M2 transistor reaches the threshold, so most of the tail current source flows through M2 and M4, M7 is turned on, and M3, M6 and M1 are turned off.
As the M2 gate voltage becomes smaller, the circuit reaches a point where the current value in M1 increases to be equal to the current value in M7, which is the negative transition point V of the comparator- TRP. Can be represented by the following formula:
I1＝I7；
I5＝I2+I1；
and (3) calculating:
I1＝I5-I2；
the negative turning point can be calculated using the previous equation for VGS:
V- TRP＝VGS2-VGS1。
the level converter circuit with the hysteresis effect can provide the hysteresis voltage of dozens to hundreds of mV according to design requirements, the comparator cannot be mistakenly turned over due to input signal noise or jitter, and the anti-interference capability is improved.
The output stage of the level shifter adopts an active current mirror structure to realize fully differential output, namely, a load current source is a function of an input signal, M11 and M15 are used as active current sources to provide reasonable voltage swing and output resistance, the driving capability is designed according to the load condition, the middle pole is not influenced, and the stability is improved.
The fully differential input-output buffer has an ENABLE (en) input, and when the ENABLE is inactive, the input comparator and the level conversion circuit DISABLE reduce power consumption.
The differential buffer in the embodiment adopts a fully differential structure, and comprises a rail-to-rail folding type cascode double-differential input comparator, a level converter for realizing a hysteresis function by utilizing circuit positive feedback, and an active current mirror as a differential output stage; the folding rail-to-rail double-differential input comparator adopts self-bias voltage, so that a complex bias voltage generation circuit is omitted, the circuit is simplified, the area is saved, and the power consumption and the cost are reduced; the receiver is provided with an ENABLE control end, and when the receiver is not used or is combined with other receivers, the ENABLE or DISABLE can be configured respectively, so that power consumption is saved; the fully differential buffer can be used for realizing a receiver with reference voltage VREF, can simultaneously support the standard of reference voltage input higher than 0.7V and lower than 0.7V, realizes the input standard of a wide input reference voltage range by using one circuit, saves the area and reduces the power consumption.
In practical application, as shown in fig. 6: the input comparator circuit adopts a single folding rail-to-rail cascode circuit to realize differential input and single-ended output, and the level conversion circuit also adopts single-ended input and single-ended output.
In practical application, as shown in fig. 7: the input comparator circuit adopts a single folding rail-to-rail cascode circuit to realize differential input and single-ended output, the power supply of the input comparator directly adopts a kernel power supply, and the post-stage direct BUFFER is used for shaping without a level shifter.
In practical applications, the level shifter may also implement hysteresis in other ways.
In practical application, as shown in fig. 8: the level conversion circuit adopts a single-stage active current mirror to realize the conversion from differential to single-ended output, and can directly replace the level conversion circuit in fig. 4.
In practical application, as shown in fig. 9: in the case where the output circuit in the level shift circuit uses NMOS as the active current mirror of the differential input pair as the output stage, the level shift circuit shown in fig. 4 needs to be improved.
In summary, the implementation of the present invention has at least the following advantages:
the invention provides an input buffer circuit, wherein a comparator circuit adopts a rail-to-rail folding type cascode circuit, the rail-to-rail folding type cascode circuit can realize differential input, the common mode and common difference voltage in a wide range is realized, and the problem that the conventional input buffer circuit can only support the limited common mode and differential mode voltage input range due to the comparator circuit is solved.
The above embodiments are only examples of the present invention, and are not intended to limit the present invention in any way, and any simple modification, equivalent change, combination or modification made by the technical essence of the present invention to the above embodiments still fall within the protection scope of the technical solution of the present invention.
Claims (7)
1. An input buffer circuit for a programmable logic device, comprising: a comparator circuit and a level conversion circuit; the comparator circuit comprises two rail-to-rail folding type cascode circuits, each rail-to-rail folding type cascode circuit comprises an NMOS input differential pair transistor, a PMOS input differential pair transistor and a cascode current source consisting of an NMOS and a PMOS as an output load, and the two rail-to-rail folding type cascode circuits are mutually independent and are used for realizing differential input and differential output of the comparator, widening the input range of a common-mode signal and a differential-mode signal and improving the voltage gain; the level conversion circuit is used for converting an auxiliary power supply into an inner core power supply and outputting a logic level signal to the inside of a chip according to a detection signal of the rail-to-rail folding type cascode circuit.
2. The input buffer circuit as claimed in claim 1, wherein the level shifter circuit is a fully differential circuit, and comprises an input circuit, a load circuit and an output circuit, the input circuit is connected to the load circuit, the input circuit uses NMOS transistors to implement differential input, the load circuit uses cross-coupled current sources and diode-connected transistors as loads to perform hysteretic amplification on the detection signal, and the output circuit is used to adjust current driving capability according to the load requirement of the output circuit, to perform further amplification and shaping on the output signal of the load circuit, and to output the logic level signal.
3. The input buffer circuit of claim 2, wherein the output circuit is implemented by an active current mirror circuit using PMOS as a differential input pair.
4. The input buffer circuit of claim 2, wherein the output circuit is implemented by an active current mirror circuit using NMOS as a differential input pair.
5. The input buffer circuit of claim 1, wherein the level conversion circuit is a dual-input single-output level conversion circuit, the dual-input single-output level conversion circuit comprising a differential-input, differential-to-single-ended output circuit for implementing differential input and single-ended output.
6. The input buffer circuit as claimed in claim 1, wherein the auxiliary power supply is the same as the core power supply, the comparator circuit directly uses the core power supply as the power supply of the rail-to-rail folded cascode circuit, and the detection signal is directly output to the inside of the chip by shaping the output buffer without passing through the level conversion circuit.
7. The input buffer circuit of claim 6, wherein the rail-to-rail folded-cascode circuit further comprises a bias voltage generation circuit comprising a transmission gate circuit, and an enable signal, the bias voltage generation circuit to generate a bias voltage output to the cascode current source when the enable signal is enabled.
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| CN111505525A (en) * | 2020-05-08 | 2020-08-07 | 深圳市百泰实业股份有限公司 | Anti-interference power supply detection circuit |
| CN112615606B (en) * | 2020-12-24 | 2024-10-22 | 西安翔腾微电子科技有限公司 | LVPECL signal driving circuit realized by CMOS process |
| CN112994697B (en) * | 2021-04-21 | 2021-07-30 | 微龛(广州)半导体有限公司 | Comparator |
| CN115664402A (en) * | 2022-12-09 | 2023-01-31 | 南京模砾半导体有限责任公司 | Ultra-low power consumption high-speed dynamic latch comparator |
| CN117453605B (en) * | 2023-12-26 | 2024-04-12 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
| CN118113100B (en) * | 2024-04-25 | 2024-08-13 | 瓴科微(上海)集成电路有限责任公司 | LVDS circuit with wide input range |
| CN118232904A (en) * | 2024-05-23 | 2024-06-21 | 中科亿海微电子科技（苏州）有限公司 | Input buffer for realizing high voltage resistance by using low voltage device and working method |
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