CN115001408A - Novel three-stage operational amplifier indirect frequency compensation circuit - Google Patents
Novel three-stage operational amplifier indirect frequency compensation circuit Download PDFInfo
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- CN115001408A CN115001408A CN202210675594.0A CN202210675594A CN115001408A CN 115001408 A CN115001408 A CN 115001408A CN 202210675594 A CN202210675594 A CN 202210675594A CN 115001408 A CN115001408 A CN 115001408A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45051—Two or more differential amplifiers cascade coupled
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Abstract
The invention discloses a novel three-level operational amplifier indirect frequency compensation circuit, which belongs to the field of electronic circuits and comprises a first resistor R A A second resistor R B A first capacitor C C1 A second capacitor C C2 NMOS transistor MN 1-NMOS transistor MN8 and PMOS transistor MP 1-PMOS transistor MP 6; NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 2 are first gain stages of the operational amplifier; NMOS transistors MN 6-MN 7 and PMOS transistors MP 3-MP 5 are second gain stages of the operational amplifier; NMOS transistor MN8 and PMOS transistor MP6 as third gain stage, and second resistor R B And a first capacitor C C1 A first resistor R A And a second capacitor C C2 An indirect frequency compensation network. According to the invention, the zero point positioned on the left half plane is generated to offset the secondary pole point in the operational amplifier loop, so that the phase margin of the loop and the transient stability of the circuit can be greatly improved under the condition of adopting a smaller compensation capacitor.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a novel three-level operational amplifier indirect frequency compensation circuit.
Background
An operational amplifier is an important basic unit in analog and mixed signal systems, and is widely applied to circuit design such as high-speed ADC/DAC, analog data sampling filter and voltage reference source. With the development of integrated circuit design technology, the CMOS process feature size is continuously decreased, and although the small process feature size can increase the circuit operating speed, it will cause the intrinsic gain of the MOS transistor to decrease, so that the difficulty in designing a high-performance analog circuit is greatly increased.
Compared with the threshold voltage of an MOS (metal oxide semiconductor) transistor, the power supply voltage has a faster reduction rate in modern circuit design, and the leakage current is difficult to control at the moment, so that the traditional gain enhancement scheme realized based on the cascode is not suitable for circuit design in a small-size process any more. Under the small-size process, the requirement of application on gain is realized by adopting a multistage structure operational amplifier. Considering the problems of loop stability, circuit realizability and the like, the operational amplifier design is usually completed based on a three-level structure and a direct miller compensation mode.
A small signal model of the traditional operational amplifier direct Miller compensation is shown in figure 1, and a compensation capacitor C C Will generate a zero point z in the right half plane as shown in equation (1) 1 ，z 1 The phase margin of the operational amplifier loop is reduced, and the stability of the operational amplifier is reduced.
Disclosure of Invention
The invention aims to provide a novel three-stage operational amplifier indirect frequency compensation circuit to solve the problems of reduction of circuit phase margin and reduction of stability caused by direct Miller compensation of a traditional three-stage operational amplifier.
In order to solve the above technical problems, the present invention provides a novel three-stage operational amplifier indirect frequency compensation circuit, which comprises a first resistor R A A second resistor R B A first capacitor C C1 A second capacitor C C2 NMOS transistor MN 1-NMOS transistor MN8 and PMOS transistor MP 1-PMOS transistor MP 6;
NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 2 are first gain stages of the operational amplifier; NMOS transistors MN 6-MN 7 and PMOS transistors MP 3-MP 5 are second gain stages of the operational amplifier; NMOS transistor MN8 and PMOS transistor MP6 as third gain stage, and second resistor R B And a first capacitor C C1 A first resistor R A And a second capacitor C C2 An indirect frequency compensation network.
In one embodiment, the first resistor R A Is connected with the node A at the upper end and is connected with the second capacitor C at the lower end C2 The upper end of (a); the second resistor R B Is connected with the node B at the upper end and is connected with the first capacitor C at the lower end C1 The upper end of (a); the first capacitor C C1 Is connected with the second resistor R B The lower end of the NMOS tube is simultaneously connected with the drain end of a PMOS tube MP5 and the drain end of an NMOS tube MN 7; the second capacitor C C2 Is connected with the first resistor R A The lower end of the NMOS transistor is connected with the drain terminal of the PMOS transistor MP6 and the drain terminal of the NMOS transistor MN 8.
In one embodiment, the drain terminal of the NMOS transistor MN1 is connected to the node B, and the gate terminal is connected to the negative input signal V of the operational amplifier IN_N The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN2 is connected with a node A, the gate end is connected with an operational amplifier positive input end signal V IN_P The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN3 is connected with the gate end of the PMOS tube MP5, and the gate end is connected with a signal V of the negative input end of the operational amplifier IN_N The source end is connected with the node B; the drain end of the NMOS transistor MN4 is connected with the gate end of the PMOS transistor MP4, and the gate end is connected with a signal V at the positive input end of the operational amplifier IN_P The source end is connected with the node A; the drain terminal of the NMOS tube MN5 is connected with the source terminal of the NMOS tube MN1 and the source terminal of the NMOS tube MN2 simultaneously, and the gate terminal of the NMOS tube MN5 is connected with the bias voltage signal V of the NMOS tube bias_N The source end is connected with GND; the drain end of the NMOS tube MN6 is connected with the drain end of the PMOS tube MP4, the gate end is connected with the gate end of the NMOS tube MN7, and the source end is connected with GND; the drain end of the NMOS tube MN7 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the NMOS tube MN6, and the source end is connected with GND; the drain terminal of the NMOS tube MN8 is connected with the operational amplifier output V OUT The grid end is connected with the drain end of the NMOS tube MN7, and the source end is connected with GND.
In one embodiment, the drain terminal of the PMOS transistor MP1 is connected to the drain terminal of the NMOS transistor MN3, the gate terminal is connected to the drain terminal of the PMOS transistor MP 3578, and the source terminal is connected to the power supply V DD (ii) a The drain terminal of the PMOS transistor MP2 is connected with the drain terminal and the gate terminal of the NMOS transistor MN4Connected to the gate terminal of PMOS transistor MP1, and the source terminal connected to V DD (ii) a The drain terminal of the PMOS transistor MP3 is connected with the source terminal of the PMOS transistor MP4 and the source terminal of the PMOS transistor MP5 at the same time, and the gate terminal is connected with a PMOS transistor bias voltage signal V bias_P The source end is connected with V DD (ii) a The drain end of the PMOS tube MP4 is connected with the drain end of the NMOS tube MN6, the gate end is connected with the drain end of the PMOS tube MP2, and the source end is connected with the drain end of the PMOS tube MP 3; the drain end of the PMOS tube MP5 is connected with the drain end of the NMOS tube MN7, the gate end is connected with the drain end of the PMOS tube MP1, and the source end is connected with the drain end of the PMOS tube MP 3; the drain terminal of the PMOS tube MP6 is connected with V OUT The gate terminal is connected with the drain terminal of the PMOS transistor MP2, and the source terminal is connected with V DD 。
In the novel three-level operational amplifier indirect frequency compensation circuit provided by the invention, the secondary pole point in the operational amplifier loop is offset by generating the zero point positioned on the left half plane, so that the phase margin of the loop and the transient stability of the circuit can be greatly improved under the condition of adopting a smaller compensation capacitor.
Drawings
FIG. 1 is a diagram of a small signal model of a conventional direct Miller compensation circuit;
fig. 2 is a structural diagram of a novel three-stage operational amplifier indirect frequency compensation circuit provided by the invention;
fig. 3 is a small signal model diagram of a novel three-stage operational amplifier indirect frequency compensation circuit provided by the invention.
Detailed Description
The following describes a novel three-stage operational amplifier indirect frequency compensation circuit according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a novel three-level operational amplifier indirect frequency compensation circuit, the specific structure of which is shown in figure 2, and the circuit comprises a first resistor R A A second resistor R B A first capacitor C C1 A second capacitor C C2 NMOS transistor MN 1-NMOS transistor MN8 and PMOS transistor MP 1-PMOS transistor MP 6. NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 2 are first gain stages of the operational amplifier; NMOS transistors MN 6-MN 7 and PMOS transistors MP 3-MP 5 are operational amplifiersA second gain stage; NMOS transistor MN8 and PMOS transistor MP6 as third gain stage, and second resistor R B And a first capacitor C C1 A first resistor R A And a second capacitor C C2 An indirect frequency compensation network.
With continued reference to FIG. 2, the first resistor R A Is connected with the node A at the upper end and is connected with the second capacitor C at the lower end C2 The upper end of (a); the second resistor R B Is connected with the node B at the upper end and is connected with the first capacitor C at the lower end C1 The upper end of (a); the first capacitor C C1 Is connected with the second resistor R B The lower end of the NMOS tube is simultaneously connected with the drain end of a PMOS tube MP5 and the drain end of an NMOS tube MN 7; the second capacitor C C2 Is connected with the first resistor R A The lower end of the NMOS transistor is connected with the drain terminal of the PMOS transistor MP6 and the drain terminal of the NMOS transistor MN 8.
The drain end of the NMOS tube MN1 is connected with the node B, and the gate end is connected with the negative input end signal V of the operational amplifier IN_N The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN2 is connected with a node A, the gate end is connected with an operational amplifier positive input end signal V IN_P The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN3 is connected with the gate end of the PMOS tube MP5, and the gate end is connected with a signal V of the negative input end of the operational amplifier IN_N The source end is connected with the node B; the drain end of the NMOS transistor MN4 is connected with the gate end of the PMOS transistor MP4, and the gate end is connected with a signal V at the positive input end of the operational amplifier IN_P The source end is connected with the node A; the drain terminal of the NMOS tube MN5 is connected with the source terminal of the NMOS tube MN1 and the source terminal of the NMOS tube MN2 simultaneously, and the gate terminal of the NMOS tube MN5 is connected with the bias voltage signal V of the NMOS tube bias_N The source end is connected with GND; the drain end of the NMOS tube MN6 is connected with the drain end of the PMOS tube MP4, the gate end is connected with the gate end of the NMOS tube MN7, and the source end is connected with GND; the drain end of the NMOS tube MN7 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the NMOS tube MN6, and the source end is connected with GND; the drain terminal of the NMOS tube MN8 is connected with the operational amplifier output V OUT The grid end is connected with the drain end of the NMOS tube MN7, and the source end is connected with GND.
The drain terminal of the PMOS tube MP1 is connected with the drain terminal of the NMOS tube MN3, the gate terminal is connected with the drain terminal of the PMOS tube MP1, and the source terminal is connected with a power supply V DD (ii) a The drain terminal of the PMOS transistor MP2 is connected with the drain terminal of the NMOS transistor MN4, the gate terminal is connected with the gate terminal of the PMOS transistor MP1, and the source terminal is connected with V DD (ii) a The drain terminal of the PMOS transistor MP3 is connected with the source terminal of the PMOS transistor MP4 and the source terminal of the PMOS transistor MP5 at the same time, and the gate terminal is connected with a PMOS transistor bias voltage signal V bias_P Source end connected to V DD (ii) a The drain end of the PMOS tube MP4 is connected with the drain end of the NMOS tube MN6, the gate end is connected with the drain end of the PMOS tube MP2, and the source end is connected with the drain end of the PMOS tube MP 3; the drain end of the PMOS tube MP5 is connected with the drain end of the NMOS tube MN7, the gate end is connected with the drain end of the PMOS tube MP1, and the source end is connected with the drain end of the PMOS tube MP 3; the drain terminal of the PMOS tube MP6 is connected with V OUT The gate terminal is connected with the drain terminal of the PMOS transistor MP2, and the source terminal is connected with V DD 。
The working principle of the invention is as follows:
(1) and (3) compensation network analysis:
the indirect frequency compensation is realized based on low-resistance nodes in the circuit, and particularly, in fig. 2, the MOS tube at the positive and negative input ends of the operational amplifier is split into a serial structure of NMOS tubes MN1 and MN3 and NMOS tubes MN2 and MN4, so that low-resistance nodes required for compensation are formed at the source ends of cascode tubes MN3 and MN 4. A first capacitor C C1 For compensating the capacitance, via a second resistor R as a zero-setting resistor B Is connected to a low-resistance node B and a second capacitor C C2 A first resistor R as a zero-setting resistor for compensating the capacitance A Is connected to the low-resistance node A, and finally two zeros (z) positioned in the left half plane can be generated in the loop 1 、z 2 ) To cancel the secondary pole (p) 1 、p 2 ) Influence on the loop phase margin.
(2) Frequency response analysis
In the small signal model diagram of the novel three-stage operational amplifier indirect frequency compensation circuit shown in FIG. 3, g m1 ～g m3 Equivalent transconductance of the first to third gain stages, R 1 ～R 3 The first through third gain stages are equivalent output impedances. The loop transfer function is shown in formula (2), wherein a 0 、a 1 、a 2 、a 3 、a 4 、a 5 、b 0 、b 1 、b 2 、b 3 Is a constant independent of the process.
Zero point z on left half plane generated by indirect frequency compensation network 1 、z 2 As shown in formula (3):
parasitic zero point z at high frequency 3 As shown in formula (4):
dominant pole p 1 As shown in formula (5):
the secondary pole p 2 、p 3 As shown in formulas (6) and (7):
reasonably setting middle resistance and capacitance (R) in circuit compensation network A 、R B 、C C1 、C C2 ) And when the two formulas (9) and (11) are established, the mutual offset of the zero point and the secondary pole point in the loop can be realized, and the phase margin and the stability of the circuit are greatly improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. A novel three-level operational amplifier indirect frequency compensation circuit is characterized by comprising a first resistor R A A second resistor R B A first capacitor C C1 A second capacitor C C2 NMOS transistor MN 1-NMOS transistor MN8 and PMOS transistor MP 1-PMOS transistor MP 6;
NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 2 are first gain stages of the operational amplifier; NMOS transistors MN 6-MN 7 and PMOS transistors MP 3-MP 5 are second gain stages of the operational amplifier; NMOS transistor MN8 and PMOS transistor MP6 as third gain stage, and second resistor R B And a first capacitor C C1 A first resistor R A And a second capacitor C C2 An indirect frequency compensation network.
2. The novel three-stage operational amplifier indirect frequency compensation circuit of claim 1, wherein the first resistor R is A Is connected with the node A at the upper end and is connected with the second capacitor C at the lower end C2 The upper end of (a); the second resistor R B Is connected with the node B at the upper end and is connected with the first capacitor C at the lower end C1 The upper end of (a); the first capacitor C C1 Is connected with the second resistor R B The lower end of the NMOS tube is simultaneously connected with the drain end of a PMOS tube MP5 and the drain end of an NMOS tube MN 7; the second capacitor C C2 Is connected with the first resistor R A The lower end of the NMOS transistor is connected with the drain terminal of the PMOS transistor MP6 and the drain terminal of the NMOS transistor MN 8.
3. The novel indirect frequency compensation circuit of three-stage operational amplifier as claimed in claim 2, wherein the drain terminal of the NMOS transistor MN1 is connectedNode B, grid terminal connected with negative input signal V of operational amplifier IN_N The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN2 is connected with a node A, the gate end is connected with an operational amplifier positive input end signal V IN_P The source end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN 5; the drain end of the NMOS tube MN3 is connected with the gate end of the PMOS tube MP5, and the gate end is connected with a signal V of the negative input end of the operational amplifier IN_N The source end is connected with the node B; the drain end of the NMOS tube MN4 is connected with the gate end of the PMOS tube MP4, and the gate end is connected with a signal V of the positive input end of the operational amplifier IN_P The source end is connected with the node A; the drain terminal of the NMOS transistor MN5 is connected to the source terminal of the NMOS transistor MN1 and the source terminal of the NMOS transistor MN2, and the gate terminal of the NMOS transistor MN5 is connected to an NMOS transistor bias voltage signal V bias_N The source end is connected with GND; the drain end of the NMOS tube MN6 is connected with the drain end of the PMOS tube MP4, the gate end is connected with the gate end of the NMOS tube MN7, and the source end is connected with GND; the drain end of the NMOS tube MN7 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the NMOS tube MN6, and the source end is connected with GND; the drain terminal of the NMOS tube MN8 is connected with the operational amplifier output V OUT The grid end is connected with the drain end of the NMOS tube MN7, and the source end is connected with GND.
4. The novel indirect frequency compensation circuit of three-stage operational amplifier as claimed in claim 3, wherein the drain terminal of the PMOS transistor MP1 is connected to the drain terminal of the NMOS transistor MN3, the gate terminal is connected to the drain terminal of the PMOS transistor MP1, and the source terminal is connected to the power supply V DD (ii) a The drain terminal of the PMOS transistor MP2 is connected with the drain terminal of the NMOS transistor MN4, the gate terminal is connected with the gate terminal of the PMOS transistor MP1, and the source terminal is connected with V DD (ii) a The drain terminal of the PMOS transistor MP3 is connected with the source terminal of the PMOS transistor MP4 and the source terminal of the PMOS transistor MP5 at the same time, and the gate terminal is connected with a PMOS transistor bias voltage signal V bias_P The source end is connected with V DD (ii) a The drain end of the PMOS tube MP4 is connected with the drain end of the NMOS tube MN6, the gate end is connected with the drain end of the PMOS tube MP2, and the source end is connected with the drain end of the PMOS tube MP 3; the drain end of the PMOS tube MP5 is connected with the drain end of the NMOS tube MN7, the gate end is connected with the drain end of the PMOS tube MP1, and the source end is connected with the drain end of the PMOS tube MP 3; the drain terminal of the PMOS tube MP6 is connected with V OUT The gate terminal is connected with the drain terminal of the PMOS transistor MP2, and the source terminal is connected with V DD 。
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| CN202210675594.0A CN115001408A (en) | 2022-06-15 | 2022-06-15 | Novel three-stage operational amplifier indirect frequency compensation circuit |
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| CN202210675594.0A CN115001408A (en) | 2022-06-15 | 2022-06-15 | Novel three-stage operational amplifier indirect frequency compensation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115149910A (en) * | 2022-09-06 | 2022-10-04 | 中国电子科技集团公司第五十八研究所 | Three-stage operational amplifier capacitor multiplication frequency compensation circuit |
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2022
- 2022-06-15 CN CN202210675594.0A patent/CN115001408A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115149910A (en) * | 2022-09-06 | 2022-10-04 | 中国电子科技集团公司第五十八研究所 | Three-stage operational amplifier capacitor multiplication frequency compensation circuit |
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