CN115149910B - Capacitance multiplication frequency compensation circuit for three-stage operational amplifier - Google Patents
Capacitance multiplication frequency compensation circuit for three-stage operational amplifier Download PDFInfo
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- CN115149910B CN115149910B CN202211084195.3A CN202211084195A CN115149910B CN 115149910 B CN115149910 B CN 115149910B CN 202211084195 A CN202211084195 A CN 202211084195A CN 115149910 B CN115149910 B CN 115149910B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/38—Circuit design at the mixed level of analogue and digital signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/26—Push-pull amplifiers; Phase-splitters therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
Abstract
The invention discloses a three-stage operational amplifier capacitor multiplication frequency compensation circuit, and belongs to the field of electronic circuits. The PMOS tube MP1, the PMOS tube MP2, the PMOS tube MP3, the NMOS tube MN1 and the NMOS tube MN2 form an operational amplifier first gain stage; the PMOS tube MP4 and the NMOS tube MN3 form an operational amplifier second gain stage; the PMOS tube MP5, the PMOS tube MP6 and the NMOS tube MN4 form an operational amplifier third gain stage; the NMOS transistor MN5 forms an operational amplifier feed-forward gain stage to improve the driving capability of the operational amplifier to a capacitive load. By adopting the capacitance multiplication technology, the operational amplifier can adopt smaller compensation capacitance to realize the same stability compensation effect; the extra feedforward path that increases will constitute pseudo AB class at the output of the operational amplifier and push up the output stage, can promote the output slew rate of the operational amplifier under the condition that does not increase the circuit consumption, increase the driving ability of the operational amplifier to the capacitive load.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a three-stage operational amplifier capacitor multiplication frequency compensation circuit.
Background
An operational amplifier is a fundamental unit in analog and mixed signal circuit design. With the development of modern integrated circuit industry, operational amplifiers are required to achieve high gain, high bandwidth and high stability at low supply voltages. In order to ensure that the operational amplifier performance meets the design requirements under low power supply voltage, a miller structure is usually adopted to complete frequency compensation, and a compensation capacitor in the compensation mode occupies a large amount of chip area.
The second gain stage of the traditional three-stage operational amplifier generally adopts an inverse amplification structure and carries out frequency compensation based on an inverse nested Miller structure. The small signal model of the conventional reverse nested miller compensation circuit is shown in fig. 1, due to the compensation capacitor C C1 A feed-forward path is formed in the loop, so that a zero point positioned on a right half plane exists in the loop, which causes the phase margin of the loop to be reduced, the stability to be reduced and the maximum bandwidth of the operational amplifier to be limited; meanwhile, in order to satisfy the circuit stability in the full load range, C in the reverse nested Miller compensation structure shown in FIG. 1 C1 Usually of large value, large C C1 This will lead to an increase in chip area and manufacturing cost.
Disclosure of Invention
The invention aims to provide a three-stage operational amplifier capacitance multiplication frequency compensation circuit to solve the problems that the circuit has a right half-plane zero point due to the reverse nested Miller compensation of the traditional three-stage operational amplifier, so that the stability is reduced and the required compensation capacitance is larger.
In order to solve the above technical problem, the present invention provides a three-stage operational amplifier capacitor multiplication frequency compensation circuit, which comprises a resistor R b Resistance R c Capacitor C C1 Capacitor C C2 Capacitor C L NMOS tubes MN1 to MN5 and PMOS tubes MP1 to MP6;
resistance R b The upper end of the NMOS tube is connected with the drain end of the NMOS tube MN1, and the lower end of the NMOS tube is connected with the grid end of the NMOS tube MN 1; resistance R c The upper end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN2, and the lower end of the NMOS tube is connected with a capacitor C C2 Upper end of, capacitor C C2 The lower end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN 3; capacitor C C1 The upper end of the NMOS tube MN1 is connected with the grid end of the NMOS tube MN1, and the lower end of the NMOS tube is connected with the output end V OUT (ii) a Capacitor C L Upper end of (C) is connected with output V OUT The lower end is connected with GND;
the drain end of the NMOS tube MN1 is connected with the drain end of the PMOS tube MP2, and the source end is connected with GND; the drain terminal of the NMOS transistor MN2 is connected with the drain terminal of the PMOS transistor MP3, and the gate terminal is connected with the resistor R b The source end of the upper end of the transformer is connected with GND; the drain terminal of the NMOS transistor MN3 is connected with the drain terminal of the PMOS transistor MP4, and the gate terminal is connected with the resistor R c The source end of the upper end of the transformer is connected with GND; the drain end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the PMOS tube MP4, and the source end is connected with GND; the drain end of the NMOS tube MN5 is connected with the drain end of the PMOS tube MP6, the gate end is simultaneously connected with the drain end of the NMOS tube MN2 and the gate end of the NMOS tube MN3, and the source end is connected with GND;
the drain terminal of the PMOS tube MP1 is connected with the source terminal of the PMOS tube MP2 and the source terminal of the PMOS tube MP3 at the same time, and the gate terminal is connected with a bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal of the PMOS tube MP2 is connected with the drain terminal of the NMOS tube MN1, and the gate terminal is connected with the negative input terminal V of the operational amplifier IN- (ii) a The drain terminal of the PMOS tube MP3 is connected with the drain terminal of the NMOS tube MN2, the gate terminal is connected with the positive input terminal V of the operational amplifier IN+ (ii) a The drain terminal of the PMOS transistor MP4 is connected with the drain terminal of the NMOS transistor MN3, and the gate terminal is connected with a bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal and the gate terminal of the PMOS tube MP5 are both connected with the drain terminal of the NMOS tube MN4, and the source terminal is connected with a power supply V DD (ii) a The drain terminal of the PMOS transistor MP6 is connected with the drain terminal of the NMOS transistor MN5, the gate terminal is connected with the drain terminal of the NMOS transistor MN5, and the source terminal is connected with the power supplySource V DD 。
In one embodiment, the PMOS transistor MP1, the PMOS transistor MP2, the PMOS transistor MP3, the NMOS transistor MN1, and the NMOS transistor MN2 form a first gain stage of the operational amplifier; the PMOS transistor MP4 and the NMOS transistor MN3 form an operational amplifier second gain stage; the PMOS tube MP5, the PMOS tube MP6 and the NMOS tube MN4 form an operational amplifier third gain stage; and the NMOS pipe MN5 forms an operational amplifier feed-forward gain stage so as to improve the driving capability of the operational amplifier to a capacitive load.
In one embodiment, the capacitor C C1 To compensate for capacitance, said capacitance C L As a load capacitance, the bias voltage V bias Used for setting bias current in PMOS tubes MP1 and MP4, and the capacitor C C1 And a capacitor C C2 For frequency compensation.
The three-stage operational amplifier capacitor multiplication frequency compensation circuit provided by the invention has the following beneficial effects:
(1) By the capacitance multiplication technology, the operational amplifier can adopt smaller compensation capacitance to realize the same stability compensation effect;
(2) The extra feedforward path that increases will constitute pseudo AB class at the output of the operational amplifier and push up the output stage, can promote the output slew rate of the operational amplifier under the condition that does not increase the circuit consumption, increase the driving ability of the operational amplifier to the capacitive load.
Drawings
Fig. 1 is a small signal model diagram of a traditional three-stage operational amplifier reverse nested miller compensation circuit.
Fig. 2 is a schematic structural diagram of a three-stage operational amplifier capacitance multiplication frequency compensation circuit provided in the present invention.
FIG. 3 is a diagram of a small signal model of a capacitance multiplying circuit.
Fig. 4 is a small signal model diagram of a three-stage operational amplifier capacitor multiplication frequency compensation circuit provided by the present invention.
Detailed Description
The three-stage operational amplifier capacitance multiplication frequency compensation circuit provided by the invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a three-stage operational amplifier capacitor multiplication frequency compensation circuit, the structure of which is shown in figure 2, and the circuit comprises a resistor R b And a resistor R c Capacitor C C1 Capacitor C C2 Capacitor C L NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 6;
wherein the resistance R b The upper end of the NMOS tube is connected with the drain end of the NMOS tube MN1, and the lower end of the NMOS tube is connected with the grid end of the NMOS tube MN 1; resistance R c The upper end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN2, and the lower end of the NMOS tube is connected with a capacitor C C2 Upper end of, capacitor C C2 The lower end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN 3; capacitor C C1 The upper end of the NMOS tube MN1 is connected with the grid end of the NMOS tube MN1, and the lower end of the NMOS tube is connected with the output end V OUT (ii) a Capacitor C L Upper end of (C) is connected with output V OUT The lower end is connected with GND; the drain terminal of the NMOS transistor MN1 is connected with the drain terminal of the PMOS transistor MP2, and the gate terminal is simultaneously connected with the resistor R b Lower terminal of and capacitor C C1 The source end of the upper end of the transformer is connected with GND; the drain terminal of the NMOS transistor MN2 is connected with the drain terminal of the PMOS transistor MP3, and the gate terminal is connected with the resistor R b The source end of the upper end of the transformer is connected with GND; the drain terminal of the NMOS transistor MN3 is connected with the drain terminal of the PMOS transistor MP4, and the gate terminal is connected with the resistor R c The source end of the upper end of the transformer is connected with GND; the drain end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the PMOS tube MP4, and the source end is connected with GND; the drain end of the NMOS tube MN5 is connected with the drain end of the PMOS tube MP6, the gate end is simultaneously connected with the drain end of the NMOS tube MN2 and the gate end of the NMOS tube MN3, and the source end is connected with GND; the drain terminal of the PMOS transistor MP1 is connected with the source terminal of the PMOS transistor MP2 and the source terminal of the PMOS transistor MP3 at the same time, and the gate terminal is connected with a bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal of the PMOS tube MP2 is connected with the drain terminal of the NMOS tube MN1, and the gate terminal is connected with the negative input terminal V of the operational amplifier IN- (ii) a The drain end of the PMOS tube MP3 is connected with the drain end of the NMOS tube MN2, the gate end is connected with the positive input end V of the operational amplifier IN+ (ii) a The drain terminal of the PMOS transistor MP4 is connected with the drain terminal of the NMOS transistor MN3, and the gate terminal is connected with a bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal and the gate terminal of the PMOS tube MP5 are both connected with the drain terminal of the NMOS tube MN4, and the source terminal is connected with a power supply V DD (ii) a The drain terminal of the PMOS tube MP6 is connected with the drain terminal of the NMOS tube MN5, the gate terminal is connected with the drain terminal of the NMOS tube MN5, and the source terminal is connected with a power supply V DD 。
In FIG. 2 byTo the capacitor C C1 Applying a capacitance multiplication technique to enhance its frequency compensation effect on the loop, the multiplication number being determined by a resistor R b And (6) adjusting. The PMOS tube MP1, the PMOS tube MP2, the PMOS tube MP3, the NMOS tube MN1 and the NMOS tube MN2 form an operational amplifier first gain stage. The PMOS transistor MP4 and the NMOS transistor MN3 form a second gain stage of the operational amplifier. And the PMOS tube MP5, the PMOS tube MP6 and the NMOS tube MN4 form an operational amplifier third gain stage. The NMOS transistor MN5 forms an operational amplifier feed-forward gain stage, and can improve the driving capability of the operational amplifier to capacitive loads. V bias The bias voltage is fixed, and the bias current in the PMOS tubes MP1 and MP4 is set. C L Is the load capacitance. Resistance R c Capacitor C C1 And a capacitor C C2 For frequency compensation.
The working principle of the invention is as follows:
the capacitance multiplication effect is realized:
capacitor C C1 For compensation capacitance, the capacitance multiplication small signal process is shown in FIG. 3, and the equivalent compensation capacitance seen at point A in FIG. 2 is
By multiplexing the current mirror loads MN1 and MN2 (i.e., NMOS transistor MN1 and NMOS transistor MN 2) in the operational amplifier first gain stage of fig. 2, the compensation capacitor C can be implemented C1 The multiplication effect of (2) does not need an additional circuit, and does not cause the increase of the power consumption of the circuit. Resistance R b For adjusting the multiplication factor of capacitance, in particular the multiplication factor of capacitance is
In which-g mb And represents the transconductance of the current mirror loads MN1 and MN2 in the first gain stage of the operational amplifier of fig. 2.
Small signal stability analysis:
the small signal operation model of the three-stage operational amplifier capacitor multiplication frequency compensation circuit proposed in FIG. 2 is shown in FIG. 4, where-g m1 、-g m2 、g m3 First, second and third gain stage transconductors, -g mf Transconductance of the feed-forward gain stage, -g mb Transconductance of current mirror loads MN1 and MN2 in a first gain stage of the operational amplifier; r o1 Is the first gain stage, etcEffective output impedance, C p1 Is the equivalent parasitic capacitance, R, of the output terminal of the first gain stage o2 Is the equivalent output impedance of the second gain stage, C p2 Is the equivalent parasitic capacitance, R, of the output terminal of the second gain stage L Representing the output terminal equivalent load.
As can be seen in FIG. 4, the equivalent Miller compensation capacitance seen at point A in FIG. 2 is
. The NMOS transistor MN2 provides a feedback path for the compensation network and simultaneously blocks a signal from a point A through a capacitor C C1 To the output end V OUT The feed-forward transmission path of (1) can finally eliminate the capacitor C C1 The right half-plane zero introduced by the feed-forward path is formed. For the resistor R connected across the second gain stage c Capacitor C C2 Can be adjusted by adjusting R c The parameters are such that they introduce only one left half-plane zero that does not affect the loop stability.
Negative end input signal V of operational amplifier in FIG. 4 IN- Transmitted to the output end V through three paths at the point B OUT : the first path is through a resistor R b Capacitor C C1 Transmitted to the output terminal V OUT The second path is through-g mb 、-g mf Is transmitted to the output end V OUT The third path is through-g mb 、-g m2 、g m3 Transmitted to the output terminal V OUT . Since the three transmission paths have the same signal phase, the resistor R is removed c Capacitor C C2 Besides the zero point of the introduced left half plane, a second zero point located on the left half plane exists in the loop, and the zero point located on the right half plane does not exist in the whole system.
Suppose that the amplification factors of three gain stages in the operational amplifier are all far greater than 1, and the compensation capacitor C C1 、C C2 Are far greater than parasitic capacitance C p1 、C p2 Then, under the two expressions (1) and (2), the operational amplifier transfer function a(s) is as shown in expression (3):
（1）
(3) Wherein A, B, C and D are all fixed constants, and the expressions are shown as (4), (5), (6) and (7):
according to the formula (3), the low-frequency DC gain A of the circuit DC And dominant pole ω p1 Respectively shown as formulas (8) and (9):
compared with the traditional three-stage operational amplifier reverse nested Miller compensation, the circuit provided by the invention is used for compensating the capacitor C C1 After the capacitance multiplication, the frequency of the main pole point is reduced
And (4) multiplying. Thus indicating that the same size C is used C1 Under the condition, the scheme provided by the invention can greatly improve the circuit stability.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (3)
1. A three-stage operational amplifier capacitance multiplication frequency compensation circuit is characterized by comprising a resistor R b Resistance R c Capacitor C C1 Capacitor C C2 Capacitor C L NMOS transistors MN 1-MN 5 and PMOS transistors MP 1-MP 6;
resistance R b The upper end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN1, and the lower end of the NMOS tube MN1 is connected with the grid end of the NMOS tube; resistance R c The upper end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN2, and the lower end of the NMOS tube is connected with a capacitor C C2 Upper end of, capacitor C C2 The lower end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN 3; capacitor C C1 The upper end of the NMOS tube MN1 is connected with the grid end of the NMOS tube MN1, and the lower end of the NMOS tube is connected with the output end V OUT (ii) a Capacitor C L Upper end of (C) is connected with output V OUT The lower end is connected with GND;
the drain end of the NMOS tube MN1 is connected with the drain end of the PMOS tube MP2, and the source end is connected with GND; the drain terminal of the NMOS transistor MN2 is connected with the drain terminal of the PMOS transistor MP3, and the gate terminal is connected with the resistor R b The source end of the upper end of the transformer is connected with GND; the drain terminal of the NMOS transistor MN3 is connected with the drain terminal of the PMOS transistor MP4, and the gate terminal is connected with the resistor R c The source end of the upper end of the transformer is connected with GND; the drain end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP5, the gate end is connected with the drain end of the PMOS tube MP4, and the source end is connected with GND; the drain end of the NMOS tube MN5 is connected with the drain end of the PMOS tube MP6, the grid end is simultaneously connected with the drain end of the NMOS tube MN2 and the grid end of the NMOS tube MN3, and the source end is connected with GND;
the drain terminal of the PMOS transistor MP1 is connected with the source terminal of the PMOS transistor MP2 and the source terminal of the PMOS transistor MP3 at the same time, and the gate terminal is connected with a bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal of the PMOS tube MP2 is connected with the drain terminal of the NMOS tube MN1, and the gate terminal is connected with the negative input terminal V of the operational amplifier IN- (ii) a The drain end of the PMOS tube MP3 is connected with the drain end of the NMOS tube MN2, the gate end is connected with the positive input end V of the operational amplifier IN+ (ii) a The drain terminal of the PMOS transistor MP4 is connected with the drain terminal and the gate of the NMOS transistor MN3Termination bias voltage V bias Source end connected with power supply V DD (ii) a The drain terminal and the gate terminal of the PMOS tube MP5 are both connected with the drain terminal of the NMOS tube MN4, and the source terminal is connected with a power supply V DD (ii) a The drain terminal of the PMOS tube MP6 is connected with the drain terminal of the NMOS tube MN5, the gate terminal is connected with the drain terminal of the NMOS tube MN5, and the source terminal is connected with a power supply V DD 。
2. The three-stage operational amplifier capacitance multiplication frequency compensation circuit of claim 1, wherein the PMOS transistor MP1, the PMOS transistor MP2, the PMOS transistor MP3, the NMOS transistor MN1, and the NMOS transistor MN2 form a first gain stage of the operational amplifier; the PMOS tube MP4 and the NMOS tube MN3 form an operational amplifier second gain stage; the PMOS tube MP5, the PMOS tube MP6 and the NMOS tube MN4 form an operational amplifier third gain stage; and the NMOS pipe MN5 forms an operational amplifier feed-forward gain stage so as to improve the driving capability of the operational amplifier to a capacitive load.
3. The three-stage operational amplifier capacitance multiplication frequency compensation circuit of claim 1, wherein the capacitor C C1 To compensate for capacitance, said capacitance C L As a load capacitance, the bias voltage V bias For setting bias currents in PMOS transistors MP1 and MP4, and capacitor C C1 And a capacitor C C2 For frequency compensation.
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| CN202211084195.3A CN115149910B (en) | 2022-09-06 | 2022-09-06 | Capacitance multiplication frequency compensation circuit for three-stage operational amplifier |
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| CN101917169B (en) * | 2010-08-05 | 2013-02-27 | 复旦大学 | High-bandwidth low-power consumption frequency-compensation three-stage operational amplifier |
| CN104506151B (en) * | 2014-11-27 | 2017-06-09 | 电子科技大学 | A kind of operational amplifier for medical electronics |
| CN105720927B (en) * | 2016-01-21 | 2018-03-27 | 中国电子科技集团公司第二十四研究所 | A kind of frequency compensated trsanscondutance amplifier |
| CN111880597B (en) * | 2020-07-14 | 2022-09-13 | 上海艾为电子技术股份有限公司 | Linear voltage stabilizing circuit and electronic equipment |
| CN115001407A (en) * | 2022-06-15 | 2022-09-02 | 中国电子科技集团公司第五十八研究所 | Three-stage operational amplifier active network miller compensation circuit |
| CN115001408A (en) * | 2022-06-15 | 2022-09-02 | 中国电子科技集团公司第五十八研究所 | Novel three-stage operational amplifier indirect frequency compensation circuit |
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