CN101917169B - High-bandwidth low-power consumption frequency-compensation three-stage operational amplifier - Google Patents

High-bandwidth low-power consumption frequency-compensation three-stage operational amplifier Download PDF

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CN101917169B
CN101917169B CN2010102458533A CN201010245853A CN101917169B CN 101917169 B CN101917169 B CN 101917169B CN 2010102458533 A CN2010102458533 A CN 2010102458533A CN 201010245853 A CN201010245853 A CN 201010245853A CN 101917169 B CN101917169 B CN 101917169B
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CN101917169A (en
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李冉
刘俊娟
洪志良
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Fudan University
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Abstract

The invention belongs to the technical field of analog IC (Integrated Circuit) design, in particular to a high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier. The amplifier comprises an input stage, a second stage, an output stage, a common mode feedback stage, a comprehension circuit, an internal feedforward circuit, wherein the second stage is connected with the input stage, the output stage is connected with the second stage and used for amplifying a signal output by the second stage and driving an external load circuit, the common mode feedback stage extracts the common mode level of the differential output stage and stabilizes the common mode level, the comprehension circuit comprises a traditional trsanscondutance comprehension circuit, a miller comprehension circuit and a resistor for separating a high-frequency zero pole, and the internal feedforward circuit is used for comprehending an internal additional pole and forming a push-pull circuit together with the output stage to reduce static power consumption. The three-stage operational amplifier realizes high gain, high bandwidth and high stability under the condition of little DC power consumption and can be used in a high-speed analog-digital conversion circuit, such as a sigma-delta modulator suitable for the bandwidth of an LTE (Line Terminator Equipment) wireless communication protocol.

Description

High-bandwidth low-power consumption frequency-compensation three-stage operational amplifier
Technical field
Technical field of analog integrated circuit design of the present invention is specifically related to a kind of high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier, can be used in the high speed analog-digital conversion conversion circuit.
Background technology
Along with the continuous renewal of semiconductor process techniques, supply voltage is more and more lower under the CMOS technique, and as analog integrated circuit design basic module, the design of operational amplifier has obtained increasing challenge.General structure need to adopt short channel length to realize faster speed in order to obtain high bandwidth in the situation of lower power consumption, but can cause lower DC current gain, and short channel length can produce larger process deviation, and the method that tradition improves gain has been not suitable for being applied to the from now on development of technology such as stack transistor or gain bootstrap circuit along with the reduction of supply voltage.
While is along with the development of home control network communication protocol, bandwidth requirement for analog to digital converter is increasing, take over-sampling type analog-to-digital conversion device as example, be applicable to that the requirement maximum to the analog to digital converter bandwidth can arrive 20 megahertzes in the LTE home control network communication protocol, like this will be very high to the requirement of the operational amplifier of the inside even reach upper Gigahertz (GHz).So need to find a kind of structure that realizes high-gain and high bandwidth operational amplifier with lower power consumption.
Casacade multi-amplifier can be relatively easy to the gain that reaches higher, but increase merely the problem of the progression meeting existence and stability of amplifier, because there is more zero limit in casacade multi-amplifier, the preferably stability problem of collocation structure guarantee multi-stage operational amplifier need to be arranged.The design of tradition casacade multi-amplifier is in order to drive very large capacitive load or resistive load, bandwidth generally at tens megahertzes to the hundreds of megahertz, generally ignore the impact of endophyte electric capacity during design.And the amplifier load that is applied in the communications field is generally lighter, requires very large bandwidth, need to consider like this impact of endophyte electric capacity in design.
Usually the casacade multi-amplifier frequency compensation technology that adopts has Miller (Miller) compensation technique, mutual conductance and miller-compensated (NGRNMC) technology of zero-regulator resistor and transconductance capacitor compensation (TCFC) technology etc.Take three-stage operational amplifier as example, miller-compensated technology is to adopt two feedback capacities, is connected across respectively the output of output stage and first and second grade.The miller-compensated technology of feedforward transconductance is respectively from input and second level input cross-over connection feedforward transconductance to output on miller-compensated basis; The transconductance capacitor compensation technique is to have added a mutual conductance in the middle of the output of the miller-compensated second level and second building-out capacitor.
Fig. 1 is the structured flowchart of three grades of miller-compensated technology in the background technology, and third stage amplifier comprises first order amplifier A1, second level amplifier A2, third level amplifier A3.The mutual conductance of this third stage amplifier is respectively g M1, g M2And g M3, output resistance is respectively R 1, R 2And R 3, the lump output capacitance is C 1, C 2And C LMiller-compensated capacitor C M1Be connected across the output of A1 and the output of A3.Miller-compensated capacitor C M2Be connected across the output of A2 and the output of A3.Suppose miller-compensated capacitor C M1, C M2With load capacitance C L＞＞inner lump output capacitance C 1And C 2, can obtain the open loop frequency response formula of this structure:
A v ( s ) = A dc ( 1 + s ω 3 + s 2 ω 3 ω 4 ) ( 1 + s ω d ) ( 1 + s ω 1 + s 2 ω 1 ω 2 ) - - - ( 1 )
A DcBe DC current gain A Dc=g M1g M2g M3R 1R 2R 3, ω dBe dominant pole ω d=1/C M1g M2g M3R 1R 2R 3, unity gain bandwidth is ω UG=g M1/ C M1, two limit ω 1=g M2/ C M2, ω 2=g M3/ C L, two zero point ω 3=-g M3/ C M2, ω 4=g M2/ C M1For the third stage amplifier that makes this structure keeps stable, need to make ω 2=2 ω 1=4 ω UG, in order to obtain larger unity gain bandwidth g M1/ C M1Larger, and C M1Can not get very little of to prevent the impact of endophyte electric capacity, in like manner C M2And C LThe mutual conductance that also can very littlely not this shows last two sets needs very large guarantee amplifier to keep stable, and this structure can not obtain lower power consumption, the design of inapplicable and low-power consumption.
Fig. 2 is the structured flowchart of three grades of mutual conductances and the miller-compensated technology of zero-regulator resistor in the background technology, and third stage amplifier comprises first order amplifier B1, second level amplifier B2, third level amplifier B3.The mutual conductance of this third stage amplifier is respectively g M1, g M2And g M3, output resistance is respectively R 1, R 2And R 3, the lump output capacitance is C 1, C 2And C LAlso have first order feed-forward amplifier B4, second level feed-forward amplifier B5, their mutual conductance is respectively g Mf1And g Mf0Miller-compensated capacitor C M1Be connected across the output of B1 and the output of B3.Miller-compensated capacitor C M2Be connected across output and the zero-regulator resistor R of B3 mTwo ends, zero-regulator resistor R mBe connected across output and the C of B2 M2Two ends.The miller-compensated capacitor C of same hypothesis M1, C M2With load capacitance C L＞＞inner lump output capacitance C 1And C 2, the dominant pole that can obtain it is
ω d=1/C M1g M2g M3R 1R 2R 3, other limits ω 1=g M2g M3/ [(g M2g M3R m+ g M3-g M2) C M2],
ω 2=(R M2R M3R m+ g M3-R M2)/C L, zero point
ω 3＝g m1g m2g m3/(g m3g mf0C m1+g m1g m2g m3R mC m2-g m1g m2C m2)
ω 4=(g M3g Mf0C M1+ g M1g M2g M3R mC M2-g M1g M2C M2)/(g M3g Mf0R m+ g Mf1-g Mf0-g M1) C M1C M2, the time this structure amplifier keep stable in, can be by adjusting C LAnd C M1, C LAnd C M2Ratio and resistance R mReduce the mutual conductance of last two-stage, can be reduced at most about 1/5th of NMC structure, but the condition that the zero-regulator resistor that this structure is used must very little guarantee zero limit separates, and in high frequency C M1And C M2Feedforward action can make the amplitude-frequency characteristic variation, so this structure can not satisfy the requirement of very large bandwidth.
Fig. 3 is the structured flowchart of three grades of transconductance capacitor compensation techniques in the background technology, and third stage amplifier comprises first order amplifier D1, second level amplifier D2, third level amplifier D3.The mutual conductance of this third stage amplifier is respectively g M1, g M2And g M3, output resistance is respectively R 1, R 2And R 3, the lump output capacitance is C 1, C 2And C LMiller-compensated capacitor C M1Be connected across the output of D1 and the output of D3.Miller-compensated capacitor C M2Be connected across output and the D4 two ends of D3, transconductance stage D4, its mutual conductance is g MtBe connected across output and the C of D2 M2Two ends.The third stage amplifier of this structure has adopted a mutual conductance g MtIntercepted C M2Short-circuiting effect when high frequency, the gain when having improved high frequency and PSRR.But this structure generally is to be applied in the situation that drives large capacitive load and resistive load, and bandwidth has larger advantage in the time of not high, when driving smaller capacitive but when requiring very high bandwidth and low-power consumption, and first miller-compensated resistance C M1Short-circuiting effect when high frequency will display, and the parasitic poles of second level mutual conductance collocation structure also can affect the stability of amplifier, has hindered the requirement that realizes the low-power consumption high bandwidth.
Summary of the invention
The purpose of this invention is to provide a kind ofly than low supply voltage (1.2V and following) time, have the three-stage frequency-compensated operational amplifier of high bandwidth, high-gain, low-power consumption.
High-bandwidth low-power consumption three-stage frequency-compensated operational amplifier provided by the invention comprises: input stage, and the second level, current source, output stage, the common-mode feedback level, compensating circuit, and inner feed forward circuit, wherein:
Input stage is used for receiving input signal and amplification;
The second level is connected in input stage, amplifies the signal of input stage output;
Current source is used for providing current source load to the first order and the second level;
The difference output stage is connected in the second level, amplifies the signal of second level output and drives external load circuit;
The common-mode feedback level is taken out the common mode electrical level of difference output stage and common mode electrical level is stablized;
Compensating circuit comprises: the first building-out capacitor, and the second building-out capacitor, the mutual conductance compensating circuit, high frequency zero limit discrete resistor, wherein:
The second building-out capacitor is connected between output stage output and the mutual conductance compensating circuit;
The mutual conductance compensating circuit is connected between second level output and the second building-out capacitor, the short circuit of building-out capacitor and feedforward effect when eliminating high frequency;
High frequency zero limit discrete resistor is connected among the first building-out capacitor and the output stage output, and the feedforward effect that reduces the first building-out capacitor when frequency is very high produces zero limit and separates;
The inside feed forward circuit is used for the inner extra limit of compensation also and output stage consists of push-pull circuit, to reduce quiescent dissipation.
Among the present invention, the amplifier second level comprises current mirroring circuit and mutual conductance transistor.Current mirroring circuit provides current source load; The mutual conductance transistor is connected to output and the current mirroring circuit of the first order, increases mutual conductance by the current mirror mirror image, and second level gain is provided.
Among the present invention, the mutual conductance compensating circuit of compensating circuit and the output that is connected building-out capacitor and is connected to the second level and the 3rd utmost point.
Among the present invention, in traditional mutual conductance compensating circuit and miller-compensated circuit increased by zero limit discrete resistor, it is connected in the middle of input stage output and the first building-out capacitor, has improved in the time of high frequency the compensation to parasitic zero limit.
Among the present invention, the common-mode feedback level comprises sampling resistor, and sampling common mode electrical level input transistors is with reference to common mode electrical level input transistors and load current mirror transistor.Wherein: sampling resistor is connected in the output stage difference output end; Sampling common mode electrical level input transistors is connected between sampling resistor mid point and the load current mirror transistor; Be connected in input stage current mirror load and reference voltage input terminal with reference to the common mode electrical level input transistors.The part of input stage that whole common mode feedback loop is multiplexing, the second level and output stage have whole realized under the condition that consumes very little dc power and difference is inputted similar DC current gain and AC characteristic.
Among the present invention, inner feed forward circuit transistor is connected between the output and output stage transistor of the first order, further compensated inner zero limit, improved phase margin, and and multiplexing one road direct current of output stage transistor, consist of push-pull circuit, increased the slew rate of operational amplifier, further reduced the needed dc power of output stage.
Three-stage operational amplifier provided by the invention can less load (pF level) obtain very high gain and the bandwidth of upper Gigahertz in lower power consumption.
Description of drawings
Fig. 1 is the structured flowchart of three grades of miller-compensated technology in the background technology.
Fig. 2 is the structured flowchart of three grades of mutual conductances and the miller-compensated technology of zero-regulator resistor in the background technology.
Fig. 3 is the structured flowchart of three grades of transconductance capacitor compensation techniques in the background technology.
Fig. 4 is the structured flowchart of three-stage frequency-compensated operational amplifier of the present invention.
Fig. 5 is the circuit diagram of three grades of fully differential frequency-compensated operational amplifiers of example according to the present invention.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing and example.
Fig. 4 is the structured flowchart of three-stage frequency-compensated operational amplifier of the present invention, and third stage amplifier comprises first order amplifier N1, second level amplifier N2, third level amplifier N3.The mutual conductance of this third stage amplifier is respectively g M1, g M2And g M3, output resistance is respectively R 1, R 2And R 3, the lump output capacitance is C 1, C 2And C 3, load capacitance is C LTransconductance stage N4 and feedforward transconductance level N5, their mutual conductance is respectively g MtAnd g MfMiller-compensated capacitor C M1Be connected across output and the high frequency zero limit discrete resistor R of N3 sBetween.High frequency zero limit discrete resistor R sBe connected across N1 output and miller-compensated capacitor C M1Between.Miller-compensated capacitor C M2Be connected across output and the N4 two ends of N3, N4 is connected across output and the C of N2 M2Two ends.Feedforward transconductance level N5 is connected across N1 output and N3 output two ends.Mutual conductance g MtIntercepted C M2Short-circuiting effect when high frequency, be eliminated g the zero point that the feedforward effect produces M3Can obtain smaller.But when frequency is very high, C M1Short-circuiting effect when high frequency has manifested out, at this moment requires again g M3Larger guarantee is stable, so need to be at building-out capacitor C M1Branch road on increase by zero a limit discrete resistor R s, we can be referred to as high frequency zero limit discrete resistor.The zero point that endoparasitic electric capacity can produce RHP when very high frequency, can be by adjusting the zero point of feedforward transconductance cancellation RHP, guaranteed Systems balanth, and this one-level can consist of push-pull configuration with afterbody and increased slew rate, reduce dc power.
Because parasitic capacitance C in the third stage amplifier 1, C 2And C 3Be generally tens flying methods (fF), still can satisfy miller-compensated capacitor C M1, C M2With load capacitance C L＞＞C 1, C 2, C 3So the open loop Frequency Response of the frequency-compensation three-stage amplifier that provides in the invention is as follows:
A v ( s ) = A dc ( 1 + s ω 4 + s 2 ω 4 ω 5 + s 3 ω 4 ω 5 ω 6 ) ( 1 + s ω d ) ( 1 + s ω 1 + s 2 ω 1 ω 2 + s 3 ω 1 ω 2 ω 3 ) - - - ( 2 )
DC current gain A Dc=g M1g M2g M3R 1R 2R 3, dominant pole ω d=1/C M1g M2g M3R 1R 2R 3, non-dominant pole ω 1=g M2/ [(1+a) C M2], ω 2=(1+a) C M2g M3/ C 2C L, ω 3=g M2/ aC M2Zero point ω 4=g M2/ aC M2, ω 5=-C M2/ [C 2C M1(g Mt/ g M2g M3-R s)], ω 6=g M2/ aC M2, a=g wherein M2/ g Mt, unity gain bandwidth is g M1/ C M1The a value is generally between 1-3.Can obtain non-dominant pole ω by top zero limit observation 3With Left half-plane ω at zero point 4Just in time offset non-dominant pole ω 2Very high can ignoring, non-dominant pole ω 1With Left half-plane ω at zero point 6More approaching, the phase margin loss that they cause is less.By C M1The RHP limit that feedforward produces when high frequency can be by regulating R sEliminate.Mutual conductance compensated stage g when high frequency in the compensating circuit MtGrid leak parasitic capacitance and Cm2 zero point that can regenerate together RHP, so add one-level feed forward circuit g MfAdjust the RHP zero point that endophyte produces, it does not affect the distribution of original limit, structurally can also consist of push-pull circuit with output stage, reduces power consumption.Amplifier is similar to one-pole system substantially in the time of design, mutual conductance for the second level and output stage does not require, can reduce greatly like this demand to dc power, be applicable to the design of low-power consumption, effect when in design, not only having considered low frequency simultaneously, all careful considerations of the feedforward effect of master's building-out capacitor and ghost effect can realize the design of high bandwidth during to high frequency.
Fig. 5 is the circuit diagram of three grades of fully differential frequency-compensated operational amplifiers of example according to the present invention.Amplifier is divided into several parts of input stage, the second level, output stage, common-mode feedback and compensating network and consists of, and design (calculated) load is 1.5pF, and bandwidth is 1.2GHz.With reference to figure 5, input stage comprises MP0a, MP2a-MN4a, MP2b-MP4b and MN1a, MN1b.The second level comprises MN2a-MN5a, MN2b-MN5b and MP5a, MP5b, and MN2a-MN5a, MN2b-MN5b have consisted of current mirror, can provide current mirror load for the second level.Output stage comprises MP8a and MP8b, and the feedforward transconductance level comprises MN7a and MN7b, and these two modules have consisted of push-pull circuit together.Compensated stage comprises the first building-out capacitor C M1With high frequency zero limit discrete resistor R s, the second building-out capacitor C M2With MP6a, MP6b, MP7a and MP7b, MP6a and MP6b are mutual conductance g Mt, MP7a and MP7b are that constant-current source provides bias current.The common-mode feedback level is made of MP0b, MP1a, MP1b, MP1c and MN1c.
In input stage, 9 transistors have consisted of the Foldable cascade structure, and input is g to the mutual conductance of pipe MP2a and MP2b in this structure M1, the difference between difference input voltage vinp and the vinn can be through amplifying the input that is input to the second level from the drain terminal of MP3a and MP3b.
The mutual conductance of MP5a and MP5b is g in the second level M2/ n, n are the ratio of load current mirror, can produce g by this way M2Electric current be reduced into original 1/n, by 1: the mirror image of n can obtain g M2, saved dc power.The direct current of mirror image also provides current circuit for transconductance stage in the collocation structure, does not need other DC channel, so that electric current obtains is multiplexing.
The second building-out capacitor one end is connected to the drain terminal of output stage MP8a or MP8b in the compensating circuit, and the other end is connected to MP6a or MP6b, and the mutual conductance of MP6a and MP6b is g Mt, these two transistorized drain terminals are connected to the output of the second level, can avoid C when higher-frequency like this M2The feedforward effect.The first building-out capacitor one end also is linked to the drain terminal of output stage MP8a or MP8b, and the other end is connected to high frequency zero limit discrete resistor R s, R sReceive the drain terminal of input stage MP3a and MP3b.The RHP that produces like this is zero point: ω 5=-C M2/ [C 2C M1(g Mt/ g M2g M3-R s)], can find out and work as R s＞g Mt/ g M2g M3In time, can eliminate this RHP zero point.
The common mode electrical level that samples in the common mode feedback circuit is connected to the grid end of MP1a, carries out FEEDBACK CONTROL by the grid end that relatively control signal is fed back to input stage MN1a and MN1b with desirable common-mode signal.Can in the situation that consumes very little electric current, make common mode feedback bandwidth reach more than 2/3 of difference mode signal bandwidth by this feedback system.
Compare with traditional three-stage frequency-compensated amplifier, the three-stage frequency-compensated amplifier shown in the present invention has been realized very large bandwidth under the lower power consumption condition, and third stage amplifier also can provide very high gain simultaneously.This operational amplifier is applicable to satisfy its requirement to high-gain high-bandwidth low-power consumption operational amplifier in the analog to digital converter at a high speed in the more and more lower situation of supply voltage.

Claims (6)

1. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier is characterized in that comprising: input stage, and the second level, current source, output stage, the common-mode feedback level, compensating circuit, and inner feed forward circuit, wherein:
Input stage is used for receiving input signal and amplification;
The second level is connected in input stage, amplifies the signal of input stage output;
Current source is used for providing current source load to input stage and the second level;
Output stage is connected in the second level, amplifies the signal of second level output and drives external load circuit;
The common-mode feedback level is taken out the common mode electrical level of output stage and common mode electrical level is stablized;
Compensating circuit comprises: the first building-out capacitor, and the second building-out capacitor, the mutual conductance compensating circuit, high frequency zero limit discrete resistor, wherein:
The second building-out capacitor is connected between output stage output and the mutual conductance compensating circuit;
The mutual conductance compensating circuit is connected between second level output and the second building-out capacitor, the short circuit of the second building-out capacitor and feedforward effect when eliminating high frequency;
The first building-out capacitor is connected between high frequency zero limit discrete resistor and the output stage;
High frequency zero limit discrete resistor is connected between the first building-out capacitor and the output stage output, and the feedforward effect that reduces the first building-out capacitor when frequency is very high produces zero limit and separates;
Inner feed forward circuit, be used for inner extra zero point of compensation and and output stage formation push-pull circuit reduce quiescent dissipation.
2. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier according to claim 1 is characterized in that, this second level comprises current mirroring circuit, and current source load is provided; The mutual conductance transistor is connected to output and the current mirroring circuit of input stage, increases mutual conductance by the current mirror mirror image, and second level gain is provided.
3. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier according to claim 1 is characterized in that, the mutual conductance compensating circuit in the compensating circuit and the second building-out capacitor are connected to the output of the second level and output stage.
4. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier according to claim 1, it is characterized in that, in mutual conductance compensating circuit and miller-compensated circuit, increased by zero limit discrete resistor, should zero limit discrete resistor be connected in the middle of input stage output and the first building-out capacitor, to improve the high frequency time compensation to parasitic zero limit.
5. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier according to claim 1, it is characterized in that, inner feed forward circuit transistor is connected between the output and output stage transistor of input stage, and and multiplexing one road direct current of output stage transistor, consist of push-pull circuit.
6. high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier according to claim 1 is characterized in that, the common-mode feedback level comprises sampling resistor, sampling common mode electrical level input transistors, with reference to common mode electrical level input transistors and load current mirror transistor; Wherein: sampling resistor is connected in the output of output stage; Sampling common mode electrical level input transistors is connected between sampling resistor and the load current mirror transistor; Be connected in current source load and the reference voltage input terminal of input stage with reference to the common mode electrical level input transistors; The part of the multiplexing input stage of whole common mode feedback loop, the second level and output stage whole.
CN2010102458533A 2010-08-05 2010-08-05 High-bandwidth low-power consumption frequency-compensation three-stage operational amplifier Expired - Fee Related CN101917169B (en)

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CN115149910B (en) * 2022-09-06 2023-01-24 中国电子科技集团公司第五十八研究所 Capacitance multiplication frequency compensation circuit for three-stage operational amplifier
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